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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-06-09 21:59:27 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-06-09 21:59:27 +0000 |
| commit | f655bf7f3e0c608f4b9cae1ee76e2be5477f4df6 (patch) | |
| tree | 0338f216152ede4b53c77123a11822d6bd8ac1fc /src/superio/NSC | |
| parent | 032211593248d4d9a569ecfd269a2433ea5b1c7c (diff) | |
| download | coreboot-f655bf7f3e0c608f4b9cae1ee76e2be5477f4df6.tar.xz | |
Moved from freebios
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/NSC')
| -rw-r--r-- | src/superio/NSC/pc97307/superio.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/superio/NSC/pc97307/superio.c b/src/superio/NSC/pc97307/superio.c new file mode 100644 index 0000000000..0a04806a8b --- /dev/null +++ b/src/superio/NSC/pc97307/superio.c @@ -0,0 +1,47 @@ +/* $Id$ */ +/* Copyright 2000 AG Electronics Ltd. */ +/* This code is distributed without warranty under the GPL v2 (see COPYING) */ + +#include <ppc.h> +#include <ppcreg.h> +#include <types.h> +#include <pci.h> +#include <arch/io.h> + +#ifndef PNP_INDEX_REG +#define PNP_INDEX_REG 0x15C +#endif +#ifndef PNP_DATA_REG +#define PNP_DATA_REG 0x15D +#endif +#ifndef SIO_COM1 +#define SIO_COM1_BASE 0x3F8 +#endif +#ifndef SIO_COM2 +#define SIO_COM2_BASE 0x2F8 +#endif + +void pnp_output(char address, char data) +{ + outb(address, PNP_INDEX_REG); + outb(data, PNP_DATA_REG); +} + +void sio_enable(void) +{ + /* Enable Super IO Chip */ + pnp_output(0x07, 6); /* LD 6 = UART1 */ + pnp_output(0x30, 0); /* Dectivate */ + pnp_output(0x60, SIO_COM1_BASE >> 8); /* IO Base */ + pnp_output(0x61, SIO_COM1_BASE & 0xFF); /* IO Base */ + pnp_output(0x30, 1); /* Activate */ +} + +struct superio_control superio_NSC_pc97307_control = { + pre_pci_init: (void *)0, + init: (void *)0, + finishup: (void *)0, + defaultport: SIO_COM1_BASE, + name: "NSC 87307" +}; + |