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| author | Eric Biederman <ebiederm@xmission.com> | 2003-06-17 08:42:17 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2003-06-17 08:42:17 +0000 |
| commit | 8d9c123812492a80a43112c8dd217fcfb3cee2c5 (patch) | |
| tree | 0bc841279e289f958d85cc8f2873b42770ecbce1 /src/superio/NSC | |
| parent | f96a810f11681ba436b446e9451e02cffcd525f5 (diff) | |
| download | coreboot-8d9c123812492a80a43112c8dd217fcfb3cee2c5.tar.xz | |
- Minor mod to reset16.inc to work with newer binutils hopefully this works with older ones...
- Update apic.h to include the APIC_TASK_PRI register definition
- Update mptable.c to have a reasonable board OEM and productid
- Additional testfiles for romcc.
- Split out auto.c and early failover.c moving their generic bits elsewere
- Enable cache of the rom
- Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/NSC')
0 files changed, 0 insertions, 0 deletions