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| author | Frans Hendriks <fhendriks@eltan.com> | 2018-11-26 10:33:00 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-05-24 07:22:23 +0000 |
| commit | 2e1fea408d8c7287497f0846715ee933fa9449f0 (patch) | |
| tree | 55a7143e2ef89376316ab95a687e4313e6fe8e20 /src/superio/aspeed/common/aspeed.h | |
| parent | 3d84038d57d606945403b3a1e4759dff359a7a7d (diff) | |
| download | coreboot-2e1fea408d8c7287497f0846715ee933fa9449f0.tar.xz | |
superio: Add ASpeed AST2400
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/superio/aspeed/common/aspeed.h')
| -rw-r--r-- | src/superio/aspeed/common/aspeed.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h new file mode 100644 index 0000000000..d3774eab3e --- /dev/null +++ b/src/superio/aspeed/common/aspeed.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com> + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H +#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <device/pnp_type.h> +#include <stdint.h> + +void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase); + +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); + +#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */ |