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author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-08 15:16:30 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-08 15:16:30 +0000 |
commit | 5c6bae213ea55e1436e010706560d86120b0b286 (patch) | |
tree | 48373faf8bc3a9e0628eeb1002508402c5b9299e /src/superio/ite/it8673f/it8673f_early_serial.c | |
parent | 6018e1ba7f797db3a7f1ae34bdb10ec1fa5c8a6c (diff) | |
download | coreboot-5c6bae213ea55e1436e010706560d86120b0b286.tar.xz |
Random ITE Super I/O fixes.
- Drop some of the less useful / outdated / duplicated comments.
- Simplify and streamline some code to look like the other Super I/Os.
- Use u8/16/etc. everywhere.
- ITE IT8718F: Add missing GPIO LDN.
- Add missing braces around SIO_DATA #defines, potential bug even.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/ite/it8673f/it8673f_early_serial.c')
-rw-r--r-- | src/superio/ite/it8673f/it8673f_early_serial.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/src/superio/ite/it8673f/it8673f_early_serial.c b/src/superio/ite/it8673f/it8673f_early_serial.c index 9edbfb9adc..37d4c74f1d 100644 --- a/src/superio/ite/it8673f/it8673f_early_serial.c +++ b/src/superio/ite/it8673f/it8673f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -34,18 +34,18 @@ #define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */ -/* Special values used for entering MB PnP mode. The first four bytes of - each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8673f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8673F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -53,10 +53,10 @@ static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8673F Super I/O chip. */ -static void it8673f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8673f_enable_serial(device_t dev, u16 iobase) { - uint8_t i; + int i; /* (1) Enter the configuration state (MB PnP mode). */ @@ -70,15 +70,14 @@ static void it8673f_enable_serial(device_t dev, unsigned iobase) outb(0x55, IT8673F_CONFIGURATION_PORT); /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) { + for (i = 0; i < 32; i++) outb(init_values[i], SIO_BASE); - } /* (2) Modify the data of configuration registers. */ /* Enable all devices. */ - it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (clear bit 0). */ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); |