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author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-08 15:16:30 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-08 15:16:30 +0000 |
commit | 5c6bae213ea55e1436e010706560d86120b0b286 (patch) | |
tree | 48373faf8bc3a9e0628eeb1002508402c5b9299e /src/superio/ite/it8718f/it8718f_early_serial.c | |
parent | 6018e1ba7f797db3a7f1ae34bdb10ec1fa5c8a6c (diff) | |
download | coreboot-5c6bae213ea55e1436e010706560d86120b0b286.tar.xz |
Random ITE Super I/O fixes.
- Drop some of the less useful / outdated / duplicated comments.
- Simplify and streamline some code to look like the other Super I/Os.
- Use u8/16/etc. everywhere.
- ITE IT8718F: Add missing GPIO LDN.
- Add missing braces around SIO_DATA #defines, potential bug even.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/ite/it8718f/it8718f_early_serial.c')
-rw-r--r-- | src/superio/ite/it8718f/it8718f_early_serial.c | 55 |
1 files changed, 23 insertions, 32 deletions
diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c index c3a8c73264..76f9b0daf6 100644 --- a/src/superio/ite/it8718f/it8718f_early_serial.c +++ b/src/superio/ite/it8718f/it8718f_early_serial.c @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -33,11 +33,7 @@ #define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8718F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8718f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -47,63 +43,58 @@ static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) static void it8718f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8718F_CONFIGURATION_PORT); - outb(0x01, IT8718F_CONFIGURATION_PORT); - outb(0x55, IT8718F_CONFIGURATION_PORT); - outb(0x55, IT8718F_CONFIGURATION_PORT); + u16 port = 0x2e; /* TODO: Don't hardcode! */ + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void it8718f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); } +/* Select 24MHz CLKIN (48MHz default). */ void it8718f_24mhz_clkin(void) { it8718f_enter_conf(); - - /* Select 24MHz CLKIN (48MHZ default)*/ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); - it8718f_exit_conf(); } -/* GIGABYTE uses a special SuperIO register to protect its Dual BIOS +/* + * GIGABYTE uses a special Super I/O register to protect its Dual BIOS * mechanism. It lives in the GPIO LDN. However, register 0xEF is not - * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for - * now. + * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ void it8718f_disable_reboot(void) { it8718f_enter_conf(); - - it8718f_sio_write(0x07, 0xEF, 0x7E); - + it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); it8718f_exit_conf(); } -/* Enable the peripheral devices on the IT8718F Super I/O chip. */ -void it8718f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +void it8718f_enable_serial(device_t dev, u16 iobase) { /* (1) Enter the configuration state (MB PnP mode). */ it8718f_enter_conf(); /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ |