summaryrefslogtreecommitdiff
path: root/src/superio/ite/it8718f
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2010-11-08 15:16:30 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-08 15:16:30 +0000
commit5c6bae213ea55e1436e010706560d86120b0b286 (patch)
tree48373faf8bc3a9e0628eeb1002508402c5b9299e /src/superio/ite/it8718f
parent6018e1ba7f797db3a7f1ae34bdb10ec1fa5c8a6c (diff)
downloadcoreboot-5c6bae213ea55e1436e010706560d86120b0b286.tar.xz
Random ITE Super I/O fixes.
- Drop some of the less useful / outdated / duplicated comments. - Simplify and streamline some code to look like the other Super I/Os. - Use u8/16/etc. everywhere. - ITE IT8718F: Add missing GPIO LDN. - Add missing braces around SIO_DATA #defines, potential bug even. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/ite/it8718f')
-rw-r--r--src/superio/ite/it8718f/Makefile.inc2
-rw-r--r--src/superio/ite/it8718f/chip.h6
-rw-r--r--src/superio/ite/it8718f/it8718f.h8
-rw-r--r--src/superio/ite/it8718f/it8718f_early_serial.c55
-rw-r--r--src/superio/ite/it8718f/superio.c7
5 files changed, 33 insertions, 45 deletions
diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc
index c72bf8c434..e3369083d6 100644
--- a/src/superio/ite/it8718f/Makefile.inc
+++ b/src/superio/ite/it8718f/Makefile.inc
@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c
+
diff --git a/src/superio/ite/it8718f/chip.h b/src/superio/ite/it8718f/chip.h
index c230014b2f..b0ee40566c 100644
--- a/src/superio/ite/it8718f/chip.h
+++ b/src/superio/ite/it8718f/chip.h
@@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef _SUPERIO_ITE_IT8718F
-#define _SUPERIO_ITE_IT8718F
+#ifndef SUPERIO_ITE_IT8718F_CHIP_H
+#define SUPERIO_ITE_IT8718F_CHIP_H
#include <device/device.h>
#include <pc80/keyboard.h>
@@ -32,4 +32,4 @@ struct superio_ite_it8718f_config {
struct pc_keyboard keyboard;
};
-#endif /* _SUPERIO_ITE_IT8718F */
+#endif
diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h
index c441db3fbd..def5c52951 100644
--- a/src/superio/ite/it8718f/it8718f.h
+++ b/src/superio/ite/it8718f/it8718f.h
@@ -19,20 +19,20 @@
*/
/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */
-/* Status: Untested on real hardware, but it compiles. */
#define IT8718F_FDC 0x00 /* Floppy */
#define IT8718F_SP1 0x01 /* Com1 */
#define IT8718F_SP2 0x02 /* Com2 */
#define IT8718F_PP 0x03 /* Parallel port */
#define IT8718F_EC 0x04 /* Environment controller */
-#define IT8718F_KBCK 0x05 /* Keyboard */
-#define IT8718F_KBCM 0x06 /* Mouse */
+#define IT8718F_KBCK 0x05 /* PS/2 keyboard */
+#define IT8718F_KBCM 0x06 /* PS/2 mouse */
+#define IT8718F_GPIO 0x07 /* GPIO */
#define IT8718F_IR 0x0a /* Consumer IR */
#if defined(__PRE_RAM__) && !defined(__ROMCC__)
void it8718f_24mhz_clkin(void);
void it8718f_disable_reboot(void);
-void it8718f_enable_serial(device_t dev, unsigned iobase);
+void it8718f_enable_serial(device_t dev, u16 iobase);
#endif
diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c
index c3a8c73264..76f9b0daf6 100644
--- a/src/superio/ite/it8718f/it8718f_early_serial.c
+++ b/src/superio/ite/it8718f/it8718f_early_serial.c
@@ -24,7 +24,7 @@
/* The base address is 0x2e or 0x4e, depending on config bytes. */
#define SIO_BASE 0x2e
#define SIO_INDEX SIO_BASE
-#define SIO_DATA SIO_BASE+1
+#define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */
#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
@@ -33,11 +33,7 @@
#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
-#define IT8718F_CONFIGURATION_PORT 0x2e /* Write-only. */
-
-/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the
- LDN the register belongs to, before you can access the register. */
-static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
+static void it8718f_sio_write(u8 ldn, u8 index, u8 value)
{
outb(IT8718F_CONFIG_REG_LDN, SIO_BASE);
outb(ldn, SIO_DATA);
@@ -47,63 +43,58 @@ static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
static void it8718f_enter_conf(void)
{
- /* Enter the configuration state (MB PnP mode). */
-
- /* Perform MB PnP setup to put the SIO chip at 0x2e. */
- /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
- /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
- outb(0x87, IT8718F_CONFIGURATION_PORT);
- outb(0x01, IT8718F_CONFIGURATION_PORT);
- outb(0x55, IT8718F_CONFIGURATION_PORT);
- outb(0x55, IT8718F_CONFIGURATION_PORT);
+ u16 port = 0x2e; /* TODO: Don't hardcode! */
+
+ outb(0x87, port);
+ outb(0x01, port);
+ outb(0x55, port);
+ outb((port == 0x4e) ? 0xaa : 0x55, port);
}
static void it8718f_exit_conf(void)
{
- /* Exit the configuration state (MB PnP mode). */
it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02);
}
+/* Select 24MHz CLKIN (48MHz default). */
void it8718f_24mhz_clkin(void)
{
it8718f_enter_conf();
-
- /* Select 24MHz CLKIN (48MHZ default)*/
it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1);
-
it8718f_exit_conf();
}
-/* GIGABYTE uses a special SuperIO register to protect its Dual BIOS
+/*
+ * GIGABYTE uses a special Super I/O register to protect its Dual BIOS
* mechanism. It lives in the GPIO LDN. However, register 0xEF is not
- * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for
- * now.
+ * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now.
*/
void it8718f_disable_reboot(void)
{
it8718f_enter_conf();
-
- it8718f_sio_write(0x07, 0xEF, 0x7E);
-
+ it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E);
it8718f_exit_conf();
}
-/* Enable the peripheral devices on the IT8718F Super I/O chip. */
-void it8718f_enable_serial(device_t dev, unsigned iobase)
+/* Enable the serial port(s). */
+void it8718f_enable_serial(device_t dev, u16 iobase)
{
/* (1) Enter the configuration state (MB PnP mode). */
it8718f_enter_conf();
/* (2) Modify the data of configuration registers. */
- /* Select the chip to configure (if there's more than one).
- Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
- If this register is not written, both chips are configured. */
+ /*
+ * Select the chip to configure (if there's more than one).
+ * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+ * If this register is not written, both chips are configured.
+ */
+
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */
/* Enable serial port(s). */
- it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
- it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
+ it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */
+ it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */
/* Clear software suspend mode (clear bit 0). TODO: Needed? */
/* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */
diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c
index d0f971d233..3bf2f2fc65 100644
--- a/src/superio/ite/it8718f/superio.c
+++ b/src/superio/ite/it8718f/superio.c
@@ -28,14 +28,11 @@
static void init(device_t dev)
{
- struct superio_ite_it8718f_config *conf;
+ struct superio_ite_it8718f_config *conf = dev->chip_info;
struct resource *res0, *res1;
- if (!dev->enabled) {
+ if (!dev->enabled)
return;
- }
-
- conf = dev->chip_info;
switch (dev->path.pnp.device) {
case IT8718F_FDC: /* TODO. */