src/superio/ite/it8772f: Separate mainboard from SIO at obj level

Remove #include early_serial.c and rename to early_init.c as no actual
UART configuration is done here. Note that this SIO component still
hard codes its base address to 0x2e.

Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6271
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 87 insertions, 0 deletions

diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c
new file mode 100644
index 0000000000..1ae80c8294
--- /dev/null
+++ b/src/superio/ite/it8772f/early_init.c
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+
+#include "it8772f.h"
+
+/* NOTICE: This file is deprecated, use ite/common instead */
+
+/* RAMstage equiv */
+/* u8 pnp_read_config(device_t dev, u8 reg) */
+u8 it8772f_sio_read(device_t dev, u8 reg)
+{
+	u16 port = dev >> 8;
+
+	outb(reg, port);
+	return inb(port + 1);
+}
+
+/* RAMstage equiv */
+/* void pnp_write_config(device_t dev, u8 reg, u8 value) */
+void it8772f_sio_write(device_t dev, u8 reg, u8 value)
+{
+	u16 port = dev >> 8;
+
+	outb(reg, port);
+	outb(value, port + 1);
+}
+
+void it8772f_enter_conf(device_t dev)
+{
+	u16 port = dev >> 8;
+
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+void it8772f_exit_conf(device_t dev)
+{
+	it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02);
+}
+
+/* Set AC resume to be up to the Southbridge */
+void it8772f_ac_resume_southbridge(device_t dev)
+{
+	it8772f_enter_conf(dev);
+	it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC);
+	it8772f_sio_write(dev, 0xf4, 0x60);
+	it8772f_exit_conf(dev);
+}
+
+/* Configure a set of GPIOs */
+void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity,
+			u8 pullup, u8 output, u8 enable)
+{
+	set--; /* Set 1 is offset 0 */
+	it8772f_enter_conf(dev);
+	it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+	if (set < 5) {
+		it8772f_sio_write(dev, GPIO_REG_SELECT(set), select);
+		it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable);
+		it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity);
+	}
+	it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output);
+	it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup);
+	it8772f_exit_conf(dev);
+}