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authorFurquan Shaikh <furquan@google.com>2019-02-05 14:03:44 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-07 08:52:07 +0000
commita08765d2871b891c8da2e8686a0db35b320c96b0 (patch)
treea243942b77a637a7e88fdd9ac4794c8412ef5f49 /src/superio/ite
parent86d2afb86b5c76fe8da719ce7746609eb1109ff0 (diff)
downloadcoreboot-a08765d2871b891c8da2e8686a0db35b320c96b0.tar.xz
mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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