add PC87384 SuperIO

Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 161 insertions, 0 deletions

diff --git a/src/superio/nsc/pc87384/Makefile.inc b/src/superio/nsc/pc87384/Makefile.inc
new file mode 100644
index 0000000000..b57748947b
--- /dev/null
+++ b/src/superio/nsc/pc87384/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_NSC_PC87384) += superio.c
+
diff --git a/src/superio/nsc/pc87384/chip.h b/src/superio/nsc/pc87384/chip.h
new file mode 100644
index 0000000000..4eaa92f3ec
--- /dev/null
+++ b/src/superio/nsc/pc87384/chip.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87384_CHIP_H
+#define SUPERIO_NSC_PC87384_CHIP_H
+
+#include <uart8250.h>
+extern struct chip_operations superio_nsc_pc87384_ops;
+
+struct superio_nsc_pc87384_config {
+	struct uart8250 com1, com2;
+};
+
+#endif
diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h
new file mode 100644
index 0000000000..fe573b7773
--- /dev/null
+++ b/src/superio/nsc/pc87384/pc87384.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_NSC_PC87384_H
+#define SUPERIO_NSC_PC87384_H
+
+#define PC87384_PP   0x01
+#define PC87384_SP2  0x02
+#define PC87384_SP1  0x03
+#define PC87384_GPIO 0x07
+#endif
diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c
new file mode 100644
index 0000000000..5bd318fb3d
--- /dev/null
+++ b/src/superio/nsc/pc87384/superio.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "pc87384.h"
+
+static void init(device_t dev)
+{
+	struct superio_nsc_pc87384_config *conf = dev->chip_info;
+	struct resource *res0;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case PC87384_SP1:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com1);
+		break;
+	case PC87384_SP2:
+		res0 = find_resource(dev, PNP_IDX_IO0);
+		init_uart8250(res0->base, &conf->com2);
+		break;
+
+	case PC87384_GPIO:
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, PC87384_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} },
+	{ &ops, PC87384_SP1,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87384_SP2,  PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
+	{ &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nsc_pc87384_ops = {
+	CHIP_NAME("NSC PC87384 Super I/O")
+	.enable_dev = enable_dev,
+};