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authorSubrata Banik <subrata.banik@intel.com>2019-05-06 19:51:34 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-05-13 02:06:46 +0000
commit095c931cf12924da9011b47aa64f4a6f11d89f13 (patch)
tree3e4da8c0a4aca79f1e7bcd686a905e5e85655533 /src/superio/nsc
parenta6d401c193c9bb53162df9523f9ba4ebb2a6f1a7 (diff)
downloadcoreboot-095c931cf12924da9011b47aa64f4a6f11d89f13.tar.xz
src/arch/x86: Use core apic id to get cpu_index()
This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/nsc')
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