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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-03-22 11:24:45 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-04-01 23:27:21 +0200 |
| commit | a2d6a40480c97043e9126c0fbc9e1a79db22d408 (patch) | |
| tree | fe62358015161ca7c301276bd1e78d31d467b4ca /src/superio/renesas | |
| parent | 0ce2b4368286df8267bfb290b206671825981248 (diff) | |
| download | coreboot-a2d6a40480c97043e9126c0fbc9e1a79db22d408.tar.xz | |
lynxpoint: Fix LP clock gating setup for LPC
This bit offset is incorrect and should only be set based
on another bit in a different register.
Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2973
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/superio/renesas')
0 files changed, 0 insertions, 0 deletions