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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-04-17 16:13:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-19 07:52:43 +0000 |
| commit | 26be35a50720f7dc60aa6a28dae151b47cb782ce (patch) | |
| tree | f114b460a7c9346c183a726d7fa969765e8e997c /src/superio/serverengines | |
| parent | afabaede2c20d22fc00d40eddf3d0dd01a591932 (diff) | |
| download | coreboot-26be35a50720f7dc60aa6a28dae151b47cb782ce.tar.xz | |
soc/intel/cannonlake: Set DISB after Dram init
DRAM Initialization Scratchpad Bit needs to be set after Dram
Initialization finished, according to Cannonlake PCH-LP EDS(#565870)
chapter 5.3.1.
BUG=None
Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
Diffstat (limited to 'src/superio/serverengines')
0 files changed, 0 insertions, 0 deletions