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| author | Keith Hui <buurin@gmail.com> | 2017-09-04 15:47:40 -0400 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-03 15:24:24 +0000 |
| commit | b9c1a4e8d92b51881672d440ff8e00a5ba8a0ef2 (patch) | |
| tree | 26e5cba91d15addd6467eedf9c37078f8e402f06 /src/superio/serverengines | |
| parent | 427feecbf0003d968ac804edaac7cb25ac67b397 (diff) | |
| download | coreboot-b9c1a4e8d92b51881672d440ff8e00a5ba8a0ef2.tar.xz | |
sb/intel/i82371eb: Consolidate bootblock.c logic
The southbridge bootblock entry point bootblock_southbridge_init()
just calls i82371eb_enable_rom() which does all the work. Move all
that code into bootblock_southbridge_init() and drop the second
function.
Plus combine the 3 lines that set 3 bits in XBCS into one.
Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/superio/serverengines')
0 files changed, 0 insertions, 0 deletions