This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 285 insertions, 0 deletions

diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc
new file mode 100644
index 0000000000..19dc4694c9
--- /dev/null
+++ b/src/superio/smsc/kbc1100/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += superio.c
diff --git a/src/superio/smsc/kbc1100/chip.h b/src/superio/smsc/kbc1100/chip.h
new file mode 100644
index 0000000000..4ca90e360f
--- /dev/null
+++ b/src/superio/smsc/kbc1100/chip.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_KBC1100_CHIP_H
+#define SUPERIO_SMSC_KBC1100_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_kbc1100_ops;
+
+struct superio_smsc_kbc1100_config {
+	struct uart8250 com1, com2;
+	struct pc_keyboard keyboard;
+};
+
+#endif
\ No newline at end of file
diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h
new file mode 100644
index 0000000000..710fdc8097
--- /dev/null
+++ b/src/superio/smsc/kbc1100/kbc1100.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define KBC1100_PM1              1            /* PM1 */
+#define SMSCSUPERIO_SP1          4            /* Com1 */
+#define SMSCSUPERIO_SP2          5            /* Com2 */
+#define KBC1100_KBC              7            /* Keyboard */
+#define KBC1100_EC0              8            /* EC Channel 0 */
+#define KBC1100_MAILBOX          9            /* Mail Box */
+#define KBC1100_GPIO             0x0A         /* GPIO */
+#define KBC1100_SPI              0x0B         /* Share flash interface */
+
+#define KBC1100_EC1              0x0D         /* EC Channel 1 */
+#define KBC1100_EC2              0x0E         /* EC Channel 2 */
+
+
diff --git a/src/superio/smsc/kbc1100/kbc1100_early_init.c b/src/superio/smsc/kbc1100/kbc1100_early_init.c
new file mode 100644
index 0000000000..4247a96318
--- /dev/null
+++ b/src/superio/smsc/kbc1100/kbc1100_early_init.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/romcc_io.h>
+#include "kbc1100.h"
+
+static inline void pnp_enter_conf_state(device_t dev)
+{
+  unsigned port = dev>>8;
+  outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+  unsigned port = dev>>8;
+  outb(0xaa, port);
+}
+
+static inline void kbc1100_early_init(unsigned port)
+{
+  device_t dev;
+  dev = PNP_DEV (port, KBC1100_KBC);
+
+  pnp_enter_conf_state(dev);
+  
+  /* Serial IRQ enabled */
+  outb(0x25, port);
+  outb(0x04, port + 1);
+  
+  /* Enable SMSC UART 0 */
+  dev = PNP_DEV (port, SMSCSUPERIO_SP1);
+  pnp_set_logical_device(dev);
+  pnp_set_enable(dev, 0);
+  pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+  pnp_set_enable(dev, 1);
+
+  /* Enable keyboard */
+  dev = PNP_DEV (port, KBC1100_KBC);
+  pnp_set_logical_device(dev);
+  pnp_set_enable(dev, 0);
+  pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
+  pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
+  pnp_set_irq(dev, 0x70, 1);   /* IRQ 1 */
+  pnp_set_irq(dev, 0x72, 12);   /* IRQ 12 */
+  pnp_set_enable(dev, 1);
+
+  /* Enable EC Channel 0 */
+  dev = PNP_DEV (port, KBC1100_EC0);
+  pnp_set_logical_device(dev);
+  pnp_set_enable(dev, 1);
+
+  pnp_exit_conf_state(dev);
+
+  /* disable the 1s timer */
+  outb(0xE7, 0x64);  
+}
+
diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c
new file mode 100644
index 0000000000..bd330bac4a
--- /dev/null
+++ b/src/superio/smsc/kbc1100/superio.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "kbc1100.h"
+
+/* Forward declarations */
+static void enable_dev(device_t dev);
+static void kbc1100_pnp_set_resources(device_t dev);
+static void kbc1100_pnp_enable_resources(device_t dev);
+static void kbc1100_pnp_enable(device_t dev);
+static void kbc1100_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+struct chip_operations superio_smsc_kbc1100_ops = {
+  CHIP_NAME("SMSC KBC1100 Super I/O")
+  .enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+  .read_resources   = pnp_read_resources,
+  .set_resources    = kbc1100_pnp_set_resources,
+  .enable_resources = kbc1100_pnp_enable_resources,
+  .enable           = kbc1100_pnp_enable,
+  .init             = kbc1100_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+  { &ops, KBC1100_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+};
+
+static void enable_dev(device_t dev)
+{
+  pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+static void kbc1100_pnp_set_resources(device_t dev)
+{
+  pnp_enter_conf_state(dev);
+  pnp_set_resources(dev);
+  pnp_exit_conf_state(dev);
+}
+
+static void kbc1100_pnp_enable_resources(device_t dev)
+{
+  pnp_enter_conf_state(dev);
+  pnp_enable_resources(dev);
+  pnp_exit_conf_state(dev);
+}
+
+static void kbc1100_pnp_enable(device_t dev)
+{
+  pnp_enter_conf_state(dev);
+  pnp_set_logical_device(dev);
+
+  if(dev->enabled) {
+    pnp_set_enable(dev, 1);
+  }
+  else {
+    pnp_set_enable(dev, 0);
+  }
+  pnp_exit_conf_state(dev);
+}
+
+static void kbc1100_init(device_t dev)
+{
+  struct superio_smsc_kbc1100_config *conf = dev->chip_info;
+  struct resource *res0, *res1;
+
+  
+   
+  if (!dev->enabled) {
+    return;
+  }
+
+  switch(dev->path.pnp.device) {
+  
+  case KBC1100_KBC:
+    res0 = find_resource(dev, PNP_IDX_IO0);
+    res1 = find_resource(dev, PNP_IDX_IO1);
+    pc_keyboard_init(&conf->keyboard);
+    break;
+  }
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+  outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+  outb(0xaa, dev->path.pnp.port);
+}