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author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-14 21:48:14 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-14 21:48:14 +0000 |
commit | 2e9323e5bef293c051d9fd982214e6db2e3305ee (patch) | |
tree | 5db8a5fdf87ba5b3cd2c2ab5cc4ca8a62eaf73d3 /src/superio/smsc/lpc47m10x/superio.c | |
parent | 0675d5c34f90d0b2a3864d0f30461dfe696374f0 (diff) | |
download | coreboot-2e9323e5bef293c051d9fd982214e6db2e3305ee.tar.xz |
Add a target for the ASUS A8V-E Deluxe (trivial).
For now this is a plain copy of the ASUS A8V-E SE target, I reported
that most of the code also works (sort of) for the ASUS A8V-E Deluxe
a long while ago, see
http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html
http://www.coreboot.org/ASUS_A8V-E_Deluxe
There will be a bunch of changes necessary though (devicetree.cb, mptable.c,
ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target.
Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as
otherwise there will be build errors if the MAINBOARD_PART_NUMBER string
gets too long (as is the case for "A8V-E Deluxe"). The error is:
ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps
section .romstrap loaded at [00000000ffffff80,00000000ffffffd3]
(both with stock Debian gcc and with xgcc)
Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/smsc/lpc47m10x/superio.c')
0 files changed, 0 insertions, 0 deletions