summaryrefslogtreecommitdiff
path: root/src/superio/smsc/lpc47m10x
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2010-11-15 19:35:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-15 19:35:14 +0000
commita69d978be8a068944466e776de87527fb104a878 (patch)
tree8acf4247e3104ad9ccb940568a81e472105a674b /src/superio/smsc/lpc47m10x
parent2e9323e5bef293c051d9fd982214e6db2e3305ee (diff)
downloadcoreboot-a69d978be8a068944466e776de87527fb104a878.tar.xz
C and other Super I/O cosmetic fixes.
- Random coding style, whitespace and cosmetic fixes. - Consistently use the same spacing and 4-hexdigit port number format in the pnp_dev_info[] arrays. - Drop dead/unused code and less useful comments. - Add missing "(C)" characters and copyright years. - Shorten and simplify some code snippets. - Use u8/u16/etc. everywhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/smsc/lpc47m10x')
-rw-r--r--src/superio/smsc/lpc47m10x/Makefile.inc2
-rw-r--r--src/superio/smsc/lpc47m10x/lpc47m10x.h4
-rw-r--r--src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c13
-rw-r--r--src/superio/smsc/lpc47m10x/superio.c58
4 files changed, 33 insertions, 44 deletions
diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc
index 578a8a73d2..3f716018c8 100644
--- a/src/superio/smsc/lpc47m10x/Makefile.inc
+++ b/src/superio/smsc/lpc47m10x/Makefile.inc
@@ -22,5 +22,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-#config chip.h
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c
+
diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h
index 604016c0e0..4c78d9e632 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x.h
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h
@@ -28,9 +28,9 @@
#define LPC47M10X2_SP1 4 /* Com1 */
#define LPC47M10X2_SP2 5 /* Com2 */
#define LPC47M10X2_KBC 7 /* Keyboard & Mouse */
-#define LPC47M10X2_GAME 9 /* GAME */
+#define LPC47M10X2_GAME 9 /* GAME */
#define LPC47M10X2_PME 10 /* PME reg*/
-#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/
+#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ // FIXME
#define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F
diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
index e2aa63ab94..06cf7d4030 100644
--- a/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
+++ b/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c
@@ -1,6 +1,5 @@
/*
- * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip
- * derived from lpc47n217
+ * This file is part of the coreboot project.
*
* Copyright (C) 2005 Digital Design Corporation
*
@@ -22,17 +21,15 @@
#include <arch/romcc_io.h>
#include "lpc47m10x.h"
-/** Enable access to the LPC47M10X2's configuration registers. */
-static inline void pnp_enter_conf_state(device_t dev)
+static void pnp_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0x55, port);
}
-/** Disable access to the LPC47M10X2's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ u16 port = dev >> 8;
outb(0xaa, port);
}
@@ -43,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev)
* @param dev High 8 bits = Super I/O port, low 8 bits = logical device number.
* @param iobase Processor I/O port address to assign to this serial device.
*/
-static void lpc47m10x_enable_serial(device_t dev, unsigned iobase)
+static void lpc47m10x_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c
index 1cb7e7d262..c935d628cf 100644
--- a/src/superio/smsc/lpc47m10x/superio.c
+++ b/src/superio/smsc/lpc47m10x/superio.c
@@ -1,11 +1,11 @@
/*
- * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip
+ * This file is part of the coreboot project.
*
- * Copyright 2000 AG Electronics Ltd.
- * Copyright 2003-2004 Linux Networx
- * Copyright 2004 Tyan
+ * Copyright (C) 2000 AG Electronics Ltd.
+ * Copyright (C) 2003-2004 Linux Networx
+ * Copyright (C) 2004 Tyan
* Copyright (C) 2005 Digital Design Corporation
- * Copyright (C) Ron Minnich, LANL
+ * Copyright (C) 2006 Ron Minnich, LANL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -44,7 +44,7 @@ static void lpc47m10x_init(device_t dev);
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
-//static void dump_pnp_device(device_t dev);
+// static void dump_pnp_device(device_t dev);
struct chip_operations superio_smsc_lpc47m10x_ops = {
CHIP_NAME("SMSC LPC47M10x Super I/O")
@@ -60,11 +60,11 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
};
/**
@@ -103,13 +103,7 @@ static void lpc47m10x_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
-
- if(dev->enabled) {
- pnp_set_enable(dev, 1);
- }
- else {
- pnp_set_enable(dev, 0);
- }
+ pnp_set_enable(dev, (dev->enabled) ? 1 : 0);
pnp_exit_conf_state(dev);
}
@@ -134,25 +128,21 @@ static void lpc47m10x_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
-
case LPC47M10X2_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
-
case LPC47M10X2_KBC:
pc_keyboard_init(&conf->keyboard);
break;
}
}
-/** Enable access to the LPC47M10X2's configuration registers. */
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
-/** Disable access to the LPC47M10X2's configuration registers. */
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
@@ -168,30 +158,32 @@ static void pnp_exit_conf_state(device_t dev)
*/
static void dump_pnp_device(device_t dev)
{
- int register_index;
+ int i;
print_debug("\n");
- for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) {
- uint8_t register_value;
+ for (i = 0; i <= LPC47M10X2_MAX_CONFIG_REGISTER; i++) {
+ u8 register_value;
- if ((register_index & 0x0f) == 0) {
- print_debug_hex8(register_index);
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
print_debug_char(':');
}
- /* Skip over 'register' that would cause exit from configuration mode */
- if (register_index == 0xaa)
+ /*
+ * Skip over 'register' that would cause exit from
+ * configuration mode.
+ */
+ if (i == 0xaa)
register_value = 0xaa;
else
- register_value = pnp_read_config(dev, register_index);
+ register_value = pnp_read_config(dev, i);
print_debug_char(' ');
print_debug_hex8(register_value);
- if ((register_index & 0x0f) == 0x0f) {
+ if ((i & 0x0f) == 0x0f)
print_debug("\n");
- }
}
- print_debug("\n");
+ print_debug("\n");
}
#endif