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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-15 19:35:14 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-15 19:35:14 +0000
commita69d978be8a068944466e776de87527fb104a878 (patch)
tree8acf4247e3104ad9ccb940568a81e472105a674b /src/superio/via/vt1211
parent2e9323e5bef293c051d9fd982214e6db2e3305ee (diff)
downloadcoreboot-a69d978be8a068944466e776de87527fb104a878.tar.xz
C and other Super I/O cosmetic fixes.
- Random coding style, whitespace and cosmetic fixes. - Consistently use the same spacing and 4-hexdigit port number format in the pnp_dev_info[] arrays. - Drop dead/unused code and less useful comments. - Add missing "(C)" characters and copyright years. - Shorten and simplify some code snippets. - Use u8/u16/etc. everywhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/superio/via/vt1211')
-rw-r--r--src/superio/via/vt1211/vt1211.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c
index 09346fcdac..3cfeea66a4 100644
--- a/src/superio/via/vt1211/vt1211.c
+++ b/src/superio/via/vt1211/vt1211.c
@@ -205,17 +205,17 @@ struct device_operations ops = {
/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
static struct pnp_info pnp_dev_info[] = {
- { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
- { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
- { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
- { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
- { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, },
- { &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, },
- { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
- { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
- { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, },
- { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, },
- { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, },
+ { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+ { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
+ { &ops, VT1211_GAME, PNP_IO0, {0xfff8, 0}, },
+ { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+ { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+ { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
+ { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, {0xff00, 0}, },
+ { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff00, 0}, },
{ &ops, VT1211_ROM, },
};