W83627DHG/W83627EHG fixups for virtual LDNs.

W83627DHG:

 - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
   that don't have their "enable" bit in bit 0 of the 0x30 register).

 - Fix various I/O masks in the pnp_dev_info[] array as per
   datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.

W83627EHG:

 - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
   mostly implemented already, though).

 - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.

Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.

include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.

asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.

ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 20 insertions, 3 deletions

diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h
index 8a1668c4dc..74761e9884 100644
--- a/src/superio/winbond/w83627dhg/w83627dhg.h
+++ b/src/superio/winbond/w83627dhg/w83627dhg.h
@@ -25,13 +25,30 @@
 #define W83627DHG_PP               1   /* Parallel port */
 #define W83627DHG_SP1              2   /* Com1 */
 #define W83627DHG_SP2              3   /* Com2 */
-#define W83627DHG_KBC              5   /* PS/2 keyboard + mouse */
+#define W83627DHG_KBC              5   /* PS/2 keyboard & mouse */
 #define W83627DHG_SPI              6   /* Serial peripheral interface */
-#define W83627DHG_GPIO6            7   /* GPIO6 */
 #define W83627DHG_WDTO_PLED        8   /* WDTO#, PLED */
-#define W83627DHG_GPIO2345         9   /* GPIO2, GPIO3, GPIO4, GPIO5 */
 #define W83627DHG_ACPI            10   /* ACPI */
 #define W83627DHG_HWM             11   /* Hardware monitor */
 #define W83627DHG_PECI_SST        12   /* PECI, SST */
 
+/* The following are handled using "virtual LDNs" (hence the _V suffix). */
+#define W83627DHG_GPIO6_V          7   /* GPIO6 */
+#define W83627DHG_GPIO2345_V       9   /* GPIO2, GPIO3, GPIO4, GPIO5 */
+
+/*
+ * Virtual devices sharing the enables are encoded as follows:
+ *   VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
+ */
+
+/* GPIO6 has bit 3 as enable (instead of bit 0 as usual). */
+#define W83627DHG_GPIO6	((3 << 8) | W83627DHG_GPIO6_V)
+
+#define W83627DHG_GPIO2	((0 << 8) | W83627DHG_GPIO2345_V)
+#define W83627DHG_GPIO3	((1 << 8) | W83627DHG_GPIO2345_V)
+#define W83627DHG_GPIO4	((2 << 8) | W83627DHG_GPIO2345_V)
+#define W83627DHG_GPIO5	((3 << 8) | W83627DHG_GPIO2345_V)
+
+/* Note: There is no GPIO1 on the W83627DHG as per datasheet. */
+
 #endif