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| author | Nico Huber <nico.huber@secunet.com> | 2013-05-14 15:25:26 +0200 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-06-18 19:15:12 +0200 |
| commit | cacc58a874092bbbd680cd636ed840c1844c84a1 (patch) | |
| tree | e3c1921f1eef2d764e049689155f87a9ce02de61 /src/superio/winbond/w83627dhg | |
| parent | df8d27357f7a23a2f840b3d2af7b67229c16e42b (diff) | |
| download | coreboot-cacc58a874092bbbd680cd636ed840c1844c84a1.tar.xz | |
winbond/w83627dhg: Correct resource setting for SPI (LDN6)
The SPI logical device on the W83627DHG uses the second i/o port
register pair but not the first one. So we have to also set `io1`
(the second io_info struct) and not `io0` in the pnp_info structure.
Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to
hang in pnp_enable_devices() until commit aeead274 which added a
check for an unset mask.
Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3391
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/superio/winbond/w83627dhg')
| -rw-r--r-- | src/superio/winbond/w83627dhg/superio.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1a83b3d010..537d83490f 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -85,8 +85,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, - /* the next line makes coreboot hang in pnp_enable_devices() */ - /* { &ops, W83627DHG_SPI, PNP_IO1, { 0x7f8, 0 }, }, */ + { &ops, W83627DHG_SPI, PNP_IO1, {}, { 0x7f8, 0 }, }, { &ops, W83627DHG_GPIO6, }, { &ops, W83627DHG_WDTO_PLED, }, { &ops, W83627DHG_GPIO2, }, |