Random Winbond Super I/O cosmetic and coding-style fixes.

 - Whitespace, coding style, and typo fixes.

 - Drop unused/obsolete "#config chip.h".

 - Use u8/u16/etc. everywhere.

 - Use pnp_read_config()/pnp_write_config() instead of open-coding them.

 - Use pnp_set_logical_device() instead of open-coding it.

 - W83627EHG: Fix incorrect enable_hwm_smbus() code comment.

 - Use ARRAY_SIZE.

 - w83627hf/superio.c: w83627hf_16_bit_addr_qual(): Bugfix, the code was using
   'dev->path.pnp.port >> 8' as config port, which is incorrect in superio.c
   (which has a "real" device_t struct, in contrast to *_early_serial.c which
   uses "unsigned" as device_t where 'dev >> 8' is required).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 60 insertions, 59 deletions

diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc
index 1cecd88531..0bff762f47 100644
--- a/src/superio/winbond/w83627ehg/Makefile.inc
+++ b/src/superio/winbond/w83627ehg/Makefile.inc
@@ -19,5 +19,5 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#config chip.h
 ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c
+
diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c
index 45410d1ff4..cc65a65160 100644
--- a/src/superio/winbond/w83627ehg/superio.c
+++ b/src/superio/winbond/w83627ehg/superio.c
@@ -45,74 +45,74 @@ static void pnp_exit_ext_func_mode(device_t dev)
 	outb(0xaa, dev->path.pnp.port);
 }
 
-static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value)
+static void pnp_write_index(u16 port, u8 reg, u8 value)
 {
-	outb(reg, port_base);
-	outb(value, port_base + 1);
+	outb(reg, port);
+	outb(value, port + 1);
 }
 
-static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
+static u8 pnp_read_index(u16 port, u8 reg)
 {
-	outb(reg, port_base);
-	return inb(port_base + 1);
+	outb(reg, port);
+	return inb(port + 1);
 }
 
 static void enable_hwm_smbus(device_t dev)
 {
-	/* Set the pin 91,92 as I2C bus. */
-	uint8_t reg, value;
-	reg = 0x2a;
-	value = pnp_read_config(dev, reg);
-	value |= (1 << 1);
-	pnp_write_config(dev, reg, value);
+	u8 reg8;
+
+	/* Configure pins 91/92 as SDA/SCL (I2C bus). */
+	reg8 = pnp_read_config(dev, 0x2a);
+	reg8 |= (1 << 1);
+	pnp_write_config(dev, 0x2a, reg8);
 }
 
 static void init_acpi(device_t dev)
 {
-	uint8_t value = 0x20;
+	u8 value = 0x20; /* TODO: 0x20 value here never used? */
 	int power_on = 1;
 
 	get_option(&power_on, "power_on_after_fail");
 	pnp_enter_ext_func_mode(dev);
-	pnp_write_index(dev->path.pnp.port, 7, 0x0a);
+	pnp_set_logical_device(dev);
 	value = pnp_read_config(dev, 0xe4);
 	value &= ~(3 << 5);
-	if (power_on) {
+	if (power_on)
 		value |= (1 << 5);
-	}
 	pnp_write_config(dev, 0xe4, value);
 	pnp_exit_ext_func_mode(dev);
 }
 
-static void init_hwm(unsigned long base)
+static void init_hwm(u16 base)
 {
 	int i;
-	uint8_t reg, value;
+	u8 reg, value;
 
 	/* reg mask data */
-	unsigned hwm_reg_values[] = {
+	u8 hwm_reg_values[] = {
 		0x40, 0xff, 0x81, /* Start HWM. */
-		0x48, 0x7f, 0x2a, /* Set SMBus base to 0x54 >> 1. */
+		0x48, 0x7f, 0x2a, /* Set SMBus base to 0x2a (0x54 >> 1). */
 	};
 
-	for(i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
+	for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
 		reg = hwm_reg_values[i];
 		value = pnp_read_index(base, reg);
 		value &= 0xff & (~(hwm_reg_values[i + 1]));
 		value |= 0xff & hwm_reg_values[i + 2];
-		/* printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value); */
+		printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, "
+		       "value = 0x%02x\n", base, reg, value);
 		pnp_write_index(base, reg, value);
 	}
 }
 
 static void w83627ehg_init(device_t dev)
 {
-	struct superio_winbond_w83627ehg_config *conf;
+	struct superio_winbond_w83627ehg_config *conf = dev->chip_info;
 	struct resource *res0, *res1;
-	if (!dev->enabled) {
+
+	if (!dev->enabled)
 		return;
-	}
-	conf = dev->chip_info;
+
 	switch(dev->path.pnp.device) {
 	case W83627EHG_SP1:
 		res0 = find_resource(dev, PNP_IDX_IO0);
@@ -152,7 +152,7 @@ static void w83627ehg_pnp_enable_resources(device_t dev)
 
 	switch (dev->path.pnp.device) {
 	case W83627EHG_HWM:
-		printk(BIOS_DEBUG, "w83627ehg hwm smbus enabled\n");
+		printk(BIOS_DEBUG, "W83627EHG HWM SMBus enabled\n");
 		enable_hwm_smbus(dev);
 		break;
 	}
@@ -162,12 +162,13 @@ static void w83627ehg_pnp_enable_resources(device_t dev)
 
 static void w83627ehg_pnp_enable(device_t dev)
 {
-	if (!dev->enabled) {
-		pnp_enter_ext_func_mode(dev);
-		pnp_set_logical_device(dev);
-		pnp_set_enable(dev, 0);
-		pnp_exit_ext_func_mode(dev);
-	}
+	if (dev->enabled)
+		return;
+
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_exit_ext_func_mode(dev);
 }
 
 static struct device_operations ops = {
@@ -183,7 +184,6 @@ static struct pnp_info pnp_dev_info[] = {
 	{ &ops, W83627EHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
 	{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 	{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
-	/* No 4 { 0,}, */
 	{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
 	{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
 	{ &ops, W83627EHG_WDTO_PLED, },
@@ -201,8 +201,7 @@ static struct pnp_info pnp_dev_info[] = {
 
 static void enable_dev(struct device *dev)
 {
-	pnp_enable_devices(dev, &ops,
-		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
 
 struct chip_operations superio_winbond_w83627ehg_ops = {
diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h
index f03cf0672d..60c2b064b2 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg.h
+++ b/src/superio/winbond/w83627ehg/w83627ehg.h
@@ -23,35 +23,36 @@
 #define SUPERIO_WINBOND_W83627EHG_W83627EHG_H
 
 #define W83627EHG_FDC              0   /* Floppy */
-#define W83627EHG_PP               1   /* Parallel Port */
+#define W83627EHG_PP               1   /* Parallel port */
 #define W83627EHG_SP1              2   /* Com1 */
 #define W83627EHG_SP2              3   /* Com2 */
-#define W83627EHG_KBC              5   /* Keyboard & Mouse */
-#define W83627EHG_GPIO_GAME_MIDI   7   /* GPIO1, GPIO6, Game Port and MIDI Port */
+#define W83627EHG_KBC              5   /* PS/2 keyboard & mouse */
+#define W83627EHG_GPIO_GAME_MIDI   7   /* GPIO1, GPIO6, Game port, MIDI port */
 #define W83627EHG_WDTO_PLED        8   /* TODO */
-#define W83627EHG_GPIO_SUSLED      9   /* GPIO2, GPIO3, GPIO4, GPIO5 and SUSLED */
+#define W83627EHG_GPIO_SUSLED      9   /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
 #define W83627EHG_ACPI            10   /* ACPI */
-#define W83627EHG_HWM             11   /* Hardware Monitor */
+#define W83627EHG_HWM             11   /* Hardware monitor */
 
-/* virtual devices sharing the enables are encoded as follows:
+/*
+ * Virtual devices sharing the enables are encoded as follows:
  *   VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
  */
 
-#define W83627EHG_SFI		((1 << 8) | 6) /* Flash has bit1 as enable */
-#define W83627EHG_GPIO1		W83627EHG_GPIO_GAME_MIDI /* GPIO1 is at LDN 7, bit 0 */
-#define W83627EHG_GAME		((1 << 8) | 7)
-#define W83627EHG_MIDI		((2 << 8) | 7)
-#define W83627EHG_GPIO6		((3 << 8) | 7)
+#define W83627EHG_SFI	((1 << 8) | 6)           /* Flash has bit1 as enable */
+#define W83627EHG_GPIO1	W83627EHG_GPIO_GAME_MIDI /* GPIO1: LDN 7, bit 0 */
+#define W83627EHG_GAME	((1 << 8) | 7)
+#define W83627EHG_MIDI	((2 << 8) | 7)
+#define W83627EHG_GPIO6	((3 << 8) | 7)
 
-#define W83627EHG_GPIO2		W83627EHG_GPIO_SUSLED /* GPIO2 is at LDN 9, bit 0 */
-#define W83627EHG_GPIO3		((1 << 8) | 9)
-#define W83627EHG_GPIO4		((2 << 8) | 9)
-#define W83627EHG_GPIO5		((3 << 8) | 9)
+#define W83627EHG_GPIO2	W83627EHG_GPIO_SUSLED    /* GPIO2: LDN 9, bit 0 */
+#define W83627EHG_GPIO3	((1 << 8) | 9)
+#define W83627EHG_GPIO4	((2 << 8) | 9)
+#define W83627EHG_GPIO5	((3 << 8) | 9)
 
 #if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void w83627ehg_enable_dev(device_t dev, unsigned iobase);
+void w83627ehg_enable_dev(device_t dev, u16 iobase);
 void w83627ehg_disable_dev(device_t dev);
-void w83627ehg_enable_serial(device_t dev, unsigned iobase);
+void w83627ehg_enable_serial(device_t dev, u16 iobase);
 #endif
 
 #endif
diff --git a/src/superio/winbond/w83627ehg/w83627ehg_early_init.c b/src/superio/winbond/w83627ehg/w83627ehg_early_init.c
index 0335a67be5..5e66fafadb 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg_early_init.c
+++ b/src/superio/winbond/w83627ehg/w83627ehg_early_init.c
@@ -19,6 +19,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
 #include <arch/romcc_io.h>
 #include "w83627ehg.h"
 
@@ -28,7 +29,7 @@ void w83627ehg_disable_dev(device_t dev)
 	pnp_set_enable(dev, 0);
 }
 
-void w83627ehg_enable_dev(device_t dev, unsigned iobase)
+void w83627ehg_enable_dev(device_t dev, u16 iobase)
 {
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
diff --git a/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c b/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c
index 63b044a9e5..deb8bf6566 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c
+++ b/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c
@@ -22,20 +22,20 @@
 #include <arch/romcc_io.h>
 #include "w83627ehg.h"
 
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(device_t dev)
 {
-	unsigned port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0x87, port);
 	outb(0x87, port);
 }
 
 static void pnp_exit_ext_func_mode(device_t dev)
 {
-	unsigned port = dev >> 8;
+	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
 
-void w83627ehg_enable_serial(device_t dev, unsigned iobase)
+void w83627ehg_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);