W83627DHG/W83627EHG fixups for virtual LDNs.

W83627DHG:

 - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
   that don't have their "enable" bit in bit 0 of the 0x30 register).

 - Fix various I/O masks in the pnp_dev_info[] array as per
   datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.

W83627EHG:

 - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
   mostly implemented already, though).

 - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.

Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.

include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.

asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.

ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 27 insertions, 21 deletions

diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c
index 8bc8461ad2..1f1b681eaf 100644
--- a/src/superio/winbond/w83627ehg/superio.c
+++ b/src/superio/winbond/w83627ehg/superio.c
@@ -178,17 +178,18 @@ static struct device_operations ops = {
 };
 
 static struct pnp_info pnp_dev_info[] = {
-	{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_PP,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
-	{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
-	{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_FDC,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_SP1,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_SP2,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, W83627EHG_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
+	{ &ops, W83627EHG_SFI,  PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
 	{ &ops, W83627EHG_WDTO_PLED, },
-	{ &ops, W83627EHG_ACPI, },
-	{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, W83627EHG_ACPI, PNP_IRQ0, },
+	{ &ops, W83627EHG_HWM,  PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
+
 	{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
-	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
+	{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07fe, 4}, },
 	{ &ops, W83627EHG_GPIO1, },
 	{ &ops, W83627EHG_GPIO2, },
 	{ &ops, W83627EHG_GPIO3, },
diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h
index 60c2b064b2..6d6d05db8b 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg.h
+++ b/src/superio/winbond/w83627ehg/w83627ehg.h
@@ -27,27 +27,32 @@
 #define W83627EHG_SP1              2   /* Com1 */
 #define W83627EHG_SP2              3   /* Com2 */
 #define W83627EHG_KBC              5   /* PS/2 keyboard & mouse */
-#define W83627EHG_GPIO_GAME_MIDI   7   /* GPIO1, GPIO6, Game port, MIDI port */
-#define W83627EHG_WDTO_PLED        8   /* TODO */
-#define W83627EHG_GPIO_SUSLED      9   /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
+#define W83627EHG_WDTO_PLED        8   /* Watchdog timer timeout, power LED */
 #define W83627EHG_ACPI            10   /* ACPI */
 #define W83627EHG_HWM             11   /* Hardware monitor */
 
+/* The following are handled using "virtual LDNs" (hence the _V suffix). */
+#define W83627EHG_SFI_V            6   /* Serial flash interface (SFI) */
+#define W83627EHG_GPIO_GAME_MIDI_V 7   /* GPIO1, GPIO6, game port, MIDI */
+#define W83627EHG_GPIO_SUSLED_V    9   /* GPIO2, GPIO3, GPIO4, GPIO5, SUSLED */
+
 /*
  * Virtual devices sharing the enables are encoded as follows:
  *   VLDN = baseLDN[7:0] | [10:8] bitpos of enable in 0x30 of baseLDN
  */
 
-#define W83627EHG_SFI	((1 << 8) | 6)           /* Flash has bit1 as enable */
-#define W83627EHG_GPIO1	W83627EHG_GPIO_GAME_MIDI /* GPIO1: LDN 7, bit 0 */
-#define W83627EHG_GAME	((1 << 8) | 7)
-#define W83627EHG_MIDI	((2 << 8) | 7)
-#define W83627EHG_GPIO6	((3 << 8) | 7)
+/* SFI has bit 1 as enable (instead of bit 0 as usual). */
+#define W83627EHG_SFI	((1 << 8) | W83627EHG_SFI_V)
+
+#define W83627EHG_GPIO1	((0 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+#define W83627EHG_GAME	((1 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+#define W83627EHG_MIDI	((2 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
+#define W83627EHG_GPIO6	((3 << 8) | W83627EHG_GPIO_GAME_MIDI_V)
 
-#define W83627EHG_GPIO2	W83627EHG_GPIO_SUSLED    /* GPIO2: LDN 9, bit 0 */
-#define W83627EHG_GPIO3	((1 << 8) | 9)
-#define W83627EHG_GPIO4	((2 << 8) | 9)
-#define W83627EHG_GPIO5	((3 << 8) | 9)
+#define W83627EHG_GPIO2	((0 << 8) | W83627EHG_GPIO_SUSLED_V)
+#define W83627EHG_GPIO3	((1 << 8) | W83627EHG_GPIO_SUSLED_V)
+#define W83627EHG_GPIO4	((2 << 8) | W83627EHG_GPIO_SUSLED_V)
+#define W83627EHG_GPIO5	((3 << 8) | W83627EHG_GPIO_SUSLED_V)
 
 #if defined(__PRE_RAM__) && !defined(__ROMCC__)
 void w83627ehg_enable_dev(device_t dev, u16 iobase);