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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-08-02 20:08:35 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-08-23 05:30:42 +0200
commit47b8075bb14de4dad4cfd2c2f42482e04644b28d (patch)
treeeabeb1e0762ee83cdeec20c4b1a01baee6563141 /src/superio
parent8b685398a74065d832fe2a3dfcfb313f0f4f11c3 (diff)
downloadcoreboot-47b8075bb14de4dad4cfd2c2f42482e04644b28d.tar.xz
superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE as argument instead of hard coding and playing funny business with the pre-processor. Fix board to match. Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6463 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/superio')
-rw-r--r--src/superio/smsc/sio1036/Makefile.inc1
-rw-r--r--src/superio/smsc/sio1036/sio1036.h5
-rw-r--r--src/superio/smsc/sio1036/sio1036_early_init.c31
3 files changed, 21 insertions, 16 deletions
diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc
index f09d451d48..c4b61381b9 100644
--- a/src/superio/smsc/sio1036/Makefile.inc
+++ b/src/superio/smsc/sio1036/Makefile.inc
@@ -17,4 +17,5 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
+romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c
ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c
diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h
index e61b600f5a..fa52a1a5c8 100644
--- a/src/superio/smsc/sio1036/sio1036.h
+++ b/src/superio/smsc/sio1036/sio1036.h
@@ -26,4 +26,9 @@
#define LPT_POWER_DOWN (1 << 2)
#define IR_OUPUT_MUX (1 << 6)
+#include <arch/io.h>
+#include <stdint.h>
+
+void sio1036_enable_serial(device_t dev, u16 iobase);
+
#endif /* SUPERIO_SMSC_1306_H */
diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c
index 52232a5410..5f10230c84 100644
--- a/src/superio/smsc/sio1036/sio1036_early_init.c
+++ b/src/superio/smsc/sio1036/sio1036_early_init.c
@@ -20,50 +20,49 @@
/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
#include <arch/io.h>
+#include <stdint.h>
+
#include "sio1036.h"
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE 0x3F8
-#endif
static inline void sio1036_enter_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ unsigned port = dev >> 8;
outb(0x55, port);
}
static inline void sio1036_exit_conf_state(device_t dev)
{
- unsigned port = dev>>8;
+ unsigned port = dev >> 8;
outb(0xaa, port);
}
+/* Detect SMSC SIO1036 LPC Debug Card status */
static u8 detect_sio1036_chip(unsigned port)
{
- device_t dev;
- dev = PNP_DEV (port, SIO1036_SP1);
+ device_t dev = PNP_DEV(port, SIO1036_SP1);
unsigned data;
+
sio1036_enter_conf_state (dev);
data = pnp_read_config (dev, 0x0D);
sio1036_exit_conf_state(dev);
- /* detect smsc sio1036 chip */
+
+ /* Detect SMSC SIO1036 chip */
if (data == 0x82) {
/* Found SMSC SIO1036 chip */
return 0;
}
else {
- return -1;
+ return 1;
};
}
-static inline void sio1036_early_init(unsigned port)
+void sio1036_enable_serial(device_t dev, u16 iobase)
{
- device_t dev;
- dev = PNP_DEV (port, SIO1036_SP1);
+ unsigned port = dev >> 8;
- if (detect_sio1036_chip(port) != 0) {
- /* Not found SMSC SIO1036 */
+ if (detect_sio1036_chip(port) != 0)
return;
- }
+
sio1036_enter_conf_state (dev);
/* Enable SMSC UART 0 */
@@ -91,7 +90,7 @@ static inline void sio1036_early_init(unsigned port)
/* Enable SMSC UART 0 */
/*Set base io address */
- pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2));
+ pnp_write_config (dev, 0x25, (u8)(iobase >> 2));
/* Set UART IRQ onto 0x04 */
pnp_write_config (dev, 0x28, 0x04);