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authorPaul Menzel <pmenzel@molgen.mpg.de>2020-10-12 01:29:12 +0200
committerNico Huber <nico.h@gmx.de>2020-10-17 13:34:33 +0000
commit138c1b864bf9745f084e2b7035204aaa3b5b983c (patch)
tree775256f6708a903b0454822606207fc9eca36e35 /src/superio
parentffbb4b2b11f2bb875fbaca0137615b592ba0cd9c (diff)
downloadcoreboot-138c1b864bf9745f084e2b7035204aaa3b5b983c.tar.xz
superio/nuvoton: Only set bit 7 of global CR 0x2a for COM A
Currently, when selecting SUPERIO_NUVOTON_NCT*_COM_A, the whole global control register 0x2a is written to 0x40. CR 0x2a defaults to 0xc0, so indeed bit 7 is cleared, but the device early init code might have set other bits in that control register, so setting it to 0x40 might override already set bits. So, only clear bit 7 and leave the other bits untouched. Fixes: f95daa510d ("superio/nuvoton: Add back Nuvoton NCT6776 support") Change-Id: I9ded9dab3985c4c8e5c45af354ef44af482e18c2 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/superio')
-rw-r--r--src/superio/nuvoton/common/early_serial.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c
index cc21f40d2a..ed5fdbab1f 100644
--- a/src/superio/nuvoton/common/early_serial.c
+++ b/src/superio/nuvoton/common/early_serial.c
@@ -55,7 +55,7 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A) ||
CONFIG(SUPERIO_NUVOTON_NCT6776_COM_A))
/* Route COM A to GPIO8 pin group */
- pnp_write_config(dev, 0x2a, 0x40);
+ pnp_unset_and_set_config(dev, 0x2a, 1 << 7, 0);
if (CONFIG(SUPERIO_NUVOTON_NCT6791D_COM_A))
/* Route COM A to GPIO8 pin group */