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authorStefan Reinauer <reinauer@chromium.org>2012-03-30 15:10:07 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-06 21:23:08 +0200
commit6626d6a9e3d8c6eb6b8348f6a0736d7971b736db (patch)
tree8462a4b2ac45784edf89d8469cfd9913b96e3064 /src/superio
parent8198600b0b71b474ac8ec75248d5dd916a2713ae (diff)
downloadcoreboot-6626d6a9e3d8c6eb6b8348f6a0736d7971b736db.tar.xz
Add initial support for SMSC SIO1007 SuperI/O chip
early_serial and some ACPI needed for compilation Change-Id: I5dd970676488697156e0630392884f31149ac85b Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: http://review.coreboot.org/824 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/superio')
-rw-r--r--src/superio/smsc/Kconfig2
-rw-r--r--src/superio/smsc/Makefile.inc1
-rw-r--r--src/superio/smsc/sio1007/acpi/superio.asl299
-rw-r--r--src/superio/smsc/sio1007/early_serial.c64
4 files changed, 366 insertions, 0 deletions
diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index d4f07ec19c..224376bfa8 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -36,6 +36,8 @@ config SUPERIO_SMSC_LPC47N227
bool
config SUPERIO_SMSC_SIO10N268
bool
+config SUPERIO_SMSC_SIO1007
+ bool
config SUPERIO_SMSC_KBC1100
bool
config SUPERIO_SMSC_SMSCSUPERIO
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index d07afea2ad..bb4bf1d725 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -27,6 +27,7 @@ subdirs-y += lpc47m15x
subdirs-y += lpc47n217
subdirs-y += lpc47n227
subdirs-y += sio10n268
+subdirs-y += sio1007
subdirs-y += kbc1100
subdirs-y += smscsuperio
subdirs-y += sio1036
diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl
new file mode 100644
index 0000000000..5bb45fad9a
--- /dev/null
+++ b/src/superio/smsc/sio1007/acpi/superio.asl
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+ Name (_ADR, 0x2E)
+ OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
+ Field (SIOA, ByteAcc, NoLock, Preserve)
+ {
+ SI2E, 8,
+ SI2F, 8,
+ }
+
+ IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x02),
+ SCNT, 8, /* Configure Control */
+ Offset (0x07),
+ SLDN, 8, /* Logical Device Number */
+ Offset (0x30),
+ SACT, 8, /* Activate */
+ Offset (0x60),
+ IO0H, 8, /* Base Address 0 MSB */
+ IO0L, 8, /* Base Address 0 LSB */
+ Offset (0x62),
+ IO1H, 8, /* Base Address 1 MSB */
+ IO1L, 8, /* Base Address 1 LSB */
+ Offset (0x70),
+ IQ00, 8, /* Interrupt Select */
+ }
+
+ Name (SFDC, 0) /* Floppy Disk Controller */
+ Name (SSP1, 1) /* Serial Port 1 */
+ Name (SENV, 4) /* Environment Controller */
+ Name (SKBC, 5) /* Keyboard */
+ Name (SKBM, 6) /* Mouse */
+ Name (SGPI, 7) /* GPIO */
+ Name (SINF, 10) /* Consumer IR */
+
+ Method (ENTR, 0, NotSerialized)
+ {
+ Store (0x87, SI2E)
+ Store (0x01, SI2E)
+ Store (0x55, SI2E)
+ Store (0x55, SI2E)
+ }
+
+ Method (EXIT, 0, NotSerialized)
+ {
+ Store (0x02, SCNT)
+ }
+
+ /* Parse activate register for an LDN */
+ Method (ISEN, 1, NotSerialized)
+ {
+ ENTR ()
+ Store (Arg0, SLDN)
+ Store (SACT, Local0)
+ EXIT ()
+
+ /* Check if it exists */
+ If (LEqual (Local0, 0xFF))
+ {
+ Return (0x00)
+ }
+
+ /* Check if activated */
+ If (LEqual (Local0, One))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0D)
+ }
+ }
+
+ /* Enable an LDN via the activate register */
+ Method (SENA, 1, NotSerialized)
+ {
+ ENTR ()
+ Store (Arg0, SLDN)
+ Store (One, SACT)
+ EXIT ()
+ }
+
+ /* Disable an LDN via the activate register */
+ Method (SDIS, 1, NotSerialized)
+ {
+ ENTR ()
+ Store (Arg0, SLDN)
+ Store (Zero, SACT)
+ EXIT ()
+ }
+
+#ifdef SIO_ENABLE_ENVC
+ Device (ENVC) {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 10)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SENV))
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
+ IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
+ IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
+ })
+
+ OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07)
+ Field (ECAP, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x05),
+ ECAI, 8, // Address Index Register
+ ECAD, 8, // Address Data Register
+ }
+
+ // Registers for thermal zone implementations
+ IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x29),
+ TIN1, 8, // TMPIN1 Reading
+ TIN2, 8, // TMPIN2 Reading
+ TIN3, 8, // TMPIN3 Reading
+ Offset (0x6b),
+ F2PS, 8, // FAN2 PWM Setting
+ Offset (0x73),
+ F3PS, 8, // FAN3 PWM Setting
+ }
+ }
+#endif
+
+#ifdef SIO_ENABLE_GPIO
+ Device (GPIO) {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 11)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
+ IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
+ IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_COM1
+ Device (COM1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SSP1))
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+ IRQNoFlags () {4}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SKBC))
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+ IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+ IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+ Device (PS2M) // Mouse
+ {
+ Name (_HID, EISAID("PNP0F13"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SKBM))
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IRQNoFlags () {12}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ IRQNoFlags () {12}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_FDC0
+ Device (FDC0) // Floppy controller
+ {
+ Name (_HID, EISAID ("PNP0700"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SFDC))
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+ IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+ IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_INFR
+ Device (INFR) // Infrared controller
+ {
+ Name (_HID, EISAID ("PNP0510"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (ISEN (SINF))
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
+ IRQNoFlags () { SIO_INFR_IRQ }
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
+ IRQNoFlags () { SIO_INFR_IRQ }
+ })
+ }
+#endif
+}
diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c
new file mode 100644
index 0000000000..859e351765
--- /dev/null
+++ b/src/superio/smsc/sio1007/early_serial.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The chip could be bootstrap mapped to one of four LPC addresses:
+ * 0x2e, 0x4e, 0x162e, and 0x164e.
+ */
+const u16 sio1007_lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
+
+static void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
+{
+ u8 reg_value;
+
+ outb(reg, lpc_port);
+ reg_value = inb(lpc_port + 1);
+ reg_value &= ~mask;
+ reg_value |= (value & mask);
+ outb(reg_value, lpc_port + 1);
+}
+
+static int sio1007_enable_uart_at(u16 port)
+{
+ /* Enable config mode. */
+ outb(0x55, port);
+ if (inb(port) != 0x55)
+ return 0; /* There is no LPC device at this address. */
+
+ /* Registers 12 and 13 hold config address, look for a match. */
+ outb(0x12, port);
+ if (inb(port + 1) != (port & 0xff))
+ return 0;
+
+ outb(0x13, port);
+ if (inb(port + 1) != (port >> 8))
+ return 0;
+
+ /* This must be the sio1007, enable the UART. */
+ /* turn on power */
+ sio1007_setreg(port, 0x2, 1 << 3, 1 << 3);
+ /* enable high speed */
+ sio1007_setreg(port, 0xc, 1 << 6, 1 << 6);
+ /* set the base address */
+ sio1007_setreg(port, 0x24, CONFIG_TTYS0_BASE >> 2, 0xff);
+
+ /* Disable config mode. */
+ outb(0xaa, port);
+ return 1;
+}