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authorNick Vaccaro <nvaccaro@chromium.org>2017-12-22 22:50:57 -0800
committerMartin Roth <martinroth@google.com>2018-01-07 18:45:46 +0000
commit780a1c44e190427522ee27e887b2a9ab692eb594 (patch)
tree6052cb7faf581fe4186aa558c254f0a7f6191736 /src/superio
parenta98727849ad06dd5464c88d485f57f09e090f5c4 (diff)
downloadcoreboot-780a1c44e190427522ee27e887b2a9ab692eb594.tar.xz
soc/intel/cannonlake: provide LPDDR4 memory init
Instead of having the mainboards duplicate logic surrounding LPDDR4 initialization provide helpers to do the heavy lifting. It also handles the quirks of the FSP configuration which allows the mainboard porting to focus on the schematic/design. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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