superio: Add ASpeed AST2400

Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.

BUG = N/A
TEST = ASRock D1521D4U

Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

10 files changed, 304 insertions, 0 deletions

diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc
index 5fc0ecdd7e..ca96343858 100644
--- a/src/superio/Makefile.inc
+++ b/src/superio/Makefile.inc
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2018 Eltan B.V.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -13,6 +14,7 @@
 ## GNU General Public License for more details.
 ##
 
+subdirs-y += aspeed
 subdirs-y += fintek
 subdirs-y += intel
 subdirs-y += ite
diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc
new file mode 100644
index 0000000000..6d0cc263e9
--- /dev/null
+++ b/src/superio/aspeed/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2018 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+## include generic fintek pre-ram stage driver
+romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c
+bootblock-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c
+
+subdirs-y += ast2400
+subdirs-y += common
+
+CPPFLAGS_common += -Isrc/superio/aspeed
diff --git a/src/superio/aspeed/ast2400/Kconfig b/src/superio/aspeed/ast2400/Kconfig
new file mode 100644
index 0000000000..1ced5afdc2
--- /dev/null
+++ b/src/superio/aspeed/ast2400/Kconfig
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+## Copyright (C) 2018 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ASPEED_AST2400
+	bool
+	default n
+	select SUPERIO_ASPEED_COMMON_PRE_RAM
diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc
new file mode 100644
index 0000000000..a6f8b2003a
--- /dev/null
+++ b/src/superio/aspeed/ast2400/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+## Copyright (C) 2018 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c
diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h
new file mode 100644
index 0000000000..aa9b0a9899
--- /dev/null
+++ b/src/superio/aspeed/ast2400/ast2400.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ASPEED_AST2400_H
+#define SUPERIO_ASPEED_AST2400_H
+
+#define AST2400_SUART1	0x2 /* Com1 */
+#define AST2400_SUART2	0x3 /* Com2 */
+#define AST2400_SWAK	0x4 /* System Wake-Up control */
+#define AST2400_KBC	0x5 /* Keyboard controller */
+#define AST2400_GPIO	0x7 /* GPIO */
+#define AST2400_SUART3	0xB /* Com3 */
+#define AST2400_SUART4	0xC /* Com4 */
+#define AST2400_ILPC2AHB	0xD /* LPC 2 AHB */
+#define AST2400_MAILBOX	0xE /* Mailbox */
+
+#endif /* SUPERIO_ASPEED_AST2400_H */
diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c
new file mode 100644
index 0000000000..dcb14fa668
--- /dev/null
+++ b/src/superio/aspeed/ast2400/superio.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <console/console.h>
+#include <string.h>
+#include <pc80/keyboard.h>
+#include "ast2400.h"
+
+static void ast2400_init(struct device *dev)
+{
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case AST2400_KBC:
+		pc_keyboard_init(NO_AUX_DEVICE);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources = pnp_read_resources,
+	.set_resources = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable = pnp_enable,
+	.init = ast2400_init,
+	.ops_pnp_mode = &pnp_conf_mode_a5a5_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ NULL, AST2400_SUART1,   PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
+	{ NULL, AST2400_SUART2,   PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
+	{ NULL, AST2400_SWAK,     PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3
+		| PNP_IRQ0, 0xfff8, 0xfff8, 0xfff8, 0xfff8, },
+	{ NULL, AST2400_KBC,      PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1
+		| PNP_MSC0, 0xffff, 0xffff, },
+	{ NULL, AST2400_GPIO,     PNP_IRQ0, }, // GPIO LDN has no IO Region
+	{ NULL, AST2400_SUART3,   PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
+	{ NULL, AST2400_SUART4,   PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0xfff8, },
+	{ NULL, AST2400_ILPC2AHB, PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2
+		| PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7
+		| PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCC
+		| PNP_MSCD | PNP_MSCE, },
+	{ NULL, AST2400_MAILBOX,  PNP_IO0 | PNP_IRQ0, 0xfffe, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info),
+		pnp_dev_info);
+}
+
+struct chip_operations superio_aspeed_ast2400_ops = {
+	CHIP_NAME("ASpeed AST2400 Super I/O")
+	.enable_dev = enable_dev,
+};
diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig
new file mode 100644
index 0000000000..3f0dabb853
--- /dev/null
+++ b/src/superio/aspeed/common/Kconfig
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+## Copyright (C) 2018 Eltan B.V.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+# Generic Aspeed preram driver - Just enough UART initialisation code for
+# preram phase.
+config SUPERIO_ASPEED_COMMON_PRE_RAM
+	bool
+	default n
diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h
new file mode 100644
index 0000000000..d3774eab3e
--- /dev/null
+++ b/src/superio/aspeed/common/aspeed.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H
+#define SUPERIO_ASPEED_COMMON_ROMSTAGE_H
+
+#include <arch/io.h>
+#include <device/pnp_type.h>
+#include <stdint.h>
+
+void aspeed_enable_serial(pnp_devfn_t dev, uint16_t iobase);
+
+void pnp_enter_conf_state(pnp_devfn_t dev);
+void pnp_exit_conf_state(pnp_devfn_t dev);
+
+#endif /* SUPERIO_ASPEED_COMMON_ROMSTAGE_H */
diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c
new file mode 100644
index 0000000000..7ac9474bcc
--- /dev/null
+++ b/src/superio/aspeed/common/early_serial.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * A generic pre-ram driver for Aspeed variant Super I/O chips.
+ *
+ * The following is derived directly from the vendor Aspeed's data-sheets:
+ *
+ * To toggle between `configuration mode` and `normal operation mode` as to
+ * manipulation the various LDN's in Aspeed Super I/O's we are required to
+ * pass magic numbers `passwords keys`.
+ *
+ *  ASPEED_ENTRY_KEY :=  enable  configuration : 0xA5 (twice!)
+ *  ASPEED_EXIT_KEY  :=  disable configuration : 0xAA
+ *
+ * To modify a LDN's configuration register, we use the index port to select
+ * the index of the LDN and then writing to the data port to alter the
+ * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a
+ * user modified pair is 0x2E, 0x2F respectively.
+ *
+ */
+
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <device/pnp_ops.h>
+#include <stdint.h>
+#include "aspeed.h"
+
+#define ASPEED_ENTRY_KEY 0xA5
+#define ASPEED_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0xA5' into index port dev. */
+void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(ASPEED_ENTRY_KEY, port);
+	outb(ASPEED_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(ASPEED_EXIT_KEY, port);
+}
+
+/* Bring up early serial debugging output before the RAM is initialized. */
+void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c
index dec630bfa4..8ba1cddba9 100644
--- a/src/superio/common/conf_mode.c
+++ b/src/superio/common/conf_mode.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Nico Huber <nico.h@gmx.de>
+ * Copyright (C) 2017-2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -48,6 +49,12 @@ void pnp_enter_conf_mode_a0a0(struct device *dev)
 	outb(0xa0, dev->path.pnp.port);
 }
 
+void pnp_enter_conf_mode_a5a5(struct device *dev)
+{
+	outb(0xa5, dev->path.pnp.port);
+	outb(0xa5, dev->path.pnp.port);
+}
+
 void pnp_exit_conf_mode_aa(struct device *dev)
 {
 	outb(0xaa, dev->path.pnp.port);
@@ -96,6 +103,11 @@ const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = {
 	.exit_conf_mode  = pnp_exit_conf_mode_aa,
 };
 
+const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = {
+	.enter_conf_mode = pnp_enter_conf_mode_a5a5,
+	.exit_conf_mode  = pnp_exit_conf_mode_aa,
+};
+
 const struct pnp_mode_ops pnp_conf_mode_870155_aa = {
 	.enter_conf_mode = pnp_enter_conf_mode_870155aa,
 	.exit_conf_mode  = pnp_exit_conf_mode_0202,