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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-07 12:12:58 +0200
committerMartin Roth <martinroth@google.com>2018-08-09 15:49:08 +0000
commit6de6571f1c362c43dbfd04c79d1ddedcb953c724 (patch)
tree7aabb5a1a34216b79f2a557edd0cf74c5472c8b5 /src/superio
parent089b6857615a3bbf9c28b8e658da6b768650692f (diff)
downloadcoreboot-6de6571f1c362c43dbfd04c79d1ddedcb953c724.tar.xz
src/superio: Fix typo and remove unneeded whitespace
Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/superio')
-rw-r--r--src/superio/ite/it8772f/it8772f.h2
-rw-r--r--src/superio/smsc/sio1036/sio1036.h2
-rw-r--r--src/superio/smsc/sio1036/sio1036_early_init.c26
3 files changed, 15 insertions, 15 deletions
diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h
index ec210a8bec..91d107a9a2 100644
--- a/src/superio/ite/it8772f/it8772f.h
+++ b/src/superio/ite/it8772f/it8772f.h
@@ -120,7 +120,7 @@ enum thermal_mode {
/* GPIO Inernal Pull-up: 1: Enable, 0: Disable */
#define GPIO_REG_PULLUP(x) (0xb8 + (x))
-/* GPIO Fucntion Select: 1: Simple I/O, 0: Alternate function */
+/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */
#define GPIO_REG_ENABLE(x) (0xc0 + (x))
/* GPIO Mode: 0: input mode, 1: output mode */
diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h
index 37ef041aec..683dcd113e 100644
--- a/src/superio/smsc/sio1036/sio1036.h
+++ b/src/superio/smsc/sio1036/sio1036.h
@@ -20,7 +20,7 @@
#define UART_POWER_DOWN (1 << 7)
#define LPT_POWER_DOWN (1 << 2)
-#define IR_OUPUT_MUX (1 << 6)
+#define IR_OUTPUT_MUX (1 << 6)
#include <arch/io.h>
#include <stdint.h>
diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c
index b01151061c..1f2c9f2e5c 100644
--- a/src/superio/smsc/sio1036/sio1036_early_init.c
+++ b/src/superio/smsc/sio1036/sio1036_early_init.c
@@ -38,8 +38,8 @@ static u8 detect_sio1036_chip(unsigned port)
pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1);
unsigned data;
- sio1036_enter_conf_state (dev);
- data = pnp_read_config (dev, 0x0D);
+ sio1036_enter_conf_state(dev);
+ data = pnp_read_config(dev, 0x0D);
sio1036_exit_conf_state(dev);
/* Detect SMSC SIO1036 chip */
@@ -59,37 +59,37 @@ void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase)
if (detect_sio1036_chip(port) != 0)
return;
- sio1036_enter_conf_state (dev);
+ sio1036_enter_conf_state(dev);
/* Enable SMSC UART 0 */
/* Valid configuration cycle */
- pnp_write_config (dev, 0x00, 0x28);
+ pnp_write_config(dev, 0x00, 0x28);
/* PP power/mode/cr lock */
- pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN);
- pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN);
+ pnp_write_config(dev, 0x01, 0x98 | LPT_POWER_DOWN);
+ pnp_write_config(dev, 0x02, 0x08 | UART_POWER_DOWN);
/*Auto power management*/
- pnp_write_config (dev, 0x07, 0x00 );
+ pnp_write_config(dev, 0x07, 0x00);
/*ECP FIFO threhod */
- pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX);
+ pnp_write_config(dev, 0x0A, 0x00 | IR_OUTPUT_MUX);
/*GPIO direction register 2 */
- pnp_write_config (dev, 0x033, 0x00);
+ pnp_write_config(dev, 0x033, 0x00);
/*UART Mode */
- pnp_write_config (dev, 0x0C, 0x02);
+ pnp_write_config(dev, 0x0C, 0x02);
/* GPIO polarity regisgter 2 */
- pnp_write_config (dev, 0x034, 0x00);
+ pnp_write_config(dev, 0x034, 0x00);
/* Enable SMSC UART 0 */
/*Set base io address */
- pnp_write_config (dev, 0x25, (u8)(iobase >> 2));
+ pnp_write_config(dev, 0x25, (u8)(iobase >> 2));
/* Set UART IRQ onto 0x04 */
- pnp_write_config (dev, 0x28, 0x04);
+ pnp_write_config(dev, 0x28, 0x04);
sio1036_exit_conf_state(dev);
}