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| author | Christian Walter <christian.walter@9elements.com> | 2020-01-25 13:42:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-26 18:23:33 +0000 |
| commit | da60958ae37f15b6bc6f976bdf32b26fab573ae0 (patch) | |
| tree | e5871685ba3e282adc2b3c96e4d042d1f5c8e391 /src/superio | |
| parent | e9b3fd1d5da628c7207701ead053a318235c86b3 (diff) | |
| download | coreboot-da60958ae37f15b6bc6f976bdf32b26fab573ae0.tar.xz | |
superio/aspeed/ast2400: Fix Register Offset
According to the specification the register offset must be 0x71 instead
of 0x70.
Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/superio')
| -rw-r--r-- | src/superio/aspeed/ast2400/superio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 37a7c9d30c..6f2cbcdb70 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -35,7 +35,7 @@ static void ast2400_init(struct device *dev) pnp_enter_conf_mode(dev); pnp_set_logical_device(dev); /* In ESPI mode must write 0 to IRQ level on every LDN */ - pnp_write_config(dev, 0x70, 0); + pnp_write_config(dev, 0x71, 0); pnp_exit_conf_mode(dev); } |