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| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-01-14 06:08:21 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-17 19:26:15 +0100 |
| commit | 17335fab175ed1a16f61729b03c1fbeeec366f37 (patch) | |
| tree | 8922c6825d455ea2178600ee3f0403c3e297711c /src/vboot | |
| parent | 4979d7610e74b83f7b41b10ac30b4fb619b4e26d (diff) | |
| download | coreboot-17335fab175ed1a16f61729b03c1fbeeec366f37.tar.xz | |
soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
Add APIs and required parameters for creating Maxim 98927
and Realtek 5336 SSP endpoints in NHLT table.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=check that NHLT table created is created properly
Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: M Naveen <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/18213
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/vboot')
0 files changed, 0 insertions, 0 deletions