diff options
author | efdesign98 <efdesign98@gmail.com> | 2011-06-20 18:12:43 -0700 |
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committer | Marc Jones <marcj303@gmail.com> | 2011-06-22 01:35:45 +0200 |
commit | 621ca384a7a5efb2cc7597504dc17b741cd2df10 (patch) | |
tree | 01871adc6d39f48916b5625b3aa1a4b6d5ab9c92 /src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c | |
parent | 05a89ab922473f375820a3bd68691bb085c62448 (diff) | |
download | coreboot-621ca384a7a5efb2cc7597504dc17b741cd2df10.tar.xz |
Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.
Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c')
-rw-r--r-- | src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c | 256 |
1 files changed, 0 insertions, 256 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c deleted file mode 100644 index 2802ba21f7..0000000000 --- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c +++ /dev/null @@ -1,256 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * PCIe port initialization service procedure - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: GNB - * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ -#include "AGESA.h" -#include "Ids.h" -#include "Gnb.h" -#include "GnbPcie.h" -#include "GnbPcieFamServices.h" -#include "PcieFamilyServices.h" -#include GNB_MODULE_DEFINITIONS (GnbCommonLib) -#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) -#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) -#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) -#include "GnbRegistersON.h" -#include "Filecode.h" -#define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -PCIE_PORT_REGISTER_ENTRY PortInitTable [] = { - { - DxF0xE4_x02_ADDRESS, - DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, - (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) - }, - { - DxF0xE4_x70_ADDRESS, - DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, - (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) - }, - { - DxF0xE4_xA0_ADDRESS, - DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK, - (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | - (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) - }, - { - DxF0xE4_xA1_ADDRESS, - DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, - (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) - }, - { - DxF0xE4_xA2_ADDRESS, - DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, - (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | - (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) - }, - { - DxF0xE4_xA3_ADDRESS, - DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, - (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) - }, - { - DxF0xE4_xB1_ADDRESS, - DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, - (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | - (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) - } -}; - - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all active ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie); - PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); - PcieSetLinkWidthCap (Engine, Pcie); - PcieCompletionTimeout (Engine, Pcie); - PcieLinkSetSlotCap (Engine, Pcie); - PcieLinkInitHotplug (Engine, Pcie); - PcieFmPhyChannelCharacteristic (Engine, Pcie); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - if (Engine->Type.Port.PortData.PortPresent == PortDisabled) { - ASSERT (Engine->Type.Port.IsSB == FALSE); - PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); - } - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortInitCallback, - NULL, - Pcie - ); - return Status; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Callback to init various features on all ports - * - * - * - * - * @param[in] Engine Pointer to engine config descriptor - * @param[in, out] Buffer Not used - * @param[in] Pcie Pointer to global PCIe configuration - * - */ - -VOID -STATIC -PciePortPostInitCallback ( - IN PCIe_ENGINE_CONFIG *Engine, - IN OUT VOID *Buffer, - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - PCIE_LINK_SPEED_CAP LinkSpeedCapability; - ASSERT (Engine->EngineData.EngineType == PciePortEngine); - if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { - PcieLinkSafeMode (Engine, Pcie); - } - LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); - PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); - if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) { - PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); - PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); - } - if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { - PcieForceCompliance (Engine, Pcie); - PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Master procedure to init various features on all active ports - * - * - * - * - * @param[in] Pcie Pointer to global PCIe configuration - * @retval AGESA_STATUS - * - */ - -AGESA_STATUS -PciePortPostInit ( - IN PCIe_PLATFORM_CONFIG *Pcie - ) -{ - AGESA_STATUS Status; - Status = AGESA_SUCCESS; - PcieConfigRunProcForAllEngines ( - DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, - PciePortPostInitCallback, - NULL, - Pcie - ); - return Status; -} |