Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

1 files changed, 102 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
new file mode 100755
index 0000000000..b81e267c3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
+{
+  0x1052, 0x1041,
+  0x1053, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
+}
+