Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

82 files changed, 26647 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
new file mode 100755
index 0000000000..4313e08695
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
@@ -0,0 +1,1442 @@
+/**
+ * @file
+ *
+ * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] =
+{
+  // Function 0
+
+// F0x68 - Link Transaction Control
+// bit[14:13], BufPriRel = 02h
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      (AMD_F10_ALL & ~AMD_F10_Dx),          // CpuRevision  rev C or less.
+    },
+    {AMD_PF_MULTI_LINK},                     // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 2
+  // 17:16 NpReqData: 2
+  // 15:12 ProbeCmd: 9
+  // 11:8 RspCmd: 9
+  // 7:5 PReq: 2
+  // 4:0 NpReqCmd: 4
+{
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x10,                               // address
+      0x048A9944,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 4
+  // 4:0 NpReqCmd: 18
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x04850292,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 16
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x008502D0,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 3
+  // 17:16 NpReqData: 2
+  // 15:12 ProbeCmd: 8
+  // 11:8 RspCmd: 9
+  // 7:5 PReq: 2
+  // 4:0 NpReqCmd: 4
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x10,                               // address
+      0x008E8944,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x008502CF,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+{
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x14,                               // address
+      0x00000000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x14,                               // address
+      0x00000000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 1
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x14,                               // address
+      0x02010000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x14,                               // address
+      0x00010000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+
+// Function 3 - Misc. Control
+
+// F3x6C - Data Buffer Control
+// XBAR buffer settings
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
+      0x00018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// XBAR buffer settings
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 2
+// bits[30:28] IsocRspDBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
+      0x00028052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00041153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00051153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x10151153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00081111,                           // regData
+      0x00FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00181111,                           // regData
+      0x00FF7777,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 24
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090A18,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 22
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090A16,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 23
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090917,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 23
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090917,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 21
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090915,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = A
+  {
+    ProcCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),  // anything but two.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A00755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    ProcCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),   // exactly two.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 10
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A11755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 9
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00911755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 5
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00511755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 7
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00711555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = ]
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE),     // 4 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00811755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 2
+// bits[23:20] FreeTok = 2
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00211755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 6
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00611555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00811756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// All non probe filter configs
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 4
+// bits[7:4] ProbeTok = 1
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)),     // 2 Socket, half populated, or 4 Socket, fully populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000014,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)),     // 2 Socket, fully populated, or 4 Socket, half populated.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_GANGED,
+      0x000000AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      0x00550055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 1
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      0x00554055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      0x0000012A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x000001A6,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROBEFILTER,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x0000016A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      0x01550155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 2
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      0x0000022A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 1
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      0x01554155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x000001A6,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 =1
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROBEFILTER,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      0x00000196,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEATURES_ALL,
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      0x0000812A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU)},  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_COHERENT,
+      0x000081AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10MultiLinkPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h
new file mode 100755
index 0000000000..7573da9c8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PackageType.h
@@ -0,0 +1,83 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Package Type Definitions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _F10_PACKAGE_TYPE_H_
+#define _F10_PACKAGE_TYPE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+// Below equates are defined to cooperate with LibAmdGetPackageType.
+#define PACKAGE_TYPE_FR2_FR5_FR6            (1 << 0)
+#define PACKAGE_TYPE_AM2R2_AM3              (1 << 1)
+#define PACKAGE_TYPE_S1G3_S1G4              (1 << 2)
+#define PACKAGE_TYPE_G34                    (1 << 3)
+#define PACKAGE_TYPE_ASB2                   (1 << 4)
+#define PACKAGE_TYPE_C32                    (1 << 5)
+
+#define PACKAGE_TYPE_FR2                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_FR5                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_FR6                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_S1G3                   PACKAGE_TYPE_S1G3_S1G4
+#define PACKAGE_TYPE_S1G4                   PACKAGE_TYPE_S1G3_S1G4
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif  // _F10_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
new file mode 100755
index 0000000000..1e87ce596b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -0,0 +1,287 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB COF VID Initialization
+ *
+ * Performs the "BIOS Northbridge COF and VID Configuration" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "cpuCommonF10Utilities.h"
+#include "F10PmNbCofVidInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Structure used for performing the steps outlined in
+/// the NB COFVID configuration sequence
+typedef struct {
+  UINT8   NewNbVid;           ///< Destination NB VID code
+  BOOLEAN NbVidUpdateAll;     ///< Status of NbVidUpdateAll
+} NB_COF_VID_INIT_WARM;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PmNbCofVidInitP0P1Core (
+  IN       VOID *NewNbVid,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+PmNbCofVidInitWarmCore (
+  IN       VOID *FunctionData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the "Northbridge COF and
+ * VID Configuration" algorithm.
+ *
+ * The steps are as follows:
+ *    1. Determine if the algorithm is necessary by checking if all NB FIDs
+ *       match in the coherent fabric.  If so, check to see if NbCofVidUpdate
+ *       is zero for all CPUs.  If that is also true, no further steps are
+ *       necessary.  If not + cold reset, proceed to step 2.  If not + warm
+ *       reset, proceed to step 8.
+ *    2. Determine NewNbVid & NewNbFid.
+ *    3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
+ *    4. Copy NewNbVid to P0 NbVid on all local cores.
+ *    5. Transition to P1 on all local cores.
+ *    6. Transition to P0 on local core 0 only.
+ *    7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
+ *    8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
+ *       on all local cores.
+ *    9. Transition to Startup Pstate on all local cores.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmNbCofVidInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  BOOLEAN   PerformNbCofVidCfg;
+  BOOLEAN   SystemNbCofsMatch;
+  UINT8     NewNbFid;
+  UINT8     NewNbVid;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Core;
+  UINT32    SystemNbCof;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT32    Ignored;
+  UINT32    NewNbVoltage;
+  WARM_RESET_REQUEST Request;
+  AP_TASK   TaskPtr;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+  NB_COF_VID_INIT_WARM FunctionData;
+
+  PerformNbCofVidCfg = TRUE;
+  OptionMultiSocketConfiguration.GetSystemNbCof (&SystemNbCof, &SystemNbCofsMatch, StdHeader);
+  if (SystemNbCofsMatch) {
+    if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
+      PerformNbCofVidCfg = FALSE;
+    }
+  }
+  if (PerformNbCofVidCfg) {
+    // get the local node ID
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+    ASSERT (Core == 0);
+
+    // get NewNbVid
+    FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, &Ignored, &NewNbVoltage, StdHeader);
+    ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
+    NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
+    ASSERT (NewNbVid < 0x80);
+
+    if (!(IsWarmReset (StdHeader))) {
+
+      // determine NewNbFid
+      NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
+
+      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
+      TaskPtr.DataTransfer.DataSizeInDwords = 1;
+      TaskPtr.DataTransfer.DataPtr = &NewNbVid;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = 0;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+      // Transition core 0 to P0 and wait for change to complete
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+
+      PciAddress.Address.Register = CPTC0_REG;
+      AndMask = 0xFFFFFFFF;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
+      OrMask = 0x00000000;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
+      ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+      // warm reset request
+      FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
+      Request.RequestBit = TRUE;
+      FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
+    } else {
+      // warm reset path
+
+      FunctionData.NewNbVid = NewNbVid;
+      FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
+
+      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
+      TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
+      TaskPtr.DataTransfer.DataPtr = &FunctionData;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = WAIT_FOR_CORE;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+    }
+  } // skip whole algorithm
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Cold reset support routine for F10PmNbCofVidInit.
+ *
+ * This function implements steps 3, 4, & 5 on each core.
+ *
+ * @param[in]  NewNbVid           NewNbVid determined by core 0 in step 2.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbCofVidInitP0P1Core (
+  IN       VOID *NewNbVid,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 MsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
+  LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
+  ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
+  LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Warm reset support routine for F10PmNbCofVidInit.
+ *
+ * This function implements steps 8 & 9 on each core.
+ *
+ * @param[in]  FunctionData       Contains NewNbVid determined by core 0 in step
+ *                                2, and NbVidUpdateAll.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbCofVidInitWarmCore (
+  IN       VOID *FunctionData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 MsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
+    LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
+        ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
+        LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+      }
+    }
+  }
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (((COFVID_STS_MSR *) &MsrRegister)->StartupPstate), (BOOLEAN) FALSE, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
new file mode 100755
index 0000000000..4e6f3e4e10
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB COF VID Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
+#define _CPU_F10_PM_NB_COF_VID_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmNbCofVidInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_PM_NB_COF_VID_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
new file mode 100755
index 0000000000..455f312090
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -0,0 +1,186 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB Pstate Initialization
+ *
+ * Performs the action described in F3x1F0[NbPstate] as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "F10PmNbPstateInit.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Structure used for modifying the P-state
+/// MSRs on fuse enable CPUs.
+typedef struct {
+  UINT8   NbVid1;             ///< Destination NB VID code
+  UINT8   NbPstate;           ///< Status of NbVidUpdateAll
+} NB_PSTATE_INIT;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PmNbPstateInitCore (
+  IN       VOID *NbPstateParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the actions described in the
+ * description of F3x1F0[NbPstate].
+ *
+ * If F3x1F0[NbPstate] is non zero, it specifies the highest performance
+ * P-state in which to enable NbDid.  Each core must loop through their
+ * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmNbPstateInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32         Core;
+  UINT32         Module;
+  UINT32         PciRegister;
+  UINT32         ProcessorPackageType;
+  UINT32         Socket;
+  AP_TASK        TaskPtr;
+  PCI_ADDR       PciAddress;
+  AGESA_STATUS   IgnoredSts;
+  NB_PSTATE_INIT ApParams;
+
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, StdHeader)) {
+    ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+    if ((CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) ||
+        (ProcessorPackageType != PACKAGE_TYPE_S1G3_S1G4)) {
+      IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+      ASSERT (Core == 0);
+      GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = 0x1F0;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if ((PciRegister & 0x00070000) != 0) {
+        ApParams.NbPstate = (UINT8) ((PciRegister & 0x00070000) >> 16);
+        ASSERT (ApParams.NbPstate < NM_PS_REG);
+
+        PciAddress.Address.Function = FUNC_4;
+        PciAddress.Address.Register = 0x1F4;
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+        ApParams.NbVid1 = (UINT8) ((PciRegister & 0x00003F80) >> 7);
+
+        TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
+        TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
+        TaskPtr.DataTransfer.DataPtr = &ApParams;
+        TaskPtr.DataTransfer.DataTransferFlags = 0;
+        TaskPtr.ExeFlags = WAIT_FOR_CORE;
+        ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmNbPstateInit.
+ *
+ * This function modifies NbVid and NbDid on each core.
+ *
+ * @param[in]  NbPstateParams     Appropriate NbVid1 and NbPstate as determined by core 0.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbPstateInitCore (
+  IN       VOID *NbPstateParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 MsrRegister;
+
+  for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
+    LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      ((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
+      ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
+      LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
new file mode 100755
index 0000000000..d4c868cd02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * AMD Family_10 NB P-State Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 6524 $   @e \$Date: 2008-06-24 17:00:51 -0500 (Tue, 24 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
+#define _CPU_F10_PM_NB_PSTATE_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmNbPstateInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_PM_NB_PSTATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
new file mode 100755
index 0000000000..a97214ad1a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
@@ -0,0 +1,1267 @@
+/**
+ * @file
+ *
+ * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] =
+{
+// F0x68 - Link Transaction Control
+// bit[14:13], BufPriRel = 01b
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                     // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00002000,                           // regData
+      0x00006000,                           // regMask
+    }
+  },
+// F0x68 - Link Transaction Control
+// bit[24], DispRefModeEn = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_ALL,                             // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00000000,                           // regData
+      0x01000000,                           // regMask
+    }
+  },
+// F0x68 - Link Transaction Control
+// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_UMA,                     // platform Features
+    {
+      PERFORMANCE_IS_WARM_RESET,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x01000000,                           // regData
+      0x01000000,                           // regMask
+    }
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 3
+  // 4:0 NpReqCmd: 11
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x0885026B,                           // Data
+      0x0FFFFFFF                            // Mask
+    },
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x008502CF,                           // Data
+      0x0FFFFFFF                            // Mask
+    },
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 1
+  // 18:16 IsocNpReqCmd: 7
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x000F0000,                           // Data
+      0x1FFF0000                            // Mask
+    },
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),
+    {
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x00010000,                           // Data
+      0x1FFF0000                            // Mask
+    },
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// bit[8] LS2En = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                     // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 10b
+// bits[31:28] MctVarPriCntLmt = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x00002000,                           // regData
+      0xF0003000,                           // regMask
+    }
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 11b
+// bits[31:28] MctVarPriCntLmt = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),       // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x10003000,                           // regData
+      0xF0003000,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32  0
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
+      0x00000000,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 0
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
+      0x00000000,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 1
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
+      0x00000400,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 1
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA | AMD_PF_UMA_IFCM),        // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
+      0x00000400,                           // regData
+      0x00000400,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x00018052,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x60018051,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x60018051,                           // regData
+      0x700780F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00041153,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 2
+// bits[22:20] IsocReqCBC = 2
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x61221151,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 2
+// bits[22:20] IsocReqCBC = 2
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x61221151,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x11141153,                           // regData
+      0x777777F7,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00081111,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = 9
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x91180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = 9
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x91180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = C
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xC1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = C
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xC1181111,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = F
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xF1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = F
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xF1181111,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 8
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x01880101,                           // regData
+      0xF7FF7777,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x007FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080C,                           // regData
+      0x007FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080C,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 9
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070809,                           // regData
+      0x007FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 9
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070809,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 17
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070811,                           // regData
+      0x707FFF1F,                           // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000016,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20, 2-core is 20
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000014,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000012,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000010,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x0000000E,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x0000000C,                               // regData
+      0x0000001F,                               // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 2
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37656,                           // regData
+      0x00F3FFFF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 1
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x8000152A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 1
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x8000152A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),  // platform Features
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }
+  },
+  // F3x158 - Link to XCS Token Count Registers
+  // bits [3:0]LnkToXcsDRToken = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU),
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000000,
+      0x0000000F
+    }
+  },
+  // F3x158 - Link to XCS Token Count Registers
+  // bits [3:0]LnkToXcsDRToken = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    (AMD_PF_UMA_IFCM | AMD_PF_UMA),
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,
+      0x0000000F
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10SingleLinkPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
new file mode 100755
index 0000000000..c4f819a062
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -0,0 +1,146 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/BL
+ * @e \$Revision: 10071 $   @e \$Date: 2008-12-17 08:03:04 +0800 (Wed, 17 Dec 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable BL-C Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in,out]   PciAddress               Pointer to Pci address struct.
+ *    @param[in,out]   AndMask                  Pointer to AND mask bits.
+ *    @param[in,out]   OrMask                   Pointer to Or mask bits.
+ *    @param[in]       StdHeader                Handle of Header for calling lib functions and services.
+ */
+VOID
+GetF10BlCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN OUT   PCI_ADDR                     *PciAddress,
+  IN OUT   UINT32                       *AndMask,
+  IN OUT   UINT32                       *OrMask,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32     CoreCount;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
+    //
+    // F3xDC[25:19] = 04h
+    // F3xDC[18:16] = 111b
+    //
+    *AndMask = 0xFC00FFFF;
+    *OrMask = 0x00270000;
+  } else {
+    //
+    // F3xDC[25:19] = 28h
+    // F3xDC[18:16] = 111b
+    //
+    *AndMask = 0xFC00FFFF;
+    *OrMask = 0x01470000;
+
+    //
+    //For BL_C2 single Core, F3xDC[18:16] = 0
+    //
+    GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+    if (CoreCount == 1) {
+      if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
+        *OrMask = 0x01400000;
+      }
+    }
+  }
+
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
+{
+  0,
+  GetF10BlCacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
new file mode 100755
index 0000000000..b81e267c3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
+{
+  0x1052, 0x1041,
+  0x1053, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
new file mode 100755
index 0000000000..a3d744ccf9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT  Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
+{
+
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+//
+// Deemphasis Settings
+//
+
+// For BL-C3, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_BL_C3                         // CpuRevision
+    },
+    AMD_PF_ALL,                             // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10BlHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
new file mode 100755
index 0000000000..32a9fcb802
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] =
+{
+  {
+    0x1052,
+    AMD_F10_BL_C2
+  },
+  {
+    0x1053,
+    AMD_F10_BL_C3
+  }
+};
+
+VOID
+GetF10BlLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **BlIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *BlIdPtr = CpuF10BlLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_BL;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
+//};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
new file mode 100755
index 0000000000..2a1bfa9a56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10BlMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
new file mode 100755
index 0000000000..fb7a30ddc3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
new file mode 100755
index 0000000000..c3bbb55e23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
@@ -0,0 +1,174 @@
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
+{
+  // Function 0
+
+// F0x16C - Link Global Extended Control Register, Errata 351
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C2                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// Errata 351 (only need to override single link case.)
+// bit[8] LS2En = 0,
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C2                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000000,                           // regData
+      0x00000100,                           // regMask
+    }
+  },
+
+
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_Cx                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEATURES_ALL,                 // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000000,                           // regData
+      0x10000000,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10BlPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
new file mode 100755
index 0000000000..c1c9db0f33
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/DA
+ * @e \$Revision: 10071 $   @e \$Date: 2008-12-17 08:03:04 +0800 (Wed, 17 Dec 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable DA-C Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in,out]   PciAddress               Pointer to Pci address struct.
+ *    @param[in,out]   AndMask                  Pointer to AND mask bits.
+ *    @param[in,out]   OrMask                   Pointer to Or mask bits.
+ *    @param[in]       StdHeader                Handle of Header for calling lib functions and services.
+ */
+VOID
+GetF10DaCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN OUT   PCI_ADDR                     *PciAddress,
+  IN OUT   UINT32                       *AndMask,
+  IN OUT   UINT32                       *OrMask,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32     CoreCount;
+  CPU_LOGICAL_ID LogicalId;
+
+  //
+  // F3xDC[25:19] = 04h
+  // F3xDC[18:16] = 111b
+  //
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  *AndMask = 0xFC00FFFF;
+  *OrMask = 0x00270000;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if (LogicalId.Revision == AMD_F10_DA_C2) {
+    //
+    //For DA_C2 single Core, F3xDC[18:16] = 0
+    //
+    GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+    if (CoreCount == 1) {
+      *OrMask = 0x00200000;
+    }
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt =
+{
+  0,
+  GetF10DaCacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
new file mode 100755
index 0000000000..afedd8890d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
+{
+  0x1062, 0x1062,
+  0x1063, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  DaEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10DaMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **DaEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
new file mode 100755
index 0000000000..91ac42329e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
@@ -0,0 +1,278 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] =
+{
+
+//
+// Deemphasis Settings
+//
+
+// For DA, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10DaHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
new file mode 100755
index 0000000000..0917fb3173
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -0,0 +1,102 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] =
+{
+  {
+    0x1062,
+    AMD_F10_DA_C2
+  },
+  {
+    0x1063,
+    AMD_F10_DA_C3
+  }
+};
+
+VOID
+GetF10DaLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **DaIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *DaIdPtr = CpuF10DaLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_DA;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
+//};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
new file mode 100755
index 0000000000..48a8cd0bb1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  DaUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10DaMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **DaUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10DaMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
new file mode 100755
index 0000000000..836760aacc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
new file mode 100755
index 0000000000..77305cb549
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
@@ -0,0 +1,172 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] =
+{
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }
+  },
+
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_Cx                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEATURES_ALL,                 // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 1
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000800,                           // regData
+      0x10003800,                           // regMask
+    }
+  },
+// F3xD4 - Clock Power/Timing Control 0 Register
+// bits[30:28] NbClkDiv = 5
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_C2                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEAT_HT3,                     // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0x50000000,                           // regData
+      0x70000000,                           // regMask
+    }
+  },
+// F3x188 - NB Extended Configuration Low Register
+// bits[4] EnStpGntOnFlushMaskWakeup = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_Cx                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00000010,                           // regData
+      0x00000010,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10DaPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
new file mode 100755
index 0000000000..949b846463
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 5832 $   @e \$Date: 2008-04-15 16:30:24 -0700 (Tue, 15 Apr 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000085 for 1040 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 =
+{
+0x08,
+0x20,
+0x01,
+0x05,
+0x85,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xc1,
+0xb9,
+0x5d,
+0x3d,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x40,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x2f,
+0x02,
+0x00,
+0x00,
+0xa0,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xcf,
+0xf8,
+0xff,
+0x2a,
+0xc3,
+0x3f,
+0xd5,
+0xfd,
+0xbc,
+0xff,
+0xff,
+0xb3,
+0x0f,
+0xff,
+0x58,
+0xd5,
+0xf0,
+0x35,
+0x95,
+0x03,
+0x1d,
+0xf8,
+0x63,
+0x7b,
+0x40,
+0x03,
+0xd4,
+0x00,
+0x80,
+0x77,
+0xff,
+0x7f,
+0xfe,
+0xe1,
+0x98,
+0x8a,
+0x54,
+0xfe,
+0xaf,
+0xff,
+0xff,
+0x87,
+0x7f,
+0xa9,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x1f,
+0xc0,
+0x65,
+0xf4,
+0x0d,
+0xf0,
+0xe0,
+0x8f,
+0xfe,
+0x04,
+0xde,
+0x04,
+0x03,
+0xad,
+0xc3,
+0x2f,
+0xfe,
+0xa9,
+0xfc,
+0x07,
+0x00,
+0x3f,
+0x0f,
+0xff,
+0x15,
+0x00,
+0xb0,
+0x00,
+0xf8,
+0xaf,
+0xe4,
+0x3f,
+0x07,
+0xf8,
+0x79,
+0xf8,
+0xfe,
+0xff,
+0x97,
+0xa7,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0xbf,
+0xf1,
+0x00,
+0xfe,
+0x7f,
+0x6f,
+0x80,
+0x03,
+0x4a,
+0x1a,
+0x00,
+0xc8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xfb,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfd,
+0x6b,
+0x00,
+0xa0,
+0xcf,
+0x56,
+0x0e,
+0x80,
+0xe0,
+0x0f,
+0xe8,
+0x75,
+0xf6,
+0xff,
+0xff,
+0x00,
+0xc3,
+0xbb,
+0x16,
+0xf2,
+0x04,
+0x37,
+0xf8,
+0x13,
+0x0e,
+0x7f,
+0x0c,
+0xb8,
+0xe0,
+0xdc,
+0x35,
+0x00,
+0x60,
+0xff,
+0xff,
+0x1f,
+0x7f,
+0x78,
+0xc7,
+0xa2,
+0x95,
+0xff,
+0xe9,
+0x3f,
+0xdf,
+0xe0,
+0xcf,
+0x2a,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0xff,
+0xf2,
+0xbf,
+0xff,
+0xfd,
+0x1f,
+0xfc,
+0x7b,
+0x0f,
+0xc0,
+0x23,
+0xd0,
+0xed,
+0xf5,
+0xe0,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfe,
+0x03,
+0xf9,
+0x5f,
+0x01,
+0x7e,
+0x1e,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x4c,
+0x06,
+0x00,
+0xbc,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c
new file mode 100755
index 0000000000..e25ca890f1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000086 for 1041 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 5832 $   @e \$Date: 2008-04-15 16:30:24 -0700 (Tue, 15 Apr 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000086 for 1041 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000086 =
+{
+0x08,
+0x20,
+0x01,
+0x05,
+0x86,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0x04,
+0xde,
+0x30,
+0x03,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x41,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0xa0,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x97,
+0xd1,
+0x7f,
+0x00,
+0x83,
+0x3f,
+0x36,
+0xc0,
+0xa0,
+0x1b,
+0xf8,
+0x13,
+0x0e,
+0xbf,
+0x0c,
+0xb4,
+0xf2,
+0x1f,
+0xf8,
+0xa7,
+0x3c,
+0xfc,
+0x03,
+0xfc,
+0x40,
+0x03,
+0x54,
+0x00,
+0x92,
+0xff,
+0xe0,
+0xbf,
+0xe7,
+0xe1,
+0x1f,
+0xe0,
+0x5f,
+0x9e,
+0xfa,
+0xff,
+0x9f,
+0x87,
+0x7f,
+0x80,
+0x03,
+0xf8,
+0xff,
+0xc6,
+0x01,
+0x0e,
+0xfc,
+0xbd,
+0x00,
+0xa0,
+0x2a,
+0x69,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0xff,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xfb,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfd,
+0x6b,
+0x00,
+0xa0,
+0xff,
+0xfe,
+0xff,
+0xcb,
+0xf0,
+0xef,
+0xf5,
+0x7f,
+0x8f,
+0x40,
+0x3f,
+0x00,
+0x83,
+0xbf,
+0xb7,
+0xd7,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe4,
+0x7f,
+0xf9,
+0x0f,
+0x79,
+0xf8,
+0x07,
+0xf8,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf0,
+0x32,
+0x19,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c
new file mode 100755
index 0000000000..090cd918da
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000098 for 1062 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000098 for 1062 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000098 =
+{
+0x08,
+0x20,
+0x11,
+0x11,
+0x98,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xf8,
+0x53,
+0xca,
+0x9a,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x62,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x9a,
+0x0b,
+0x00,
+0x00,
+0x16,
+0x0c,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x6f,
+0x58,
+0x39,
+0x00,
+0x81,
+0x3f,
+0xa0,
+0xd7,
+0x04,
+0x00,
+0xfc,
+0xb7,
+0x0f,
+0xff,
+0x58,
+0xf7,
+0x72,
+0xc0,
+0xff,
+0x6f,
+0x3c,
+0xfc,
+0x03,
+0xfc,
+0xc0,
+0x18,
+0xd5,
+0x00,
+0x80,
+0xff,
+0x66,
+0x3c,
+0xeb,
+0xc0,
+0x9f,
+0xd9,
+0x4d,
+0xee,
+0xf8,
+0xff,
+0xff,
+0x83,
+0x7f,
+0xa6,
+0x07,
+0xe8,
+0xff,
+0xff,
+0xe8,
+0x1f,
+0xbe,
+0xb5,
+0x00,
+0x60,
+0x2f,
+0x6a,
+0x0e,
+0xc0,
+0xd3,
+0x37,
+0x08,
+0x70,
+0xe0,
+0x0f,
+0xff,
+0xaf,
+0x13,
+0xfc,
+0xd7,
+0xcf,
+0xc3,
+0xbf,
+0xeb,
+0x01,
+0xfc,
+0x67,
+0xde,
+0x00,
+0x0f,
+0xfe,
+0x35,
+0x00,
+0xd0,
+0x00,
+0xff,
+0x1f,
+0x40,
+0xfc,
+0xc7,
+0x42,
+0x7e,
+0x78,
+0xef,
+0xff,
+0x16,
+0xfe,
+0x0f,
+0x60,
+0xcb,
+0xe1,
+0xb7,
+0x72,
+0x00,
+0xee,
+0x7e,
+0x00,
+0x9f,
+0x83,
+0x9f,
+0x1a,
+0x00,
+0x58,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x00,
+0xfa,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0xe0,
+0xf8,
+0xff,
+0x7f,
+0x8b,
+0xf0,
+0x0f,
+0x70,
+0xd6,
+0xff,
+0xdb,
+0x7f,
+0x2c,
+0xc3,
+0x3f,
+0xd6,
+0xe2,
+0xfc,
+0x67,
+0xeb,
+0x01,
+0x0f,
+0xfd,
+0x5e,
+0x3e,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c
new file mode 100755
index 0000000000..ae26d0f563
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000B6 for 1043 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000b6 for 1043 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000b6 =
+{
+0x09,
+0x20,
+0x31,
+0x07,
+0xb6,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xe9,
+0x98,
+0xda,
+0x6b,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x43,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x10,
+0x0c,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x18,
+0x80,
+0x38,
+0xc0,
+0x83,
+0x37,
+0x80,
+0xff,
+0xb8,
+0xff,
+0xff,
+0x13,
+0x0e,
+0xbf,
+0x0c,
+0xb6,
+0x7a,
+0xc4,
+0xff,
+0x2f,
+0x3c,
+0xfc,
+0x6b,
+0xfd,
+0x40,
+0x03,
+0xd4,
+0x00,
+0x97,
+0xff,
+0xff,
+0xff,
+0xe7,
+0xe1,
+0x1f,
+0xe0,
+0x00,
+0xfe,
+0xbf,
+0xf5,
+0x9f,
+0x87,
+0x7e,
+0x22,
+0x01,
+0xc6,
+0x00,
+0xc4,
+0x7c,
+0x1e,
+0xfa,
+0x01,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0xff,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0x20,
+0x04,
+0xff,
+0xbf,
+0xe8,
+0xf0,
+0xaf,
+0xf5,
+0xf3,
+0xff,
+0xd9,
+0x7a,
+0x00,
+0x83,
+0x3f,
+0x31,
+0xc0,
+0x0c,
+0x7d,
+0xe3,
+0x00,
+0x0f,
+0xfe,
+0x80,
+0x5e,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0x65,
+0xfe,
+0xff,
+0x9f,
+0x7f,
+0xf8,
+0xc7,
+0xba,
+0x96,
+0xf2,
+0xff,
+0x7f,
+0xfa,
+0xe1,
+0x1f,
+0xeb,
+0x45,
+0x0e,
+0xf8,
+0xff,
+0x9f,
+0x87,
+0x7f,
+0x80,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x5f,
+0x8c,
+0x7b,
+0x1d,
+0xf8,
+0x13,
+0xbf,
+0xe8,
+0x1a,
+0xff,
+0xf4,
+0xf3,
+0xf0,
+0x4f,
+0xff,
+0x2f,
+0xe3,
+0xff,
+0xd7,
+0xf5,
+0xc3,
+0xbf,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xd6,
+0x03,
+0xf8,
+0xdf,
+0x89,
+0x01,
+0x1e,
+0xfc,
+0xfb,
+0x0f,
+0xe0,
+0x3f,
+0xd6,
+0xa2,
+0x7f,
+0xf8,
+0xff,
+0x7f,
+0x82,
+0xff,
+0x97,
+0xc1,
+0xd6,
+0xe1,
+0x40,
+0x02,
+0x00,
+0x14,
+0x7f,
+0xff,
+0x01,
+0xfc,
+0xdf,
+0x5a,
+0xf4,
+0x0f,
+0xfe,
+0xff,
+0xef,
+0x32,
+0xfc,
+0x03,
+0x9c,
+0x35,
+0x7f,
+0xf7,
+0x5f,
+0xcb,
+0xf0,
+0xaf,
+0xf5,
+0xff,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x5a,
+0x87,
+0x5f,
+0xad,
+0x2b,
+0xf8,
+0xdf,
+0xd6,
+0x03,
+0x1e,
+0xfa,
+0x89,
+0x7c,
+0x20,
+0x7d,
+0xc0,
+0x9f,
+0x75,
+0xf8,
+0x65,
+0xb0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0xdb,
+0x7a,
+0xc0,
+0x83,
+0x3f,
+0x31,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xf4,
+0x0f,
+0xdf,
+0x5a,
+0x4f,
+0xa0,
+0x3e,
+0xe0,
+0xd8,
+0x3a,
+0xfc,
+0x32,
+0x00,
+0xc0,
+0x01,
+0x48,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
new file mode 100755
index 0000000000..a15cad701f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
@@ -0,0 +1,436 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
+{
+// 0x60:0x68
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0x60, 0x68,                           // Address range
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0x70:0x78
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0x70, 0x78,                           // Address range
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// Erratum 354
+// 0x40:48
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_C2 | AMD_F10_C3)           // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0x40, 0x48,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0x50:0x58
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_C2 | AMD_F10_C3)          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0x50, 0x58,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0xC0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0xC0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }
+  },
+// 0xD0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0xD0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }
+  },
+// 0xCF
+// FIFO_PTR_OPT_VALUE
+  {
+    HtPhyProfileRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      PERFORMANCE_NB_PSTATES_ENABLE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// 0xDF
+// FIFO_PTR_OPT_VALUE
+  {
+    HtPhyProfileRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      PERFORMANCE_NB_PSTATES_ENABLE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }
+  },
+// 0x520A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                           // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_ALL,                   //
+      0x520A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }
+  },
+// 0x530A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                           // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_ALL,                   //
+      0x530A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }
+  },
+
+
+
+
+//
+// Deemphasis Settings
+//
+
+// For C3, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RevCHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
new file mode 100755
index 0000000000..93b9216251
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -0,0 +1,178 @@
+/**
+ * @file
+ *
+ * AMD Family_10 HW C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the hardware C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuHwC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeHwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should hardware C1e be enabled
+ *
+ * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsHwC1eSupported (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e on a family 10h CPU.
+ *
+ * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeHwC1e (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+  AP_TASK TaskPtr;
+
+  MsrRegister = 0;
+  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
+  ((INTPEND_MSR *) &MsrRegister)->IoMsgData = 0xC1;
+  ((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
+  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
+  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
+
+  TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &MsrRegister;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e on a family 10h core.
+ *
+ * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeHwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  MsrRegister;
+
+  // Enable C1e
+  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
+
+  // Set OS Visible Workaround Status BIT1 to indicate that C1e
+  // is enabled.
+  LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
+  MsrRegister |= BIT1;
+  LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
+}
+
+
+CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
+{
+  0,
+  F10IsHwC1eSupported,
+  F10InitializeHwC1e
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
new file mode 100755
index 0000000000..bd1f788ca6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
@@ -0,0 +1,130 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// bit[21] = 1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_BU_CFG,                           // MSR Address
+      (1 << 21),                            // OR Mask
+      (1 << 21),                            // NAND Mask
+    }
+  },
+
+// MSR_BU_CFG2 (0xC001102A)
+// bit[50] = 1
+// For GH rev C1 and later [RdMmExtCfgQwEn]=1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MSR_BU_CFG2,                          // MSR Address
+      0x0004000000000000,                   // OR Mask
+      0x0004000000000000,                   // NAND Mask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
new file mode 100755
index 0000000000..6abe3895e6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
@@ -0,0 +1,261 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/RevC
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
+{
+// Function 2 - DRAM Controller
+
+// F2x1B0 - Extended Memory Controller Configuration Low Register
+//
+// bit[5:4], AdapPrefNegativeStep = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
+      0x00000000,                           // regData
+      0x00000030,                           // regMask
+    }
+  },
+// Function 3 - Misc. Control
+
+// F3x158 - Link to XCS Token Count
+// bits[3:0] LnkToXcsDRToken = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    AMD_PF_UMA,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,                           // regData
+      0x0000000F,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C2
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 1
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000E681,                           // regData
+      0x0000FFFF,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEAT_HT1,                     // link feats
+      PACKAGE_TYPE_ASB2,                    // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x00008700,                           // regData
+      0x0000FF00,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 1
+// bits[7:5] ClkDivisor = 7
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                           // CpuRevision
+    },
+    AMD_PF_ALL,                             // platformFeatures
+    {
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000F600,                           // regData
+      0x0000FF00,                           // regMask
+    }
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                   // platformFeatures
+    {
+      HT_HOST_FEAT_HT1,                     // link feats
+      PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2),  // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x00008700,                           // regData
+      0x0000FF00,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }
+  },
+// F3x180 - NB Extended Configuration
+// bits[23] SyncFloodOnDramTempErr = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x00800000,                           // regData
+      0x00800000,                           // regMask
+    }
+  },
+// F3x188 - NB Extended Configuration Low Register
+// Must be set by BIOS
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00400000,                           // regData
+      0x00400000,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RevCPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
new file mode 100755
index 0000000000..06a4fa7632
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -0,0 +1,401 @@
+/**
+ * @file
+ *
+ * AMD Family_10 revision Cx specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h rev C.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "GeneralServices.h"
+#include "cpuEarlyInit.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on a revision C processor.
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+F10CommonRevCSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    TempVar32_a;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS AgesaStatus;
+
+  switch (*LeveledCores) {
+  case 1:
+    CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    break;
+  case 2:
+    CoreDisableBits = DOWNCORE_MASK_DUAL;
+    break;
+  case 3:
+    CoreDisableBits = DOWNCORE_MASK_TRI;
+    break;
+  default:
+    CoreDisableBits = 0;
+    break;
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a = (TempVar32_a >> 12) & 0x3;
+      if (TempVar32_a == 0) {
+        CoreDisableBits &= 0x1;
+      } else if (TempVar32_a == 1) {
+        CoreDisableBits &= 0x3;
+      } else if (TempVar32_a == 2) {
+        CoreDisableBits &= 0x7;
+      } else if (TempVar32_a == 3) {
+        CoreDisableBits &= 0x0F;
+      }
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a |= CoreDisableBits;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+    }
+  }
+
+  return;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
+{
+  0,
+  F10CommonRevCSetDownCoreRegister
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current on a revision C processor.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F10CommonRevCGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       IddDiv;
+  UINT32       CmpCap;
+  UINT32       PciRegister;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Ignored;
+  UINT32       MsrAddress;
+  UINT32       SinglePlaneNbIdd;
+  UINT64       PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
+  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
+    CmpCap++;
+
+    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
+    case 0:
+      IddDiv = 1000;
+      break;
+    case 1:
+      IddDiv = 100;
+      break;
+    case 2:
+      IddDiv = 10;
+      break;
+    default:  // IddDiv = 3 is reserved. Use 10
+      ASSERT (FALSE);
+      IddDiv = 10;
+      break;
+    }
+
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
+    if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
+      *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
+    } else {
+      PciAddress.Address.Register = PRCT_INFO_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
+      SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &PciRegister)->SinglePlaneNbIdd;
+      SinglePlaneNbIdd <<= 1;
+      *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
+    }
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F10CommonRevCGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProductInfoRegister;
+
+  PciAddress->Address.Register = PRCT_INFO_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+  *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
+  return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[out]  VoltageInuV              Northbridge voltage in uV.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS     Always succeeds.
+ */
+AGESA_STATUS
+F10CommonRevCGetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProductInfoRegister;
+  UINT32 PciRegister;
+  UINT32 NbFid;
+  UINT32 NbVid;
+  UINT64 MsrRegister;
+
+  PciAddress->Address.Register = PRCT_INFO_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+  if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
+    PciAddress->Address.Register = CPTC0_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
+    NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+    NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
+  } else {
+    NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
+    NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
+    PciAddress->Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
+    if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 0) {
+      NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
+      NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
+    }
+  }
+  *FrequencyInMHz = ((NbFid + 4) * 200);
+  *VoltageInuV = (1550000 - (12500 * NbVid));
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F10CommonRevCIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32         Core;
+  UINT32         Module;
+  UINT32         NbPstate;
+  UINT32         Socket;
+  PCI_ADDR       PciAddress;
+  AGESA_STATUS   IgnoredSts;
+  CPU_LOGICAL_ID LogicalId;
+  BOOLEAN        Result;
+
+  Result = FALSE;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F10_C3) != 0) {
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = 0x1F0;
+    LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
+    if (NbPstate != 0) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get number of processor cores to be used in determining the brand string.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of cores to be used in brand string calculation.
+ */
+UINT8
+F10CommonRevCGetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Core;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = NB_CAPS_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
new file mode 100755
index 0000000000..79858d24a9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -0,0 +1,105 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
+{
+  0x1040, 0x1040,
+  0x1041, 0x1041,
+  0x1042, 0x1041,
+  0x1043, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  RbEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10RbMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **RbEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
new file mode 100755
index 0000000000..424f5ca31a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -0,0 +1,115 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] =
+{
+// Erratum 354
+// 0x40:0x48
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C1)                     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0x40, 0x48,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+// 0x50:0x58
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C1)                     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0x50, 0x58,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RbHtPhyRegisters
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
new file mode 100755
index 0000000000..c9d5aed20f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
@@ -0,0 +1,109 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] =
+{
+  {
+    0x1040,
+    AMD_F10_RB_C0
+  },
+  {
+    0x1041,
+    AMD_F10_RB_C1
+  },
+  {
+    0x1042,
+    AMD_F10_RB_C2
+  },
+  {
+    0x1043,
+    AMD_F10_RB_C3
+  }
+};
+
+VOID
+GetF10RbLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **RbIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *RbIdPtr = CpuF10RbLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_RB;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray
+//};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
new file mode 100755
index 0000000000..7362ebdbd6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -0,0 +1,104 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB microcode patches
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  RbUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10RbMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **RbUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10RbMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
new file mode 100755
index 0000000000..a4c0a91129
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
@@ -0,0 +1,115 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_DC_CFG (0xC0011022)
+// bits[43:42] = 0
+// Errata #326
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                       // CpuFamily
+      AMD_F10_RB_C0                        // CpuRevision
+    },
+    AMD_PF_MULTI_LINK,                     // platformFeatures
+    {
+      MSR_DC_CFG,                            // MSR Address
+      0x0000000000000000,                    // OR Mask
+      0x00000C0000000000,                    // NAND Mask
+    }
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// Erratum #309 BU_CFG[23]=1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                            // platformFeatures
+    {
+      MSR_BU_CFG,                            // MSR Address
+      (1 << 23),                             // OR Mask
+      (1 << 23),                             // NAND Mask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
new file mode 100755
index 0000000000..6bfe0b6303
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -0,0 +1,212 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] =
+{
+  // Function 0
+
+// F0x16C - Link Global Extended Control Register, Errata 351
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                       // CpuRevision
+    },
+    AMD_PF_SINGLE_LINK,                // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// Errata 351 (only need to override single link case.)
+// bit[8] LS2En = 0,
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+     (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000000,                           // regData
+      0x00000100,                           // regMask
+    }
+  },
+
+
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C0                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00002800,                           // regData
+      0x00003800,                           // regMask
+    }
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                       // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000000,                           // regData
+      0x10000000,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_ALL                      // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00006000,                           // regData
+      0x00007000,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C0                          // CpuRevision
+    },
+    AMD_PF_ALL,                           // platformFeatures
+    {
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                            // CpuRevision
+    },
+    AMD_PF_ALL,                             // platformFeatures
+    {
+      PERFORMANCE_NB_PSTATES_ENABLE,        // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RbPciRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
new file mode 100755
index 0000000000..a86f326b8d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
@@ -0,0 +1,1037 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c4 for 1081 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVD
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c4 for 1081 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4 =
+{
+{
+0x10,
+0x20,
+0x03,
+0x03,
+0xc4,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x01,
+0x4a,
+0xe0,
+0x9c,
+0x93,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x81,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0xa7,
+0x0b,
+0x00,
+0x00,
+0x14,
+0x0c,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0x51,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x4f,
+0xdf,
+0x38,
+0x00,
+0x81,
+0x3f,
+0x20,
+0xc0,
+0x4e,
+0xf0,
+0xff,
+0xbf,
+0x0f,
+0xff,
+0x5e,
+0x3f,
+0xf0,
+0xdf,
+0xad,
+0x07,
+0x3d,
+0xf8,
+0x7b,
+0x7b,
+0xc0,
+0x00,
+0xd4,
+0x00,
+0x13,
+0xf1,
+0xff,
+0xff,
+0xac,
+0xe1,
+0x1f,
+0xe0,
+0x4e,
+0xfe,
+0xbb,
+0xff,
+0xfe,
+0x87,
+0x7f,
+0xa7,
+0x03,
+0xf8,
+0x7f,
+0xd6,
+0x7c,
+0x1e,
+0xfa,
+0xbd,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x0e,
+0x00,
+0x3d,
+0x57,
+0xe0,
+0x73,
+0xd0,
+0x0f,
+0xff,
+0x2e,
+0xfe,
+0xff,
+0xc0,
+0xcf,
+0xc3,
+0x3f,
+0xeb,
+0x01,
+0xfc,
+0x77,
+0x5a,
+0x3e,
+0x0f,
+0xfd,
+0x35,
+0x00,
+0x90,
+0x3e,
+0xff,
+0x9f,
+0xe0,
+0xfd,
+0x65,
+0x60,
+0x75,
+0xf8,
+0x9f,
+0xff,
+0x97,
+0xff,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0x03,
+0xf5,
+0xde,
+0xff,
+0x7e,
+0x2c,
+0x9f,
+0x87,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x6f,
+0x95,
+0x03,
+0x50,
+0xf4,
+0x03,
+0xf8,
+0x1c,
+0xf8,
+0xff,
+0x3f,
+0x00,
+0xf0,
+0xee,
+0x84,
+0xfc,
+0xfe,
+0xff,
+0xff,
+0x22,
+0xc3,
+0x1f,
+0x51,
+0x96,
+0x38,
+0x16,
+0x0d,
+0x00,
+0xf8,
+0xfe,
+0xfe,
+0x01,
+0x0e,
+0xfc,
+0xb1,
+0x01,
+0xe5,
+0xa6,
+0xff,
+0x1f,
+0x79,
+0xf8,
+0x07,
+0xf8,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfa,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x3f,
+0xe3,
+0x3e,
+0x0f,
+0xfd,
+0x50,
+0x03,
+0xb0,
+0xdf,
+0x8c,
+0xf9,
+0x3c,
+0xf4,
+0x43,
+0x0e,
+0xc0,
+0xfd,
+0x32,
+0xe5,
+0xf3,
+0xd0,
+0x0f,
+0x03,
+0x00,
+0x03,
+0x25,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0xff,
+0xff,
+0x00,
+0xfd,
+0xbb,
+0x14,
+0xf2,
+0xc3,
+0x2f,
+0xf8,
+0x13,
+0xcc,
+0x7f,
+0x0c,
+0xb8,
+0x0e,
+0x74,
+0xf5,
+0x03,
+0xf0,
+0xf8,
+0x33,
+0x03,
+0x1c,
+0x2b,
+0xd7,
+0x00,
+0x00,
+0xeb,
+0xe5,
+0x1f,
+0x80,
+0xc0,
+0x1f,
+0x1b,
+0xe0,
+0x9e,
+0x9b,
+0x7f,
+0x00,
+0x03,
+0x7f,
+0x6c,
+0x80,
+0xf8,
+0x7d,
+0xfe,
+0x01,
+0x0e,
+0xfc,
+0xb1,
+0x01,
+0x80,
+0xd7,
+0x62,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x38,
+0x00,
+0x43,
+0xdf,
+0xa0,
+0xd7,
+0x83,
+0x3f,
+0xe3,
+0x00,
+0x3c,
+0x75,
+0x80,
+0x5e,
+0x07,
+0xfe,
+0xff,
+0xef,
+0x7a,
+0xc1,
+0x73,
+0xfd,
+0x3c,
+0xfc,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xff,
+0xff,
+0x17,
+0xff,
+0xdf,
+0xeb,
+0xff,
+0xe1,
+0xb7,
+0xf5,
+0x00,
+0xfe,
+0x7f,
+0x6e,
+0x80,
+0x07,
+0xff,
+0xff,
+0x6f,
+0x11,
+0xfe,
+0xb5,
+0xaa,
+0x1f,
+0xff,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xff,
+0x7f,
+0x8b,
+0xf0,
+0xaf,
+0x75,
+0xff,
+0xff,
+0xdb,
+0x7f,
+0x2f,
+0xc3,
+0xbf,
+0x57,
+0xf5,
+0x0c,
+0xf1,
+0xff,
+0xb7,
+0x0f,
+0xff,
+0x00,
+0x3f,
+0x70,
+0xa2,
+0x35,
+0x00,
+0xe0,
+0xff,
+0x1b,
+0x0f,
+0x79,
+0xe8,
+0xd7,
+0xf2,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x2f,
+0x3a,
+0xc1,
+0xff,
+0xfd,
+0x3c,
+0xfc,
+0x6b,
+0x1e,
+0xc0,
+0x7f,
+0xb6,
+0x0c,
+0xf0,
+0xe0,
+0x4f,
+0xff,
+0x2f,
+0x43,
+0xfc,
+0xc0,
+0xcf,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xff,
+0x67,
+0x81,
+0xff,
+0xb1,
+0xee,
+0x1f,
+0xfe,
+0x1b,
+0x0f,
+0xe0,
+0xff,
+0xf7,
+0xf6,
+0x7a,
+0xf0,
+0xef,
+0xbf,
+0x96,
+0xff,
+0x1d,
+0xab,
+0xfe,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x6f,
+0xff,
+0xb1,
+0xfc,
+0x7f,
+0x58,
+0x59,
+0x0e,
+0xc0,
+0xff,
+0x2f,
+0x72,
+0xfc,
+0x03,
+0xfc,
+0x3c,
+0x7f,
+0x31,
+0x1e,
+0xc0,
+0xe0,
+0x4f,
+0xec,
+0x75,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xd7,
+0xf8,
+0xff,
+0x45,
+0x87,
+0x7f,
+0xa2,
+0x9f,
+0x19,
+0xff,
+0xff,
+0x67,
+0x1f,
+0xfe,
+0xb1,
+0xae,
+0x65,
+0xfc,
+0xff,
+0xff,
+0x7e,
+0xf8,
+0xf7,
+0xba,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0xdb,
+0x7a,
+0xc0,
+0x83,
+0x3f,
+0x31,
+0x01,
+0xfc,
+0x67,
+0xff,
+0xf4,
+0x0f,
+0xdf,
+0x5a,
+0x4f,
+0xf0,
+0xff,
+0xff,
+0xd8,
+0x3a,
+0xfc,
+0x32,
+0x00,
+0xc0,
+0x01,
+0x48,
+0x7f,
+0x97,
+0xf1,
+0xff,
+0xe0,
+0xac,
+0xe1,
+0x1f,
+0xff,
+0x5a,
+0xfe,
+0xbb,
+0xad,
+0xff,
+0x87,
+0x7f,
+0xfe,
+0x03,
+0xf8,
+0xff,
+0xb5,
+0xe8,
+0x1f,
+0xbe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x5f,
+0xcb,
+0x7f,
+0xab,
+0x75,
+0xe5,
+0xf0,
+0xdb,
+0x7a,
+0x00,
+0xff,
+0x3f,
+0x91,
+0xcf,
+0x43,
+0x0f,
+0xf8,
+0x13,
+0x90,
+0xbf,
+0x0c,
+0xb6,
+0x0e,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x7f,
+0x5b,
+0x0f,
+0xe0,
+0xf0,
+0x27,
+0x06,
+0x78,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x5b,
+0x8b,
+0xfe,
+0xca,
+0x07,
+0xfc,
+0x09,
+0x87,
+0x5f,
+0x06,
+0x5b,
+0x20,
+0x00,
+0x09,
+0x00,
+0xb0,
+0xc0,
+0x8d,
+0x03,
+0x3c,
+0xf8,
+0x03,
+0x02,
+0x80,
+0xf8,
+0xff,
+0x3f,
+0xfc,
+0xf0,
+0xce,
+0x85,
+0x04,
+0x3a,
+0x0e,
+0xfe,
+0xae,
+0xc3,
+0x1f,
+0x03,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x77,
+0x01,
+0x00,
+0xf8,
+0xee,
+0x1f,
+0xfe,
+0xb9,
+0x3f,
+0x65,
+0x40,
+0xe0,
+0xf8,
+0x79,
+0xf8,
+0x07,
+0xff,
+0x94,
+0xf3,
+0xff,
+0xea,
+0xfa,
+0xe0,
+0x5f,
+0x06,
+0x00,
+0x7a,
+0xbc,
+0xff,
+0xa5,
+0xfe,
+0x77,
+0x52,
+0x3f,
+0x0f,
+0xff,
+0xff,
+0xef,
+0xf2,
+0xfe,
+0x03,
+0xfc,
+0x3c,
+0xfc,
+0x77,
+0x1f,
+0xe0,
+0x7f,
+0x2f,
+0xe5,
+0xf3,
+0xd0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
new file mode 100755
index 0000000000..ce01eabdc9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
@@ -0,0 +1,1035 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c5 for 1080 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVD
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c5 for 1080 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5 =
+{{
+0x10,
+0x20,
+0x05,
+0x03,
+0xc5,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0x83,
+0xc5,
+0x93,
+0xcd,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x80,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x89,
+0x0b,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0x51,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xf8,
+0xff,
+0x2e,
+0xc3,
+0x3f,
+0xd7,
+0xfd,
+0xac,
+0xff,
+0xff,
+0xbb,
+0x0f,
+0xff,
+0x5c,
+0xd7,
+0xf3,
+0xdf,
+0xfd,
+0xc7,
+0x3f,
+0xfc,
+0xe3,
+0xf5,
+0x00,
+0x1d,
+0xd5,
+0x00,
+0x00,
+0xfd,
+0xff,
+0x7f,
+0xfa,
+0xe1,
+0xd9,
+0xca,
+0x00,
+0x66,
+0xfa,
+0x71,
+0x80,
+0x07,
+0x7f,
+0x40,
+0x67,
+0xd9,
+0xff,
+0xff,
+0xde,
+0x1d,
+0x7e,
+0xb1,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x0e,
+0x40,
+0xbd,
+0x55,
+0xe0,
+0x73,
+0xd0,
+0x0f,
+0xff,
+0x00,
+0xe0,
+0xff,
+0x13,
+0xf2,
+0xc3,
+0xbb,
+0xff,
+0x8b,
+0xf8,
+0xff,
+0x44,
+0x59,
+0x0e,
+0x7f,
+0x34,
+0x00,
+0x10,
+0x59,
+0xfb,
+0x07,
+0xe0,
+0xfb,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0xfe,
+0x7f,
+0x94,
+0x9b,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xe8,
+0xff,
+0x8c,
+0x07,
+0xf0,
+0xf4,
+0x43,
+0xf9,
+0x3c,
+0x7e,
+0x33,
+0x0e,
+0xc0,
+0xd0,
+0x0f,
+0xe5,
+0xf3,
+0xf7,
+0xcb,
+0x38,
+0x00,
+0x43,
+0x3f,
+0x94,
+0xcf,
+0x0c,
+0x94,
+0x0c,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x03,
+0xf4,
+0xff,
+0xff,
+0xc8,
+0x0f,
+0xef,
+0x52,
+0x4f,
+0x30,
+0xbf,
+0xe0,
+0xe0,
+0x3a,
+0xfc,
+0x31,
+0x0f,
+0xc0,
+0xd3,
+0xd5,
+0x0c,
+0x70,
+0xe0,
+0xcf,
+0x03,
+0x00,
+0xac,
+0x5c,
+0x7f,
+0x00,
+0xae,
+0x97,
+0x6c,
+0x80,
+0x03,
+0x7f,
+0xfe,
+0x01,
+0x78,
+0x6e,
+0xb1,
+0x01,
+0x0e,
+0xfc,
+0xf9,
+0x07,
+0xe0,
+0xf7,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0x8b,
+0x01,
+0x80,
+0x5f,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x40,
+0xf9,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0x80,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
new file mode 100755
index 0000000000..ddd937ab66
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
@@ -0,0 +1,113 @@
+;/**
+; * @file
+; *
+; * AGESA Family 10h Revision D support routines.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU/F10
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    .LIST
+
+    .586P
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   P R E S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .MODEL flat
+    .CODE
+
+;======================================================================
+; F10RevDProbeFilterCritical:  Performs critical sequence for probe
+;                              filter initialization.
+;
+;   In:
+;       PciAddress      Full PCI address of the node to init
+;       PciRegister     Current value of F3x1D4
+;
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
+
+  mov    ecx, 0C001001Fh
+  rdmsr
+  push   eax
+  push   ecx
+  push   edx
+  or     dh, 40h
+  wrmsr
+
+  mov    eax, 810003D4h
+
+  mov    ecx, PciRegister
+  mov    edx, PciAddress
+  shr    edx, 4
+  and    dh, 0F8h
+  or     ah, dh
+
+  or     cl, 2
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  mov    dx, 0CF8h        ; Set Reg Config Space
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  out    dx, eax
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  mov    dl, 0FCh         ; Set DX to Pci Config Data
+  mov    eax, ecx         ;Set config Reg data
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  out    dx, eax          ; move data to return position
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  pop    edx
+  pop    ecx
+  pop    eax
+  wrmsr
+  ret
+
+F10RevDProbeFilterCritical ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
new file mode 100755
index 0000000000..2804d29153
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
@@ -0,0 +1,127 @@
+;/**
+; * @file
+; *
+; * AGESA Family 10h Revision D support routines.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU/F10
+; * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+; 
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+;       its contributors may be used to endorse or promote products derived 
+;       from this software without specific prior written permission.
+; 
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; 
+;*****************************************************************************
+
+    .XLIST
+    .LIST
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   P R E S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .CODE
+
+;======================================================================
+; F10RevDProbeFilterCritical:  Performs critical sequence for probe
+;                              filter initialization.
+;
+;   In:
+;       PciAddress      Full PCI address of the node to init
+;       PciRegister     Current value of F3x1D4
+;
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC F10RevDProbeFilterCritical
+F10RevDProbeFilterCritical PROC
+
+  push   rax
+  push   rcx
+  push   rdx
+  push   rsi
+  push   rdi
+
+  mov    esi, ecx
+  mov    edi, edx
+
+  mov    ecx, 0C001001Fh
+  rdmsr
+  push   rax
+  push   rcx
+  push   rdx
+  or     dh, 40h
+  wrmsr
+
+  mov    eax, 810003D4h
+
+  mov    ecx, edi
+  mov    edx, esi
+
+  shr    edx, 4
+  and    dh, 0F8h
+  or     ah, dh
+
+  or     cl, 2
+  mfence
+
+  mov    dx, 0CF8h        ; Set Reg Config Space
+  mfence
+
+  out    dx, eax
+  mfence
+
+  mov    dl, 0FCh         ; Set DX to Pci Config Data
+  mov    eax, ecx         ;Set config Reg data
+  mfence
+
+  out    dx, eax          ; move data to return position
+  mfence
+
+  pop    rdx
+  pop    rcx
+  pop    rax
+  wrmsr
+
+  pop    rdi
+  pop    rsi
+  pop    rdx
+  pop    rcx
+  pop    rax
+  ret
+
+F10RevDProbeFilterCritical ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
new file mode 100755
index 0000000000..538ebdaa29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
@@ -0,0 +1,454 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RevD HT Assist feature support functions.
+ *
+ * Provides the functions necessary to initialize the HT Assist feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "CommonReturns.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuLateInit.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuHtAssist.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * The family 10h background scrubber context structure.
+ *
+ * These fields need to be saved, modified, then restored
+ * per die as part of HT Assist initialization.
+ */
+typedef struct {
+  UINT32  DramScrub:5;               ///< DRAM scrub rate
+  UINT32  :3;                        ///< Reserved
+  UINT32  L3Scrub:5;                 ///< L3 scrub rate
+  UINT32  :3;                        ///< Reserved
+  UINT32  Redirect:1;                ///< DRAM scrubber redirect enable
+  UINT32  :15;                       ///< Reserved
+} F10_SCRUB_CONTEXT;
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU supports HT Assist.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsHtAssistSupported (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       PciRegister;
+  BOOLEAN      IsSupported;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  IsSupported = FALSE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NB_CAPS_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if (((NB_CAPS_REGISTER *) &PciRegister)->L3Capable == 1) {
+        IsSupported = TRUE;
+      }
+      break;
+    }
+  }
+  return IsSupported;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the Probe filter feature.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HtAssistInit (
+  IN       HT_ASSIST_FAMILY_SERVICES  *HtAssistServices,
+  IN       UINT32  Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                     Module;
+  UINT32                     PciRegister;
+  PCI_ADDR                   PciAddress;
+  AGESA_STATUS               IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = L3_CACHE_PARAM_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      } while (((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit != 0);
+
+      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFMode = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+      F10RevDProbeFilterCritical (PciAddress, PciRegister);
+
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      } while (((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFInitDone != 1);
+      IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Save the current settings of the scrubbers, and disabled them.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10GetL3ScrubCtrl (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       ScrubCtrl;
+  UINT32       ScrubAddr;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+
+      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
+
+      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
+
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
+        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
+        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
+        ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
+
+      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
+      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
+      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Restore the initial settings for the scrubbers.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10SetL3ScrubCtrl (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+
+      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((SCRUB_RATE_CTRL_REGISTER *) &PciRegister)->DramScrub =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
+      ((SCRUB_RATE_CTRL_REGISTER *) &PciRegister)->L3Scrub =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &PciRegister)->ScrubReDirEn =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set MSR bits required for HT Assist on each core.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HookDisableCache (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  MsrRegister;
+
+  LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader);
+  MsrRegister |= BIT42;
+  LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Hook before the probe filter initialization sequence.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HookBeforeInit (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32          Module;
+  UINT32          PciRegister;
+  UINT32          PfCtrlRegister;
+  PCI_ADDR        PciAddress;
+  CPU_LOGICAL_ID  LogicalId;
+  AGESA_STATUS    IgnoredStatus;
+  UINT32          PackageType;
+
+  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
+  PackageType = LibAmdGetPackageType (StdHeader);
+
+  PciRegister = 0;
+  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFWayNum = 2;
+  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFSubCacheEn = 15;
+  ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFLoIndexHashEn = 1;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
+      ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFPreferredSORepl =
+        ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+      // Assumption: all socket use the same CPU package.
+      if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
+        // Apply erratum #384
+        // Set F2x11C[13:12] = 11b
+        PciAddress.Address.Function = FUNC_2;
+        PciAddress.Address.Register = 0x11C;
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+        PciRegister |= 0x3000;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU is running in the optimal configuration.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is running sub-optimally.
+ * @retval       FALSE              HT Assist is running optimally.
+ *
+ */
+STATIC BOOLEAN
+F10IsNonOptimalConfig (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN      IsNonOptimal;
+  BOOLEAN      IsMemoryPresent;
+  UINT32       Module;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  IsNonOptimal = FALSE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      IsMemoryPresent = FALSE;
+      PciAddress.Address.Function = FUNC_2;
+      PciAddress.Address.Register = DRAM_CFG_HI_REG0;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
+        IsMemoryPresent = TRUE;
+        if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
+          IsNonOptimal = TRUE;
+          break;
+        }
+      }
+
+      PciAddress.Address.Register = DRAM_CFG_HI_REG1;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
+        IsMemoryPresent = TRUE;
+        if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
+          IsNonOptimal = TRUE;
+          break;
+        }
+      }
+      if (!IsMemoryPresent) {
+        IsNonOptimal = TRUE;
+        break;
+      }
+    }
+  }
+  return IsNonOptimal;
+}
+
+
+CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist =
+{
+  0,
+  F10IsHtAssistSupported,
+  F10HtAssistInit,
+  F10GetL3ScrubCtrl,
+  F10SetL3ScrubCtrl,
+  F10HookBeforeInit,
+  (PF_HT_ASSIST_AFTER_INIT) CommonVoid,
+  F10HookDisableCache,
+  (PF_HT_ASSIST_ENABLE_CACHE) CommonVoid,
+  F10IsNonOptimalConfig
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
new file mode 100755
index 0000000000..aa2c738ea1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -0,0 +1,277 @@
+/**
+ * @file
+ *
+ * AMD Family_10 RevD Message-Based C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the message-based C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 46667 $   @e \$Date: 2011-02-08 14:06:57 -0700 (Tue, 08 Feb 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuMsgBasedC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeMsgBasedC1eOnCore (
+  IN       VOID              *BmStsAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+STATIC
+IsDramScrubberEnabled (
+  IN       PCI_ADDR PciAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should message-based C1e be enabled
+ *
+ * @param[in]    MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsMsgBasedC1eSupported (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
+  return ((BOOLEAN) ((LogicalId.Revision & AMD_F10_GT_D0) != 0));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Core 0 task to enable message-based C1e on a family 10h CPU.
+ *
+ * @param[in]    MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
+ * @param[in]    EntryPoint          Timepoint designator.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeMsgBasedC1e (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       AndMask;
+  UINT32       Core;
+  UINT32       Module;
+  UINT32       OrMask;
+  UINT32       PciRegister;
+  UINT32       Socket;
+  AP_TASK      TaskPtr;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    // Note that this core 0 does NOT have the ability to launch
+    // any of its cores.  Attempting to do so could lead to a system
+    // hang.
+
+    // Set F3xA0[IdleExitEn] = 1
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    AndMask = 0xFFFFFFFF;
+    OrMask = 0;
+    ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
+
+    // BIOS should set F3x1B8[5]
+    PciAddress.Address.Register = 0x1B8;
+    OrMask = 0x00000020;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x1B8
+
+    // Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
+    PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
+    OrMask = 0;
+    ((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
+
+    // Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
+    // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
+    OrMask = 0;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
+
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+
+    for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
+        PciAddress.Address.Function = FUNC_3;
+        PciAddress.Address.Register = CPTC0_REG;
+        if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
+          ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
+        } else {
+          ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
+        }
+        LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+        PciRegister &= AndMask;
+        PciRegister |= OrMask;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      }
+    }
+
+  } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
+    // At early, this core 0 can launch its subordinate cores.
+    TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 1;
+    TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable message-based C1e on a family 10h core.
+ *
+ * @param[in]    BmStsAddress       System I/O address of the bus master status bit.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeMsgBasedC1eOnCore (
+  IN       VOID              *BmStsAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
+  LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader);
+  ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
+  ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1;
+  ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0;
+  ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0;
+  ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
+  LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader);
+
+  // Set MSRC001_0015[HltXSpCycEn] = 1
+  LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader);
+  MsrRegister |= BIT12;
+  LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the DRAM background scrubbers are enabled or not.
+ *
+ * @param[in]    PciAddress         Address of F10 socket/module to check.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Memory scrubbers are enabled on the current node.
+ * @retval       FALSE              Memory scrubbers are disabled on the current node.
+ */
+BOOLEAN
+STATIC
+IsDramScrubberEnabled (
+  IN       PCI_ADDR PciAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PciRegister;
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = 0x58;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  return ((BOOLEAN) ((PciRegister & 0x1F) != 0));
+}
+
+
+CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e =
+{
+  0,
+  F10IsMsgBasedC1eSupported,
+  F10InitializeMsgBasedC1e
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
new file mode 100755
index 0000000000..fe1b2d6ad5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -0,0 +1,372 @@
+/**
+ * @file
+ *
+ * AMD Family_10 revision Dx specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h rev D.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "GeneralServices.h"
+#include "cpuEarlyInit.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+F10CommonRevDGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+  OUT      BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+BOOLEAN
+F10CommonRevDGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+  OUT      UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+AGESA_STATUS
+F10CommonRevDGetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+  OUT      UINT32 *FrequencyInMHz,
+  OUT      UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+UINT8
+F10CommonRevDGetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on a revision D processor.
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ */
+STATIC VOID
+F10CommonRevDSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    TempVar32_a;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS AgesaStatus;
+
+  switch (*LeveledCores) {
+  case 1:
+    CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    break;
+  case 2:
+    CoreDisableBits = DOWNCORE_MASK_DUAL;
+    break;
+  case 3:
+    CoreDisableBits = DOWNCORE_MASK_TRI;
+    break;
+  case 4:
+    CoreDisableBits = DOWNCORE_MASK_FOUR;
+    break;
+  case 5:
+    CoreDisableBits = DOWNCORE_MASK_FIVE;
+    break;
+  default:
+    CoreDisableBits = 0;
+    break;
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
+      if (TempVar32_a == 0) {
+        CoreDisableBits &= 0x1;
+      } else if (TempVar32_a == 1) {
+        CoreDisableBits &= 0x3;
+      } else if (TempVar32_a == 2) {
+        CoreDisableBits &= 0x7;
+      } else if (TempVar32_a == 3) {
+        CoreDisableBits &= 0x0F;
+      } else if (TempVar32_a == 4) {
+        CoreDisableBits &= 0x1F;
+      } else if (TempVar32_a == 5) {
+        CoreDisableBits &= 0x3F;
+      }
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a |= CoreDisableBits;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+    }
+  }
+
+  return;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
+{
+  0,
+  F10CommonRevDSetDownCoreRegister
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current on a revision D processor.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F10CommonRevDGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       IddDiv;
+  UINT32       CmpCap;
+  UINT32       MultiNodeCpu;
+  UINT32       NbCaps;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Ignored;
+  UINT32       MsrAddress;
+  UINT64       PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
+  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // F3xE8
+
+    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
+    case 0:
+      IddDiv = 1000;
+      break;
+    case 1:
+      IddDiv = 100;
+      break;
+    case 2:
+      IddDiv = 10;
+      break;
+    default:  // IddDiv = 3 is reserved. Use 10
+      IddDiv = 10;
+      break;
+    }
+    MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->MultiNodeCpu + 1);
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapHi << 2);
+    CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapLo);
+    CmpCap++;
+    *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F10CommonRevDGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NbVidUpdateAll = FALSE;
+  return FALSE;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[out]  VoltageInuV              Northbridge voltage in uV.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS     Always succeeds.
+ */
+AGESA_STATUS
+F10CommonRevDGetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PciRegister;
+  UINT32 NbFid;
+  UINT64 MsrRegister;
+
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CPTC0_REG;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
+  NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
+  *FrequencyInMHz = ((NbFid + 4) * 200);
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get number of processor cores to be used in determining the brand string.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of cores to be used in brand string calculation.
+ */
+UINT8
+F10CommonRevDGetNumberOfCoresForBrandstring (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       CmpCap;
+  UINT32       CmpCapOnNode;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Core;
+  UINT32       PciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  CmpCap = 0;
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NB_CAPS_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      CmpCapOnNode = (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2);
+      CmpCapOnNode |= (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
+      CmpCapOnNode++;
+      CmpCap += CmpCapOnNode;
+    }
+  }
+  return ((UINT8) CmpCap);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
new file mode 100755
index 0000000000..6a2f04f5ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6381 $   @e \$Date: 2008-06-15 17:26:25 -0500 (Sun, 15 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10HyMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
+{
+  0x1080, 0x1080,
+  0x1081, 0x1081,
+  0x1091, 0x1081
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  HyEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10HyMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
new file mode 100755
index 0000000000..4b50153636
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
@@ -0,0 +1,1290 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Ht Phy tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyHtPhyRegisters[] =
+{
+// 0x60:0x68
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL0_ALL,               //
+      0x60, 0x68,                           // Address
+      0x00000040,                           // regData
+      0x00000040},                           // regMask
+    }
+  },
+// 0x70:0x78
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL1_ALL,               //
+      0x70, 0x78,                           // Address
+      0x00000040,                           // regData
+      0x00000040},                           // regMask
+    }
+  },
+// 0xC0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL0_ALL,               //
+      0xC0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000},                           // regMask
+    }
+  },
+// 0xD0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL1_ALL,               //
+      0xD0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000},                           // regMask
+    }
+  },
+// 0xCF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF},                           // regMask
+    }
+  },
+// 0xDF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {
+      {HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF},                           // regMask
+    }
+  },
+
+//
+// All the entries for XmtRdPtr 6
+//
+
+// 0xCF
+// For HT frequencies 1200-1600 and NB Freq 1600, 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1200-1600 and NB Freq 1600, 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3200 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3200 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Entries for XmtRdPtr 5
+//
+
+// 0xCF
+// For HT frequencies 1800-2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800-2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2000 - 2800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2000 - 2800 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Entries for XmtRdPtr 4
+//
+
+// 0xCF
+// For HT frequencies 2800-3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2800-3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3000 - 3200 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3000 - 3200 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Entries for XmtRdPtr 3
+//
+
+// 0xCF
+// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Rev D0 fixups for Erratum 398.
+//
+
+// 0xCF
+// For HT frequencies 1800, 2200 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800, 2200 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2600, 3000 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600, 3000 and NB Freq 1400
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000000A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2200, 2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2200, 2600 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3000 and NB Freq 1600
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2200, 2600 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2200, 2600 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 3000 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 3000 and NB Freq 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 1800 and NB Freq 1600 for all links
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 1800 and NB Freq 1600 for all links
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
+      0xDF,                                 // Address
+      0x0000003A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK1),
+      0xCF,                                 // Address
+      0x0000001A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL1_LINK5),
+      0xDF,                                 // Address
+      0x0000001A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// Deemphasis Settings for D1 processors.
+//
+
+// For D1, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10_HY,                      // CpuFamily
+      AMD_F10_D1                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+
+// 0x520A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,                   //
+      0x520A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+// 0x530A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,                   //
+      0x530A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10HyHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10HyHtPhyRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
new file mode 100755
index 0000000000..ec31f2bf84
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
@@ -0,0 +1,138 @@
+/**
+ * @file
+ *
+ * Implements the workaround for erratum 419.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/RevD/HY
+ * @e \$Revision$   @e \$Date$
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
+extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
+
+CONST PF_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
+{
+  McaInitializationAtEarly,
+  SetRegistersFromTablesAtEarly,
+  LocalApicInitializationAtEarly,
+  LoadMicrocodePatchAtEarly,
+  SetBrandIdRegistersAtEarly,
+  NULL
+};
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly to return the steps
+ * appropriate for the executing Rev D core.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetF10HyEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+VOID
+GetF10HyEarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST PF_PERFORM_EARLY_INIT_ON_CORE  **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  UINT32         ProcessorPackageType;
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+
+  // Check if this CPU is affected by erratum 419.
+  if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) {
+    // Return initialization steps such that the microcode patch is applied before
+    // brand string determination is performed.
+    *Table = F10HyC32D0EarlyInitOnCoreTable;
+  } else {
+    // No workaround is necessary.  Return the standard table.
+    GetCommonEarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
new file mode 100755
index 0000000000..4ff9ea5d0f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
@@ -0,0 +1,112 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 6261 $   @e \$Date: 2008-06-04 17:38:17 -0500 (Wed, 04 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10HyLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10HyLogicalIdAndRevArray[] =
+{
+  {
+    0x1080,
+    AMD_F10_HY_SCM_D0
+  },
+  {
+    0x1090,
+    AMD_F10_HY_MCM_D0
+  },
+  {
+    0x1081,
+    AMD_F10_HY_SCM_D1
+  },
+  {
+    0x1091,
+    AMD_F10_HY_MCM_D1
+  }
+};
+
+VOID
+GetF10HyLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10HyLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_HY;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
new file mode 100755
index 0000000000..9715ebc9e3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
@@ -0,0 +1,112 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+extern  CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[];
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10HyMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  OUT      CONST VOID **HyUcodePtr,
+  OUT      UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  HyUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10HyMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 NumberOfUcode;
+
+  for (NumberOfUcode = 0; CpuF10HyMicroCodePatchArray[NumberOfUcode] != 0; NumberOfUcode++) {
+  }
+  *NumberOfElements = NumberOfUcode;
+  *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
new file mode 100755
index 0000000000..2c441ca1f2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
@@ -0,0 +1,139 @@
+/**
+ * @file
+ *
+ * AMD Family_10 HY MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    { AMD_PF_ALL },                       // platformFeatures
+    {
+    {
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1)                              // NAND Mask
+    }
+    }
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// bit[21] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    { AMD_PF_ALL },                       // platformFeatures
+    {
+    {
+      MSR_BU_CFG,                           // MSR Address
+      (1 << 21),                            // OR Mask
+      (1 << 21),                            // NAND Mask
+    }
+    }
+  },
+
+// MSR_BU_CFG2 (0xC001102A)
+// bit[50] = 1
+// For GH rev C1 and later [RdMmExtCfgQwEn]=1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    { AMD_PF_ALL },                       // platformFeatures
+    {
+    {
+      MSR_BU_CFG2,                          // MSR Address
+      0x0004000000000000ull,                   // OR Mask
+      0x0004000000000000ull,                   // NAND Mask
+    }
+  }
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
new file mode 100755
index 0000000000..c8fc912cdc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
@@ -0,0 +1,362 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 46786 $   @e \$Date: 2011-02-09 18:32:59 -0700 (Wed, 09 Feb 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyPciRegisters[] =
+{
+// F0x68 -
+  // BufRelPri for rev D
+  // bits[14:13]  BufRelPri = 1
+  // bit [25] CHtExtAddrEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68),   // Address
+      0x02002000,                           // regData
+      0x02006000,                           // regMask
+    }}
+  },
+  // F0x[E4,A4,C4,84] Link Control Register
+  // bit [15] Addr64bitEn = 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},
+    {{
+      HT_HOST_FEAT_NONCOHERENT,
+      0x4,
+      0x00008000,
+      0x00008000,
+    }}
+  },
+// F0x150 - Link Global Retry Control Register
+// bit[18:16] TotalRetryAttempts = 7
+// bit[13] HtRetryCrcDatInsDynEn = 1
+// bit[12]HtRetryCrcCmdPackDynEn = 1
+// bit[11:9] HtRetryCrcDatIns = 0
+// bit[8] HtRetryCrcCmdPack = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
+      0x00073100,                           // regData
+      0x00073F00,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[5:0] T0Time = 0x26
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10_HY,                   // CpuFamily
+      AMD_F10_D1                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C026,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[9] RXCalEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10_HY,                   // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000200,                           // regData
+      0x00000200,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 01b (PHY_OFF)
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_Dx                            // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }}
+  },
+// F0x[18C:170] - Link Extended Control Register - All connected links.
+// bit[8] LS2En = 1
+  {
+    HtLinkPciRegister,
+    {
+      AMD_FAMILY_10_HY,                     // CpuFamily
+      AMD_F10_D1                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platform Features
+    {{
+      HT_HOST_FEATURES_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F2x1B0 - Extended Memory Controller Configuration Low
+// bits[10:8], CohPrefPrbLmt = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_Dx                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
+      0x00000000,                           // regData
+      0x00000700,                           // regMask
+    }}
+  },
+// Function 3 - Misc. Control
+// F3x158 - Link to XCS Token Count
+// bits[3:0] LnkToXcsDRToken = 3
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    {AMD_PF_UMA},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,                           // regData
+      0x0000000F,                           // regMask
+    }}
+  },
+
+// F3x80 - ACPI Power State Control
+// ACPI State C2
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 1
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 5
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_Ax                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000A681,                           // regData
+      0x0000FFFF,                           // regMask
+    }}
+  },
+
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_D0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000E600,                           // regData
+      0x0000FF00,                           // regMask
+    }}
+  },
+
+// F3xA0 - Power Control Miscellaneous
+// bit[14] BpPinsTriEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_D0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00004000,                           // regData
+      0x00004000,                           // regMask
+    }}
+  },
+
+// F3x188 - NB Extended Configuration Low Register
+// Must be set by BIOS
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x08000000,                           // regData
+      0x08000000,                           // regMask
+    }}
+  },
+
+// F3x1B8 - L3 Control
+// Must be set by BIOS
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_D0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
+      0x00040000,                           // regData
+      0x00040000,                           // regMask
+    }}
+  },
+
+// F3x1B8 - L3 Control
+// Must be set by BIOS
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
+      0x00800000,                           // regData
+      0x00800000,                           // regMask
+    }}
+  },
+
+// F3x1D4 - Probe Filter Control Register
+// bits[21:20] PFPreferedSORepl = 2
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1D4), // Address
+      0x00200000,                           // regData
+      0x00300000,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10HyPciRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
new file mode 100755
index 0000000000..0c21de5420
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
@@ -0,0 +1,343 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 5893 $   @e \$Date: 2008-04-23 08:37:29 -0700 (Wed, 23 Apr 2008) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCommonF10Utilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/**
+ * Node ID MSR register fields.
+ * Provide the layout of fields in the Node ID MSR.
+ */
+typedef struct {
+  UINT64    NodeId:3;                 ///< The core is on the node with this node id.
+  UINT64    NodesPerProcessor:3;      ///< The number of Nodes in this processor.
+  UINT64    HeapIndex:6;              ///< The AP core heap index.
+  UINT64    :(63 - 11);               ///< Reserved.
+} NODE_ID_MSR_FIELDS;
+
+/// Node ID MSR.
+typedef union {
+  NODE_ID_MSR_FIELDS   Fields;        ///< Access the register as individual fields
+  UINT64               Value;         ///< Access the register value.
+} NODE_ID_MSR;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+F10SetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32                 Socket,
+  IN       UINT32                 Module,
+  IN       UINT32                 ApCoreNumber,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+UINT32
+F10GetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+VOID
+F10TransferApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
+ *
+ *  This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Handle of Header for calling lib functions and services.
+ *  @param[in]  Request                  Indicate warm reset status
+ *
+ */
+VOID
+F10SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  PciData &= ~(HT_INIT_BIOS_RST_DET_0);
+  PciData = PciData | (Request->RequestBit << 5);
+
+  // bit[10,9] - indicate warm reset status and count
+  PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
+  PciData |= Request->StateBits << 9;
+
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get warm reset status and count
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
+ *
+ *  This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
+ *
+ *  @param[in]  FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]  StdHeader                Config handle for library and services
+ *  @param[in]  Request                  Indicate warm reset status
+ *
+ */
+VOID
+F10GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+
+  // bit[5] - indicate a warm reset is or is not required
+  Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
+  // bit[10,9] - indicate warm reset status and count
+  Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Use the Mailbox Register to get the Ap Mailbox info for the current core.
+ *
+ *  @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
+ *
+ *  Access the mailbox register used with this NB family.  This is valid until the
+ *  point that some init code initializes the mailbox register for its normal use.
+ *  The Machine Check Misc (Thresholding) register is available as both a PCI config
+ *  register and a MSR, so it can be used as a mailbox from HT to other functions.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[out]    ApMailboxInfo           The AP Mailbox info
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F10GetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64 MailboxInfo;
+
+  LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader);
+  // Mailbox info is in bits 32 thru 43, 12 bits.
+  ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
+  LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader);
+  // Mailbox info is in bits 32 thru 43, 12 bits.
+  ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set the system AP core number in the AP's Mailbox.
+ *
+ *  @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}.
+ *
+ *  Access the mailbox register used with this NB family.  This is only intended to
+ *  run on the BSC at the time of initial AP launch.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     Socket                  The AP's socket
+ *  @param[in]     Module                  The AP's module
+ *  @param[in]     ApCoreNumber            The AP's unique core number
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F10SetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32                 Socket,
+  IN       UINT32                 Module,
+  IN       UINT32                 ApCoreNumber,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   PciRegister;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = 0x170;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  ((AP_MAIL_EXT_INFO *) &PciRegister)->Fields.HeapIndex = ApCoreNumber;
+  LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get this AP's system core number from hardware.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
+ *
+ *  Returns the system core number from the scratch MSR, where
+ *  it was saved at heap initialization.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @return        The AP's unique core number
+ */
+UINT32
+F10GetApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  NODE_ID_MSR NodeIdMsr;
+
+  LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader);
+  return (UINT32) NodeIdMsr.Fields.HeapIndex;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Move the AP's core number from the mailbox to hardware.
+ *
+ *  @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}.
+ *
+ *  Transfers this AP's system core number from the mailbox to
+ *  the NodeId MSR and initializes the other NodeId fields.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+VOID
+F10TransferApCoreNumber (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_MAILBOXES Mailboxes;
+  NODE_ID_MSR NodeIdMsr;
+  UINT64 ExtFeatures;
+
+  NodeIdMsr.Value = 0;
+  FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader);
+  NodeIdMsr.Fields.HeapIndex = Mailboxes.ApMailExtInfo.Fields.HeapIndex;
+  NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node;
+  NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType;
+  LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader);
+
+  // Indicate that the NodeId MSR is supported.
+  LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
+  ExtFeatures = (ExtFeatures | BIT51);
+  LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Return a number zero or one, based on the Core ID position in the initial APIC Id.
+ *
+ * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
+ *
+ * @param[in]     FamilySpecificServices  The current Family Specific Services.
+ * @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ * @retval        CoreIdPositionZero      Core Id is not low
+ * @retval        CoreIdPositionOne       Core Id is low
+ */
+CORE_ID_POSITION
+F10CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT64 InitApicIdCpuIdLo;
+
+  //  Check bit_54 [InitApicIdCpuIdLo] to find core id position.
+  LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
+  InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
+  return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
new file mode 100755
index 0000000000..b135429ca9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
@@ -0,0 +1,98 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_COMMON_F10_UTILITES_H_
+#define _CPU_COMMON_F10_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10GetApMailboxFromHardware (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   AP_MAILBOXES           *ApMailboxInfo,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+CORE_ID_POSITION
+F10CpuAmdCoreIdPositionInInitialApicId (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+VOID
+F10SetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+VOID
+F10GetAgesaWarmResetFlag (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       WARM_RESET_REQUEST *Request
+  );
+
+#endif  // _CPU_COMMON_F10_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
new file mode 100755
index 0000000000..7dbdf14c4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandId.c
@@ -0,0 +1,155 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10BrandIdString1 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString1Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+VOID
+GetF10BrandIdString2 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString2Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+extern CPU_BRAND_TABLE *F10BrandIdString1Tables[];
+extern CPU_BRAND_TABLE *F10BrandIdString2Tables[];
+extern CONST UINT8 F10BrandIdString1TableCount;
+extern CONST UINT8 F10BrandIdString2TableCount;
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate beginnings of the CPU brandstring.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BrandString1Ptr          Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BrandIdString1 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString1Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_BRAND_TABLE **TableEntryPtr;
+
+  TableEntryPtr = &F10BrandIdString1Tables[0];
+  *BrandString1Ptr = TableEntryPtr;
+  *NumberOfElements = F10BrandIdString1TableCount;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate endings of the CPU brandstring.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BrandString2Ptr          Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BrandIdString2 (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BrandString2Ptr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_BRAND_TABLE **TableEntryPtr;
+
+  TableEntryPtr = &F10BrandIdString2Tables[0];
+  *BrandString2Ptr = TableEntryPtr;
+  *NumberOfElements = F10BrandIdString2TableCount;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
new file mode 100755
index 0000000000..73e9bb3263
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
@@ -0,0 +1,315 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket Am3.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+/*CHAR8 strEngSample[] = "AMD Engineering Sample";
+CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
+CHAR8 strUnknown[] = "AMD Processor model unknown";
+*/
+//AM3 NC 0
+CONST CHAR8 ROMDATA str_SC_AthlonLE[] =  "AMD Athlon(tm) Processor LE-";
+CONST CHAR8 ROMDATA str_SC_SempronLE[] = "AMD Sempron(tm) Processor LE-";
+CONST CHAR8 ROMDATA str_SC_Sempron_1[] = "AMD Sempron(tm) 1";
+CONST CHAR8 ROMDATA str_SC_Athlon_1[] = "AMD Athlon(tm) II 1";
+
+//AM3 NC 1
+CONST CHAR8 ROMDATA str_Athlon[] = "AMD Athlon(tm) ";
+CONST CHAR8 ROMDATA str_Athlon_II_XL_V[] = "AMD Athlon(tm) II XL V";
+CONST CHAR8 ROMDATA str_Athlon_II_XLT_V[] = "AMD Athlon(tm) II XLT V";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_4[] = "AMD Athlon(tm) II X2 4";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_B[] = "AMD Athlon(tm) II X2 B";
+CONST CHAR8 ROMDATA str_Athlon_II_X2[] = "AMD Athlon(tm) II X2 ";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_X2[] = "AMD Athlon(tm) II Neo X2 ";
+CONST CHAR8 ROMDATA str_Phenom_II_X2_5[] = "AMD Phenom(tm) II X2 5";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_5[] = "AMD Athlon(tm) II X2 5";
+CONST CHAR8 ROMDATA str_Athlon_II_X2_3[] = "AMD Athlon(tm) II X2 3";
+CONST CHAR8 ROMDATA str_Phenom_II_X2[] = "AMD Phenom(tm) II X2 ";
+CONST CHAR8 ROMDATA str_Phenom_II_X2_B[] = "AMD Phenom(tm) II X2 B";
+CONST CHAR8 ROMDATA str_DC_Opteron13[] = "Dual-Core AMD Opteron(tm) Processor 13";
+
+//AM3 NC2
+CONST CHAR8 ROMDATA str_Phenom[] = "AMD Phenom(tm) ";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_5[] = "AMD Phenom(tm) II X3 5";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_4[] = "AMD Phenom(tm) II X3 4";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_B[] = "AMD Phenom(tm) II X3 B";
+CONST CHAR8 ROMDATA str_Phenom_II_X3[] = "AMD Phenom(tm) II X3 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_X3[] = "AMD Athlon(tm) II Neo X3 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4";
+CONST CHAR8 ROMDATA str_Phenom_II_X3_7[] = "AMD Phenom(tm) II X3 7";
+CONST CHAR8 ROMDATA str_Athlon_II_X3_B[] = "AMD Athlon(tm) II X3 B";
+CONST CHAR8 ROMDATA str_Athlon_II_X3[] = "AMD Athlon(tm) II X3 ";
+
+//AM3 NC 3
+CONST CHAR8 ROMDATA str_Phenom_FX[] =  "AMD Phenom(tm) FX-";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_9[] = "AMD Phenom(tm) II X4 9";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_8[] = "AMD Phenom(tm) II X4 8";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_7[] = "AMD Phenom(tm) II X4 7";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_6[] = "AMD Phenom(tm) II X4 6";
+CONST CHAR8 ROMDATA str_Phenom_II_X4_B[] = "AMD Phenom(tm) II X4 B";
+CONST CHAR8 ROMDATA str_Phenom_II_X4[] = "AMD Phenom(tm) II X4 ";
+CONST CHAR8 ROMDATA str_Phenom_II_Neo_X4[] = "AMD Phenom(tm) II Neo X4 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6";
+CONST CHAR8 ROMDATA str_Athlon_II_X4_5[] = "AMD Athlon(tm) II X4 5";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_X4[] = "AMD Athlon(tm) II Neo X4 ";
+CONST CHAR8 ROMDATA str_Athlon_II_X4_B[] = "AMD Athlon(tm) II X4 B";
+CONST CHAR8 ROMDATA str_Phenom_II__FX[] = "AMD Phenom(tm) II FX-";
+CONST CHAR8 ROMDATA str_Athlon_II_X4[] = "AMD Athlon(tm) II X4 ";
+CONST CHAR8 ROMDATA str_Phenom_II[] = "AMD Phenom(tm) II ";
+CONST CHAR8 ROMDATA str_Phenom_II_XLT_Q[] = "AMD Phenom(tm) II XLT Q";
+CONST CHAR8 ROMDATA str_QC_Opteron13[] = "Quad-Core AMD Opteron(tm) Processor 13";
+
+// String2
+CONST CHAR8 ROMDATA str2_SE_AM3[] = " SE";
+CONST CHAR8 ROMDATA str2_HE_AM3[] = " HE";
+CONST CHAR8 ROMDATA str2_EE_AM3[] = " EE";
+
+CONST CHAR8 ROMDATA str2_QCP_AM3[] = " Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_00[] = "00";
+CONST CHAR8 ROMDATA str2_10[] = "10";
+CONST CHAR8 ROMDATA str2_20[] = "20";
+CONST CHAR8 ROMDATA str2_30[] = "30";
+CONST CHAR8 ROMDATA str2_40[] = "40";
+CONST CHAR8 ROMDATA str2_50[] = "50";
+CONST CHAR8 ROMDATA str2_60[] = "60";
+CONST CHAR8 ROMDATA str2_70[] = "70";
+CONST CHAR8 ROMDATA str2_80[] = "80";
+CONST CHAR8 ROMDATA str2_90[] = "90";
+CONST CHAR8 ROMDATA str2_DC_00[] = "00 Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_00e[] = "00e Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_00B[] = "00B Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_50[] = "50 Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_50e[] = "50e Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_DC_50B[] = "50B Dual-Core Processor";
+CONST CHAR8 ROMDATA str2_Processor[] = " Processor";
+CONST CHAR8 ROMDATA str2_e_Processor[] = "e Processor";
+CONST CHAR8 ROMDATA str2_B_Processor[] = "B Processor";
+CONST CHAR8 ROMDATA str2_0e_Processor[] = "0e Processor";
+CONST CHAR8 ROMDATA str2_u_Processor[] = "u Processor";
+CONST CHAR8 ROMDATA str2_0_Processor[] = "0 Processor";
+CONST CHAR8 ROMDATA str2_L_Processor[] = "L Processor";
+CONST CHAR8 ROMDATA str2_C_Processor[] = "C Processor";
+CONST CHAR8 ROMDATA str2_TWKR_Black_Edition[] = " TWKR Black Edition";
+
+CONST CHAR8 ROMDATA str2_TC_00[] = "00 Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_00e[] = "00e Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_00B[] = "00B Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_50[] = "50 Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_50e[] = "50e Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_TC_50B[] = "50B Triple-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_00[] = "00 Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_00e[] = "00e Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_00B[] = "00B Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_50[] = "50 Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_50e[] = "50e Quad-Core Processor";
+CONST CHAR8 ROMDATA str2_QC_50B[] = "50B Quad-Core Processor";
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAm3[] =
+{
+  // AM3
+  {1, 0, 0, DR_SOCKET_AM3, str_SC_AthlonLE, sizeof (str_SC_AthlonLE)},
+  {1, 0, 1, DR_SOCKET_AM3, str_SC_SempronLE, sizeof (str_SC_SempronLE)},
+  {1, 0, 2, DR_SOCKET_AM3, str_SC_Sempron_1, sizeof (str_SC_Sempron_1)},
+  {1, 0, 3, DR_SOCKET_AM3, str_SC_Athlon_1, sizeof (str_SC_Athlon_1)},
+  {2, 0, 0, DR_SOCKET_AM3, str_DC_Opteron13, sizeof (str_DC_Opteron13)},
+  {2, 0, 1, DR_SOCKET_AM3, str_Athlon, sizeof (str_Athlon)},
+  {2, 0, 2, DR_SOCKET_AM3, str_Athlon_II_X2_4, sizeof (str_Athlon_II_X2_4)},
+  {2, 0, 3, DR_SOCKET_AM3, str_Athlon_II_X2_2, sizeof (str_Athlon_II_X2_2)},
+  {2, 0, 4, DR_SOCKET_AM3, str_Athlon_II_X2_B, sizeof (str_Athlon_II_X2_B)},
+  {2, 0, 5, DR_SOCKET_AM3, str_Athlon_II_X2, sizeof (str_Athlon_II_X2)},
+  {2, 0, 6, DR_SOCKET_AM3, str_Athlon_II_Neo_X2, sizeof (str_Athlon_II_Neo_X2)},
+  {2, 0, 7, DR_SOCKET_AM3, str_Phenom_II_X2_5, sizeof (str_Phenom_II_X2_5)},
+  {2, 0, 8, DR_SOCKET_AM3, str_Athlon_II_X2_5, sizeof (str_Athlon_II_X2_5)},
+  {2, 0, 9, DR_SOCKET_AM3, str_Athlon_II_X2_3, sizeof (str_Athlon_II_X2_3)},
+  {2, 0, 10, DR_SOCKET_AM3, str_Phenom_II_X2, sizeof (str_Phenom_II_X2)},
+  {2, 0, 11, DR_SOCKET_AM3, str_Phenom_II_X2_B, sizeof (str_Phenom_II_X2_B)},
+
+  {3, 0, 0, DR_SOCKET_AM3, str_Phenom, sizeof (str_Phenom)},
+  {3, 0, 1, DR_SOCKET_AM3, str_Phenom_II_X3_5, sizeof (str_Phenom_II_X3_5)},
+  {3, 0, 2, DR_SOCKET_AM3, str_Phenom_II_X3_4, sizeof (str_Phenom_II_X3_4)},
+  {3, 0, 3, DR_SOCKET_AM3, str_Phenom_II_X3_B, sizeof (str_Phenom_II_X3_B)},
+  {3, 0, 4, DR_SOCKET_AM3, str_Phenom_II_X3, sizeof (str_Phenom_II_X3)},
+  {3, 0, 5, DR_SOCKET_AM3, str_Athlon_II_X3_3, sizeof (str_Athlon_II_X3_3)},
+  {3, 0, 6, DR_SOCKET_AM3, str_Athlon_II_Neo_X3, sizeof (str_Athlon_II_Neo_X3)},
+  {3, 0, 7, DR_SOCKET_AM3, str_Athlon_II_X3_4, sizeof (str_Athlon_II_X3_4)},
+  {3, 0, 8, DR_SOCKET_AM3, str_Phenom_II_X3_7, sizeof (str_Phenom_II_X3_7)},
+  {3, 0, 9, DR_SOCKET_AM3, str_Athlon_II_X3_B, sizeof (str_Athlon_II_X3_B)},
+  {3, 0, 10, DR_SOCKET_AM3, str_Athlon_II_X3, sizeof (str_Athlon_II_X3)},
+
+  {4, 0, 0, DR_SOCKET_AM3, str_QC_Opteron13, sizeof (str_QC_Opteron13)},
+  {4, 0, 1, DR_SOCKET_AM3, str_Phenom_FX, sizeof (str_Phenom_FX)},
+  {4, 0, 2, DR_SOCKET_AM3, str_Phenom, sizeof (str_Phenom)},
+  {4, 0, 3, DR_SOCKET_AM3, str_Phenom_II_X4_9, sizeof (str_Phenom_II_X4_9)},
+  {4, 0, 4, DR_SOCKET_AM3, str_Phenom_II_X4_8, sizeof (str_Phenom_II_X4_8)},
+  {4, 0, 5, DR_SOCKET_AM3, str_Phenom_II_X4_7, sizeof (str_Phenom_II_X4_7)},
+  {4, 0, 6, DR_SOCKET_AM3, str_Phenom_II_X4_6, sizeof (str_Phenom_II_X4_6)},
+  {4, 0, 7, DR_SOCKET_AM3, str_Phenom_II_X4_B, sizeof (str_Phenom_II_X4_B)},
+  {4, 0, 8, DR_SOCKET_AM3, str_Phenom_II_X4, sizeof (str_Phenom_II_X4)},
+  {4, 0, 9, DR_SOCKET_AM3, str_Phenom_II_Neo_X4, sizeof (str_Phenom_II_Neo_X4)},
+  {4, 0, 10, DR_SOCKET_AM3, str_Athlon_II_X4_6, sizeof (str_Athlon_II_X4_6)},
+  {4, 0, 11, DR_SOCKET_AM3, str_Athlon_II_X4_5, sizeof (str_Athlon_II_X4_5)},
+  {4, 0, 12, DR_SOCKET_AM3, str_Athlon_II_Neo_X4, sizeof (str_Athlon_II_Neo_X4)},
+  {4, 0, 13, DR_SOCKET_AM3, str_Athlon_II_X4_B, sizeof (str_Athlon_II_X4_B)},
+  {4, 0, 14, DR_SOCKET_AM3, str_Phenom_II__FX, sizeof (str_Phenom_II__FX)},
+  {4, 0, 15, DR_SOCKET_AM3, str_Athlon_II_X4, sizeof (str_Athlon_II_X4)},
+  {2, 1, 1, DR_SOCKET_AM3, str_Athlon_II_XLT_V, sizeof (str_Athlon_II_XLT_V)},
+  {2, 1, 2, DR_SOCKET_AM3, str_Athlon_II_XL_V, sizeof (str_Athlon_II_XL_V)},
+  {4, 1, 0, DR_SOCKET_AM3, str_Phenom_II, sizeof (str_Phenom_II)},
+  {4, 1, 1, DR_SOCKET_AM3, str_Phenom_II_XLT_Q, sizeof (str_Phenom_II_XLT_Q)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAm3[] =
+{
+  // AM3
+  {1, 0, 0x00, DR_SOCKET_AM3, str2_00, sizeof (str2_00)},
+  {1, 0, 0x01, DR_SOCKET_AM3, str2_10, sizeof (str2_10)},
+  {1, 0, 0x02, DR_SOCKET_AM3, str2_20, sizeof (str2_20)},
+  {1, 0, 0x03, DR_SOCKET_AM3, str2_30, sizeof (str2_30)},
+  {1, 0, 0x04, DR_SOCKET_AM3, str2_40, sizeof (str2_40)},
+  {1, 0, 0x05, DR_SOCKET_AM3, str2_50, sizeof (str2_50)},
+  {1, 0, 0x06, DR_SOCKET_AM3, str2_60, sizeof (str2_60)},
+  {1, 0, 0x07, DR_SOCKET_AM3, str2_70, sizeof (str2_70)},
+  {1, 0, 0x08, DR_SOCKET_AM3, str2_80, sizeof (str2_80)},
+  {1, 0, 0x09, DR_SOCKET_AM3, str2_90, sizeof (str2_90)},
+  {1, 0, 0x0A, DR_SOCKET_AM3, str2_Processor, sizeof (str2_Processor)},
+  {1, 0, 0x0B, DR_SOCKET_AM3, str2_u_Processor, sizeof (str2_u_Processor)},
+  {1, 0, 0x0F, DR_SOCKET_AM3, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x00, DR_SOCKET_AM3, str2_DC_00, sizeof (str2_DC_00)},
+  {2, 0, 0x01, DR_SOCKET_AM3, str2_DC_00e,sizeof (str2_DC_00e)},
+  {2, 0, 0x02, DR_SOCKET_AM3, str2_DC_00B,sizeof (str2_DC_00B)},
+  {2, 0, 0x03, DR_SOCKET_AM3, str2_DC_50, sizeof (str2_DC_50)},
+  {2, 0, 0x04, DR_SOCKET_AM3, str2_DC_50e,sizeof (str2_DC_50e)},
+  {2, 0, 0x05, DR_SOCKET_AM3, str2_DC_50B,sizeof (str2_DC_50B)},
+  {2, 0, 0x06, DR_SOCKET_AM3, str2_Processor,sizeof (str2_Processor)},
+  {2, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor,sizeof (str2_e_Processor)},
+  {2, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor,sizeof (str2_B_Processor)},
+  {2, 0, 0x09, DR_SOCKET_AM3, str2_0_Processor,sizeof (str2_0_Processor)},
+  {2, 0, 0x0A, DR_SOCKET_AM3, str2_0e_Processor,sizeof (str2_0e_Processor)},
+  {2, 0, 0x0B, DR_SOCKET_AM3, str2_u_Processor,sizeof (str2_u_Processor)},
+  {2, 0, 0x0F, DR_SOCKET_AM3, 0, 0},    // Size 0 for no suffix
+  {3, 0, 0x00, DR_SOCKET_AM3, str2_TC_00, sizeof (str2_TC_00)},
+  {3, 0, 0x01, DR_SOCKET_AM3, str2_TC_00e,sizeof (str2_TC_00e)},
+  {3, 0, 0x02, DR_SOCKET_AM3, str2_TC_00B,sizeof (str2_TC_00B)},
+  {3, 0, 0x03, DR_SOCKET_AM3, str2_TC_50, sizeof (str2_TC_50)},
+  {3, 0, 0x04, DR_SOCKET_AM3, str2_TC_50e,sizeof (str2_TC_50e)},
+  {3, 0, 0x05, DR_SOCKET_AM3, str2_TC_50B,sizeof (str2_TC_50B)},
+  {3, 0, 0x06, DR_SOCKET_AM3, str2_Processor,sizeof (str2_Processor)},
+  {3, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor,sizeof (str2_e_Processor)},
+  {3, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor,sizeof (str2_B_Processor)},
+  {3, 0, 0x09, DR_SOCKET_AM3, str2_0e_Processor,sizeof (str2_0e_Processor)},
+  {3, 0, 0x0A, DR_SOCKET_AM3, str2_0_Processor,sizeof (str2_0_Processor)},
+  {3, 0, 0x0F, DR_SOCKET_AM3, 0, 0},    //Size 0 for no suffix
+  {4, 0, 0x00, DR_SOCKET_AM3, str2_QC_00, sizeof (str2_QC_00)},
+  {4, 0, 0x01, DR_SOCKET_AM3, str2_QC_00e,sizeof (str2_QC_00e)},
+  {4, 0, 0x02, DR_SOCKET_AM3, str2_QC_00B,sizeof (str2_QC_00B)},
+  {4, 0, 0x03, DR_SOCKET_AM3, str2_QC_50, sizeof (str2_QC_50)},
+  {4, 0, 0x04, DR_SOCKET_AM3, str2_QC_50e,sizeof (str2_QC_50e)},
+  {4, 0, 0x05, DR_SOCKET_AM3, str2_QC_50B,sizeof (str2_QC_50B)},
+  {4, 0, 0x06, DR_SOCKET_AM3, str2_Processor, sizeof (str2_Processor)},
+  {4, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor, sizeof (str2_e_Processor)},
+  {4, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor, sizeof (str2_B_Processor)},
+  {4, 0, 0x09, DR_SOCKET_AM3, str2_0e_Processor, sizeof (str2_0e_Processor)},
+  {4, 0, 0x0A, DR_SOCKET_AM3, str2_SE_AM3, sizeof (str2_SE_AM3)},
+  {4, 0, 0x0B, DR_SOCKET_AM3, str2_HE_AM3, sizeof (str2_HE_AM3)},
+  {4, 0, 0x0C, DR_SOCKET_AM3, str2_EE_AM3, sizeof (str2_EE_AM3)},
+  {4, 0, 0x0D, DR_SOCKET_AM3, str2_QCP_AM3, sizeof (str2_QCP_AM3)},
+  {4, 0, 0x0E, DR_SOCKET_AM3, str2_0_Processor, sizeof (str2_0_Processor)},
+  {2, 1, 0x01, DR_SOCKET_AM3, str2_L_Processor, sizeof (str2_L_Processor)},
+  {2, 1, 0x02, DR_SOCKET_AM3, str2_C_Processor, sizeof (str2_C_Processor)},
+  {4, 1, 0x00, DR_SOCKET_AM3, str2_TWKR_Black_Edition, sizeof (str2_TWKR_Black_Edition)},
+  {4, 1, 0x01, DR_SOCKET_AM3, str2_L_Processor, sizeof (str2_L_Processor)},
+  {4, 0, 0x0F, DR_SOCKET_AM3, 0, 0}
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3 = {
+  (sizeof (CpuF10BrandIdString1ArrayAm3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayAm3
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
+  (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayAm3
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
new file mode 100755
index 0000000000..1db5664235
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for package ASB2.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "F10PackageType.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+// String1
+CONST CHAR8 ROMDATA str_AMD_V[] = "AMD V";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_K[] = "AMD Athlon(tm) II Neo K";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_N[] = "AMD Athlon(tm) II Neo N";
+CONST CHAR8 ROMDATA str_Athlon_II_Neo_R[] = "AMD Athlon(tm) II Neo R";
+CONST CHAR8 ROMDATA str_Turion_II_Neo_K[] = "AMD Turion(tm) II Neo K";
+CONST CHAR8 ROMDATA str_Turion_II_Neo_N[] = "AMD Turion(tm) II Neo N";
+
+// String2
+CONST CHAR8 ROMDATA str_Asb2_5_Processor[] = "5 Processor";
+CONST CHAR8 ROMDATA str_Asb2_5_Dual_Core_Processor[] = "5 Dual-Core Processor";
+CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
+CONST CHAR8 ROMDATA str_L_Dual_Core_Processor[] = "L Dual-Core Processor";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAsb2[] =
+{
+  // ASB2
+  {1, 0, 1, DR_SOCKET_ASB2, str_Athlon_II_Neo_K, sizeof (str_Athlon_II_Neo_K)},
+  {1, 0, 2, DR_SOCKET_ASB2, str_AMD_V, sizeof (str_AMD_V)},
+  {1, 0, 3, DR_SOCKET_ASB2, str_Athlon_II_Neo_R, sizeof (str_Athlon_II_Neo_R)},
+  {2, 0, 1, DR_SOCKET_ASB2, str_Turion_II_Neo_K, sizeof (str_Turion_II_Neo_K)},
+  {2, 0, 2, DR_SOCKET_ASB2, str_Athlon_II_Neo_K, sizeof (str_Athlon_II_Neo_K)},
+  {2, 0, 3, DR_SOCKET_ASB2, str_AMD_V, sizeof (str_AMD_V)},
+  {2, 0, 4, DR_SOCKET_ASB2, str_Turion_II_Neo_N, sizeof (str_Turion_II_Neo_N)},
+  {2, 0, 5, DR_SOCKET_ASB2, str_Athlon_II_Neo_N, sizeof (str_Athlon_II_Neo_N)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAsb2[] =
+{
+  // ASB2
+  {1, 0, 0x01, DR_SOCKET_ASB2, str_Asb2_5_Processor, sizeof (str_Asb2_5_Processor)},
+  {1, 0, 0x02, DR_SOCKET_ASB2, str_L_Processor, sizeof (str_L_Processor)},
+  {2, 0, 0x01, DR_SOCKET_ASB2, str_Asb2_5_Dual_Core_Processor, sizeof (str_Asb2_5_Dual_Core_Processor)},
+  {2, 0, 0x02, DR_SOCKET_ASB2, str_L_Dual_Core_Processor, sizeof (str_L_Dual_Core_Processor)},
+  {1, 0, 0x0F, DR_SOCKET_ASB2, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x0F, DR_SOCKET_ASB2, 0, 0},    //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2 = {
+  (sizeof (CpuF10BrandIdString1ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayAsb2
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
+  (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayAsb2
+};
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
new file mode 100755
index 0000000000..6cd250e6c2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket C32.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+CONST CHAR8 ROMDATA str_Opteron_41[] = "AMD Opteron(tm) Processor 41";
+CONST CHAR8 ROMDATA str_Embedded_Opteron_C32[] = "Embedded AMD Opteron(tm) Processor ";
+
+// String2
+CONST CHAR8 ROMDATA str2_HE_C32[] = " HE";
+CONST CHAR8 ROMDATA str2_EE_C32[] = " EE";
+CONST CHAR8 ROMDATA str2_QS_HE_C32[] = "QS HE";
+CONST CHAR8 ROMDATA str2_LE_HE_C32[] = "LE HE";
+CONST CHAR8 ROMDATA str2_KX_HE_C32[] = "KX HE";
+CONST CHAR8 ROMDATA str2_GL_EE_C32[] = "GL EE";
+CONST CHAR8 ROMDATA str2_CL_EE[] = "CL EE";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayC32[] =
+{
+  // C32r1 string1:
+  {4, 0, 0x00, DR_SOCKET_C32, str_Opteron_41, sizeof (str_Opteron_41)},
+  {4, 1, 0x01, DR_SOCKET_C32, str_Embedded_Opteron_C32, sizeof (str_Embedded_Opteron_C32)},
+  {6, 0, 0x00, DR_SOCKET_C32, str_Opteron_41, sizeof (str_Opteron_41)},
+  {6, 1, 0x01, DR_SOCKET_C32, str_Embedded_Opteron_C32, sizeof (str_Embedded_Opteron_C32)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayC32[] =
+{
+  // C32r1 string2:
+  {4, 0, 0x00, DR_SOCKET_C32, str2_HE_C32, sizeof (str2_HE_C32)},
+  {4, 0, 0x01, DR_SOCKET_C32, str2_EE_C32, sizeof (str2_EE_C32)},
+  {4, 0, 0x0F, DR_SOCKET_C32, 0, 0},  //Size 0 for no suffix
+  {4, 1, 0x01, DR_SOCKET_C32, str2_QS_HE_C32, sizeof (str2_QS_HE_C32)},
+  {4, 1, 0x02, DR_SOCKET_C32, str2_LE_HE_C32, sizeof (str2_LE_HE_C32)},
+  {4, 1, 0x03, DR_SOCKET_C32, str2_CL_EE, sizeof (str2_CL_EE)},
+  {6, 0, 0x00, DR_SOCKET_C32, str2_HE_C32, sizeof (str2_HE_C32)},
+  {6, 0, 0x01, DR_SOCKET_C32, str2_EE_C32, sizeof (str2_EE_C32)},
+  {6, 0, 0x0F, DR_SOCKET_C32, 0, 0},  //Size 0 for no suffix
+  {6, 1, 0x01, DR_SOCKET_C32, str2_KX_HE_C32, sizeof (str2_KX_HE_C32)},
+  {6, 1, 0x02, DR_SOCKET_C32, str2_GL_EE_C32, sizeof (str2_GL_EE_C32)}
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32 = {
+  (sizeof (CpuF10BrandIdString1ArrayC32) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayC32
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
+  (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayC32
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
new file mode 100755
index 0000000000..a647bfd662
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
@@ -0,0 +1,176 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket Fr1207.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+/*CHAR8 strEngSample[] = "AMD Engineering Sample";
+CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
+CHAR8 strUnknown[] = "AMD Processor model unknown";
+*/
+CONST CHAR8 ROMDATA str_DC_Opteron83[] = "Dual-Core AMD Opteron(tm) Processor 83";
+CONST CHAR8 ROMDATA str_DC_Opteron23[] = "Dual-Core AMD Opteron(tm) Processor 23";
+CONST CHAR8 ROMDATA str_QC_Opteron83[] = "Quad-Core AMD Opteron(tm) Processor 83";
+CONST CHAR8 ROMDATA str_QC_Opteron23[] = "Quad-Core AMD Opteron(tm) Processor 23";
+CONST CHAR8 ROMDATA str_eQC_Opteron83[] = "Embedded AMD Opteron(tm) Processor 83";
+CONST CHAR8 ROMDATA str_eQC_Opteron23[] = "Embedded AMD Opteron(tm) Processor 23";
+CONST CHAR8 ROMDATA str_eQC_Opteron13[] = "Embedded AMD Opteron(tm) Processor 13";
+CONST CHAR8 ROMDATA str_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor ";
+CONST CHAR8 ROMDATA str_SC_Opteron84[] = "Six-Core AMD Opteron(tm) Processor 84";
+CONST CHAR8 ROMDATA str_SC_Opteron24[] = "Six-Core AMD Opteron(tm) Processor 24";
+
+CONST CHAR8 ROMDATA str_PhenomFX[] =  "AMD Phenom(tm) FX-";
+
+
+// String2
+CONST CHAR8 ROMDATA str2_SE[] = " SE";
+CONST CHAR8 ROMDATA str2_HE[] = " HE";
+CONST CHAR8 ROMDATA str2_EE[] = " EE";
+CONST CHAR8 ROMDATA str2_VS[] = "VS";
+CONST CHAR8 ROMDATA str2_QS[] = "QS";
+
+CONST CHAR8 ROMDATA str2_NP_HE[] = "NP HE";
+CONST CHAR8 ROMDATA str2_GF_HE[] = "GF HE";
+CONST CHAR8 ROMDATA str2_HF_HE[] = "HF HE";
+CONST CHAR8 ROMDATA str2_QS_HE[] = "QS HE";
+CONST CHAR8 ROMDATA str2_KH_HE[] = "KH HE";
+CONST CHAR8 ROMDATA str2_KS_EE[] = "KS EE";
+CONST CHAR8 ROMDATA str2_KS_HE[] = "KS HE";
+
+CONST CHAR8 ROMDATA str2_QCP[] = " Quad-Core Processor";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayFr1207[] =
+{
+  // FR2/FR4 1207
+  {2, 0, 0, DR_SOCKET_1207, str_DC_Opteron83, sizeof (str_DC_Opteron83)},
+  {2, 0, 1, DR_SOCKET_1207, str_DC_Opteron23, sizeof (str_DC_Opteron23)},
+  {3, 0, 0, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
+  {4, 0, 0, DR_SOCKET_1207, str_QC_Opteron83, sizeof (str_QC_Opteron83)},
+  {4, 0, 1, DR_SOCKET_1207, str_QC_Opteron23, sizeof (str_QC_Opteron23)},
+  {4, 0, 2, DR_SOCKET_1207, str_eQC_Opteron83, sizeof (str_eQC_Opteron83)},
+  {4, 0, 3, DR_SOCKET_1207, str_eQC_Opteron23, sizeof (str_eQC_Opteron23)},
+  {4, 0, 4, DR_SOCKET_1207, str_eQC_Opteron13, sizeof (str_eQC_Opteron13)},
+  {4, 0, 5, DR_SOCKET_1207, str_PhenomFX, sizeof (str_PhenomFX)},
+  {4, 1, 1, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
+  {6, 0, 0, DR_SOCKET_1207, str_SC_Opteron84, sizeof (str_SC_Opteron84)},
+  {6, 0, 1, DR_SOCKET_1207, str_SC_Opteron24, sizeof (str_SC_Opteron24)},
+  {6, 1, 1, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayFr1207[] =
+{
+  // FR2/FR4 1207
+  {2, 0, 0x0A, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
+  {2, 0, 0x0B, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
+  {2, 0, 0x0C, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
+  {2, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {3, 0, 0x00, DR_SOCKET_1207, str2_NP_HE, sizeof (str2_NP_HE)},
+  {3, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {4, 0, 0x0A, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
+  {4, 0, 0x0B, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
+  {4, 0, 0x0C, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
+  {4, 0, 0x0D, DR_SOCKET_1207, str2_QCP, sizeof (str2_QCP)},
+  {4, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {4, 1, 0x01, DR_SOCKET_1207, str2_GF_HE, sizeof (str2_GF_HE)},
+  {4, 1, 0x02, DR_SOCKET_1207, str2_HF_HE, sizeof (str2_HF_HE)},
+  {4, 1, 0x03, DR_SOCKET_1207, str2_VS, sizeof (str2_VS)},
+  {4, 1, 0x04, DR_SOCKET_1207, str2_QS_HE, sizeof (str2_QS_HE)},
+  {4, 1, 0x05, DR_SOCKET_1207, str2_NP_HE, sizeof (str2_NP_HE)},
+  {4, 1, 0x06, DR_SOCKET_1207, str2_KH_HE, sizeof (str2_KH_HE)},
+  {4, 1, 0x07, DR_SOCKET_1207, str2_KS_EE, sizeof (str2_KS_EE)},
+  {6, 0, 0x00, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
+  {6, 0, 0x01, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
+  {6, 0, 0x02, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
+  {6, 0, 0x0F, DR_SOCKET_1207, 0, 0},    //Size 0 for no suffix
+  {6, 1, 0x01, DR_SOCKET_1207, str2_QS, sizeof (str2_QS)},
+  {6, 1, 0x02, DR_SOCKET_1207, str2_KS_HE, sizeof (str2_KS_HE)},
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayFr1207 = {
+  (sizeof (CpuF10BrandIdString1ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayFr1207
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
+  (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayFr1207
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
new file mode 100755
index 0000000000..ed312a7461
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket G34.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+CONST CHAR8 ROMDATA str_Opteron_61[] = "AMD Opteron(tm) Processor 61";
+CONST CHAR8 ROMDATA str_Embedded_Opteron_G34[] = "Embedded AMD Opteron(tm) Processor ";
+
+// String2
+CONST CHAR8 ROMDATA str2_SE_G34[] = " SE";
+CONST CHAR8 ROMDATA str2_HE_G34[] = " HE";
+CONST CHAR8 ROMDATA str2_QS_G34[] = "QS";
+CONST CHAR8 ROMDATA str2_KS_G34[] = "KS";
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayG34[] =
+{
+  // G34r1 string1:
+  {8, 0, 0x00, DR_SOCKET_G34, str_Opteron_61, sizeof (str_Opteron_61)},
+  {8, 1, 0x01, DR_SOCKET_G34, str_Embedded_Opteron_G34, sizeof (str_Embedded_Opteron_G34)},
+  {12, 0, 0x00, DR_SOCKET_G34, str_Opteron_61, sizeof (str_Opteron_61)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayG34[] =
+{
+  // G34r1 string2:
+  {8, 0, 0x00, DR_SOCKET_G34, str2_HE_G34, sizeof (str2_HE_G34)},
+  {8, 0, 0x01, DR_SOCKET_G34, str2_SE_G34, sizeof (str2_SE_G34)},
+  {8, 1, 0x01, DR_SOCKET_G34, str2_QS_G34, sizeof (str2_QS_G34)},
+  {8, 1, 0x02, DR_SOCKET_G34, str2_KS_G34, sizeof (str2_KS_G34)},
+  {8, 0, 0x0F, DR_SOCKET_G34, 0, 0},  //Size 0 for no suffix
+  {12, 0, 0x00, DR_SOCKET_G34, str2_HE_G34, sizeof (str2_HE_G34)},
+  {12, 0, 0x01, DR_SOCKET_G34, str2_SE_G34, sizeof (str2_SE_G34)},
+  {12, 0, 0x0F, DR_SOCKET_G34, 0, 0}  //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34 = {
+  (sizeof (CpuF10BrandIdString1ArrayG34) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayG34
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
+  (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayG34
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
new file mode 100755
index 0000000000..c98d369f2d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for socket S1g3.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
+
+// String1
+/*CHAR8 strEngSample[] = "AMD Engineering Sample";
+CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
+CHAR8 strUnknown[] = "AMD Processor model unknown";
+*/
+// S1g3 NC 0
+CONST CHAR8 ROMDATA str_Sempron_M1[] = "AMD Sempron(tm) M1";
+
+// S1g3 NC 1
+CONST CHAR8 ROMDATA str_Turion_II_U_DC_M_M6[] = "AMD Turion(tm) II Ultra Dual-Core Mobile M6";
+CONST CHAR8 ROMDATA str_Turion_II_DC_M_M5[] = "AMD Turion(tm) II Dual-Core Mobile M5";
+CONST CHAR8 ROMDATA str_Athlon_II_DC_M3[] = "AMD Athlon(tm) II Dual-Core M3";
+
+// String2
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g3[] =
+{
+  // S1g3
+  {1, 0, 0, DR_SOCKET_S1G3, str_Sempron_M1, sizeof (str_Sempron_M1)},
+  {2, 0, 0, DR_SOCKET_S1G3, str_Turion_II_U_DC_M_M6, sizeof (str_Turion_II_U_DC_M_M6)},
+  {2, 0, 1, DR_SOCKET_S1G3, str_Turion_II_DC_M_M5, sizeof (str_Turion_II_DC_M_M5)},
+  {2, 0, 2, DR_SOCKET_S1G3, str_Athlon_II_DC_M3, sizeof (str_Athlon_II_DC_M3)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g3[] =
+{
+  // S1g3
+  {1, 0, 0x0F, DR_SOCKET_S1G3, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x0F, DR_SOCKET_S1G3, 0, 0}     //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3 = {
+  (sizeof (CpuF10BrandIdString1ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayS1g3
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
+  (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayS1g3
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
new file mode 100755
index 0000000000..343cda9a55
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
@@ -0,0 +1,138 @@
+/**
+ * @file
+ *
+ * AMD CPU BrandId related functions and structures for package S1g4.
+ *
+ * Contains code that provides CPU BrandId information
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6396 $   @e \$Date: 2008-06-16 05:52:20 -0700 (Mon, 16 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "F10PackageType.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+// String1
+CONST CHAR8 ROMDATA str_AMD_V_S1g4[] = "AMD V";
+CONST CHAR8 ROMDATA str_Turion_II_P[] = "AMD Turion(tm) II P";
+CONST CHAR8 ROMDATA str_Athlon_II_P[] = "AMD Athlon(tm) II P";
+CONST CHAR8 ROMDATA str_Phenom_II_X[] = "AMD Phenom(tm) II X";
+CONST CHAR8 ROMDATA str_Turion_II_N[] = "AMD Turion(tm) II N";
+CONST CHAR8 ROMDATA str_Athlon_II_N[] = "AMD Athlon(tm) II N";
+CONST CHAR8 ROMDATA str_Phenom_II_P[] = "AMD Phenom(tm) II P";
+CONST CHAR8 ROMDATA str_Phenom_II_N[] = "AMD Phenom(tm) II N";
+
+// String2
+CONST CHAR8 ROMDATA str_0_Processor[] = "0 Processor";
+CONST CHAR8 ROMDATA str_0_Dual_Core_Processor[] = "0 Dual-Core Processor";
+CONST CHAR8 ROMDATA str_0_Triple_Core_Processor[] = "0 Triple-Core Processor";
+CONST CHAR8 ROMDATA str_0_Quad_Core_Processor[] = "0 Quad-Core Processor";
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g4[] =
+{
+  // S1g4
+  {1, 0, 1, DR_SOCKET_S1G4, str_AMD_V_S1g4, sizeof (str_AMD_V_S1g4)},
+  {2, 0, 3, DR_SOCKET_S1G4, str_Turion_II_P, sizeof (str_Turion_II_P)},
+  {2, 0, 4, DR_SOCKET_S1G4, str_Athlon_II_P, sizeof (str_Athlon_II_P)},
+  {2, 0, 5, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
+  {2, 0, 6, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)},
+  {2, 0, 7, DR_SOCKET_S1G4, str_Turion_II_N, sizeof (str_Turion_II_N)},
+  {2, 0, 8, DR_SOCKET_S1G4, str_Athlon_II_N, sizeof (str_Athlon_II_N)},
+  {3, 0, 2, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
+  {3, 0, 3, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)},
+  {4, 0, 1, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
+  {4, 0, 2, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
+  {4, 0, 3, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)}
+};    //Cores, page, index, socket, stringstart, stringlength
+
+
+CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g4[] =
+{
+  // S1g4
+  {1, 0, 0x01, DR_SOCKET_S1G4, str_0_Processor, sizeof (str_0_Processor)},
+  {2, 0, 0x02, DR_SOCKET_S1G4, str_0_Dual_Core_Processor, sizeof (str_0_Dual_Core_Processor)},
+  {3, 0, 0x02, DR_SOCKET_S1G4, str_0_Triple_Core_Processor, sizeof (str_0_Triple_Core_Processor)},
+  {4, 0, 0x01, DR_SOCKET_S1G4, str_0_Quad_Core_Processor, sizeof (str_0_Quad_Core_Processor)},
+  {1, 0, 0x0F, DR_SOCKET_S1G4, 0, 0},    //Size 0 for no suffix
+  {2, 0, 0x0F, DR_SOCKET_S1G4, 0, 0},    //Size 0 for no suffix
+  {3, 0, 0x0F, DR_SOCKET_S1G4, 0, 0},    //Size 0 for no suffix
+  {4, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}     //Size 0 for no suffix
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4 = {
+  (sizeof (CpuF10BrandIdString1ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString1ArrayS1g4
+};
+
+
+CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
+  (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
+  CpuF10BrandIdString2ArrayS1g4
+};
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
new file mode 100755
index 0000000000..4f2296ce8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AMD Family_10 ROM Execution Cache Defaults
+ *
+ * Contains default values for ROM execution cache setup
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6163 $   @e \$Date: 2008-05-28 15:41:06 -0500 (Wed, 28 May 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#define BSP_STACK_SIZE            16384
+#define CORE0_STACK_SIZE          16384
+#define CORE1_STACK_SIZE          4096
+#define MEM_TRAINING_BUFFER_SIZE  16384
+#define VAR_MTRR_MASK             0x0000FFFFFFFFFFFFull
+
+#define SHARED_MEM_SIZE       0
+
+CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
+{
+  BSP_STACK_SIZE,
+  CORE0_STACK_SIZE,
+  CORE1_STACK_SIZE,
+  MEM_TRAINING_BUFFER_SIZE,
+  SHARED_MEM_SIZE,
+  VAR_MTRR_MASK
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific properties of the cache, and its usage.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  CacheInfoPtr             Points to the cache info properties on exit.
+ *  @param[out]  NumberOfElements         Will be one to indicate one entry.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10CacheInfo (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **CacheInfoPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *CacheInfoPtr = &CpuF10CacheInfo;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
new file mode 100755
index 0000000000..1c638c7a8a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in,out]   PciAddress               Pointer to Pci address struct.
+ *    @param[in,out]   AndMask                  Pointer to AND mask bits.
+ *    @param[in,out]   OrMask                   Pointer to Or mask bits.
+ *    @param[in]       StdHeader                Handle of Header for calling lib functions and services.
+ */
+STATIC VOID
+GetF10CacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN OUT   PCI_ADDR                     *PciAddress,
+  IN OUT   UINT32                       *AndMask,
+  IN OUT   UINT32                       *OrMask,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32     CoreCount;
+  CPU_LOGICAL_ID LogicalId;
+
+  //
+  // F3xDC[25:19] = 28h
+  // F3xDC[18:16] = 111b
+  //
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+  *AndMask = 0xFC00FFFF;
+  *OrMask = 0x01470000;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if ((LogicalId.Revision & AMD_F10_C2) != 0) {
+    //
+    //For F10_C2 single Core, F3xDC[18:16] = 0
+    //
+    GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+    if (CoreCount == 1) {
+      *OrMask = 0x01400000;
+    }
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt =
+{
+  0,
+  GetF10CacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
new file mode 100755
index 0000000000..f72cb0fd1b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c
@@ -0,0 +1,411 @@
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-13 23:58:02 -0700 (Tue, 13 May 2008) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuLateInit.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10Translate7BitVidTo6Bit (
+  IN OUT   UINT8 * MaxVidPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF10GetInfo
+ *
+ *    Get CPU type information
+ *
+ *    @param[in,out]  CpuInfoPtr     Pointer to CPU_TYPE_INFO struct.
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *
+ */
+STATIC VOID
+DmiF10GetInfo (
+  IN OUT   CPU_TYPE_INFO *CpuInfoPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CPUID_DATA CpuId;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
+  CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
+  CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
+  CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
+  CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4)  & 0xF; // bit 7:4
+  CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
+
+  CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+  CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15
+  CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11
+  CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
+  CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
+  CpuInfoPtr->TotalCoreNumber--;
+
+  LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
+  CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
+
+  switch (CpuInfoPtr->PackageType) {
+  case DR_SOCKET_1207:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_F1207;
+    break;
+  case DR_SOCKET_AM3:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_AM3;
+    break;
+  case DR_SOCKET_S1G3:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_S1GX;
+    break;
+  case DR_SOCKET_G34:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_G34;
+    break;
+  case DR_SOCKET_ASB2:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
+    break;
+  case DR_SOCKET_C32:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_C32;
+    break;
+  default:
+    CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
+    break;
+  }
+
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF10GetVoltage
+ *
+ *    Get the voltage value according to SMBIOS SPEC's requirement.
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *
+ *    @retval  Voltage   - CPU Voltage.
+ *
+ */
+STATIC UINT8
+DmiF10GetVoltage (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8     MaxVid;
+  UINT8     Voltage;
+  UINT32    Pvimode;
+  UINT32    CurrentNodeNum;
+  UINT64    MsrData;
+  PCI_ADDR  TempAddr;
+
+  // Voltage = 0x80 + (voltage at boot time * 10)
+  GetCurrentNodeNum (&CurrentNodeNum, StdHeader);
+  TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_3, PW_CTL_MISC_REG);
+  LibAmdPciReadBits (TempAddr, 8, 8, &Pvimode, (VOID *)StdHeader);
+  //Pvimode is a 1-bit register field:  1-PVI 0-SVI
+
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
+  MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
+  if (MaxVid == 0) {
+    LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
+    MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
+  }
+
+  if (Pvimode) {
+    // PVI mode
+    F10Translate7BitVidTo6Bit (&MaxVid);
+    if (MaxVid >= 0x20) {
+      Voltage = (UINT8) ((7625 - (125 * (MaxVid - 0x20)) + 500) / 1000);
+    } else {
+      Voltage = (UINT8) ((1550 - (25 * MaxVid) + 50) / 100);
+    }
+  } else {
+    // is SVI mode
+    if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
+      Voltage = 0;
+    } else {
+      Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000);
+    }
+  }
+
+  Voltage += 0x80;
+  return (Voltage);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  DmiF10GetMaxSpeed
+ *
+ *    Get the Max Speed
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *
+ *    @retval  MaxSpeed   - CPU Max Speed.
+ *
+ */
+STATIC UINT16
+DmiF10GetMaxSpeed (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT8 TempVar8_a;
+  UINT64 MsrData;
+  UINT16  MaxSpeed;
+
+  // CPU COF = 100MHz * (CpuFid + 0x10) / (2 ^ CpuDid)
+  LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
+  TempVar8_a = (UINT8) ((PSTATE_MSR *) &MsrData)->CpuDid;
+  switch (TempVar8_a) {
+  case 0:
+    TempVar8_a = 1;
+    break;
+  case 1:
+    TempVar8_a = 2;
+    break;
+  case 2:
+    TempVar8_a = 4;
+    break;
+  case 3:
+    TempVar8_a = 8;
+    break;
+  case 4:
+    TempVar8_a = 16;
+    break;
+  default:
+    TempVar8_a = 1;
+    break;
+  }
+
+  MaxSpeed = (UINT16) (MsrData & 0x3F); // get CpuFid
+  MaxSpeed = (100 * (MaxSpeed + 0x10)) / TempVar8_a;
+  return (MaxSpeed);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ * Processor Family Table
+ *
+ * Note: 'x' means we don't care this field
+ *       002h = "Unknown"
+ *       038h = "AMD Turion(TM) II Ultra Dual-Core Mobile M Processor Family"
+ *       039h = "AMD Turion(TM) II Dual-Core Mobile M Processor Family"
+ *       03Ah = "AMD Athlon(TM) II Dual-Core M Processor Family"
+ *       083h = "AMD Athlon(tm) 64 Processor Family"
+ *       084h = "AMD Opteron(TM) Processor Family"
+ *       085h = "AMD Sempron(tm) Processor Family"
+ *       087h = "Dual-Core AMD Opteron Processor Family"
+ *       08Ah = "Quad-Core AMD Opteron Processor Family"
+ *       08Ch = "AMD Phenom FX Quad-Core Processor Family"
+ *       08Dh = "AMD Phenom X4 Quad-Core Processor Family"
+ *       08Eh = "AMD Phenom X2 Dual-Core Processor Family"
+ *       08Fh = "AMD Athlon X2 Dual-Core Processor Family"
+ *       0E6h = "Embedded AMD Opteron Processor Family"
+ *       0E7h = "AMD Phenom Triple-Core Processor Family"
+ *       0ECh = "AMD Phenom(TM) II Processor Family"
+ *       0EDh = "AMD Athlon(TM) II Processor Family"
+ *       0EEh = "Six-Core AMD Opteron(TM) Processor Family"
+ *       0EFh = "AMD Sempron(TM) M Processor Family"
+ *-------------------------------------------------------------------------------------*/
+CONST DMI_BRAND_ENTRY ROMDATA Family10BrandList[] =
+{
+  // Brand --> DMI ID translation table
+  // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
+  // {'x', 'x', 'x', 'x', 0x02} MUST be the last one.
+    {0, 0, 1, 0, 0x87},
+    {0, 0, 1, 1, 0x87},
+    {0, 0, 2, 0, 0xE6},
+    {0, 0, 3, 0, 0x8A},
+    {0, 0, 3, 1, 0x8A},
+    {0, 0, 3, 2, 0xE6},
+    {0, 0, 3, 3, 0xE6},
+    {0, 0, 3, 4, 0xE6},
+    {0, 0, 3, 5, 0x8C},
+    {0, 0, 5, 0, 0xEE},
+    {0, 0, 5, 1, 0xEE},
+    {0, 1, 3, 1, 0xE6},
+    {1, 0, 0, 0, 0x83},
+    {1, 0, 0, 1, 0x85},
+    {1, 0, 0, 2, 0x85},
+    {1, 0, 0, 3, 0xED},
+    {1, 0, 1, 0, 0x87},
+    {1, 0, 1, 1, 0x8F},
+    {1, 0, 1, 2, 0xED},
+    {1, 0, 1, 3, 0xED},
+    {1, 0, 1, 4, 0xED},
+    {1, 0, 1, 5, 0xED},
+    {1, 0, 1, 6, 0xED},
+    {1, 0, 1, 7, 0xEC},
+    {1, 0, 1, 8, 0xED},
+    {1, 0, 1, 9, 0xED},
+    {1, 0, 1, 0xA, 0xEC},
+    {1, 0, 1, 0xB, 0xEC},
+    {1, 0, 2, 0, 0xE7},
+    {1, 0, 2, 1, 0xEC},
+    {1, 0, 2, 2, 0xEC},
+    {1, 0, 2, 3, 0xEC},
+    {1, 0, 2, 4, 0xEC},
+    {1, 0, 2, 5, 0xED},
+    {1, 0, 2, 6, 0xED},
+    {1, 0, 2, 7, 0xED},
+    {1, 0, 2, 8, 0xEC},
+    {1, 0, 2, 9, 0xED},
+    {1, 0, 2, 0xA, 0xED},
+    {1, 0, 3, 0, 0x8A},
+    {1, 0, 3, 1, 0x8C},
+    {1, 0, 3, 2, 0x8D},
+    {1, 0, 3, 3, 0xEC},
+    {1, 0, 3, 4, 0xEC},
+    {1, 0, 3, 5, 0xEC},
+    {1, 0, 3, 6, 0xEC},
+    {1, 0, 3, 7, 0xEC},
+    {1, 0, 3, 8, 0xEC},
+    {1, 0, 3, 9, 0xEC},
+    {1, 0, 3, 0xA, 0xED},
+    {1, 0, 3, 0xB, 0xED},
+    {1, 0, 3, 0xC, 0xED},
+    {1, 0, 3, 0xD, 0xED},
+    {1, 0, 3, 0xE, 0xEC},
+    {1, 0, 3, 0xF, 0xED},
+    {1, 1, 1, 1, 0xED},
+    {1, 1, 1, 2, 0xED},
+    {1, 1, 3, 0, 0xEC},
+    {1, 1, 3, 1, 0xEC},
+    {2, 0, 0, 0, 0xEF},
+    {2, 0, 0, 1, 0xEF},
+    {2, 0, 1, 0, 0x38},
+    {2, 0, 1, 1, 0x39},
+    {2, 0, 1, 2, 0x3A},
+    {2, 0, 1, 3, 0x39},
+    {2, 0, 1, 4, 0xED},
+    {2, 0, 1, 5, 0xEC},
+    {2, 0, 1, 6, 0xEC},
+    {2, 0, 1, 7, 0x39},
+    {2, 0, 1, 8, 0xED},
+    {2, 0, 2, 2, 0xEC},
+    {2, 0, 2, 3, 0xEC},
+    {2, 0, 3, 1, 0xEC},
+    {2, 0, 3, 2, 0xEC},
+    {2, 0, 3, 3, 0xEC},
+    {3, 0, 7, 0, 0x84},
+    {3, 0, 0xB, 0, 0x84},
+    {4, 0, 0, 1, 0xED},
+    {4, 0, 1, 1, 0x39},
+    {4, 0, 1, 2, 0xED},
+    {5, 'x', 'x', 'x', 0x84},
+    {'x', 'x', 'x', 'x', 0x02}
+  };
+
+CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
+{
+// This table is for Processor family 10h
+  AMD_FAMILY_10,                      // ID for Family 10h
+  DmiF10GetInfo,                  // Transfer vectors for family
+  DmiF10GetVoltage,                  //   specific routines (above)
+  DmiF10GetMaxSpeed,
+  (sizeof (Family10BrandList) / sizeof (Family10BrandList[0])), // Number of entries in following table
+  &Family10BrandList[0]
+};
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  F10Translate7BitVidTo6Bit
+ *
+ *    translate 7 bit VID to 6 bit VID
+ *
+ *    @param[in]  MaxVidPtr   - Pointer to MaxVid.
+ */
+VOID
+STATIC
+F10Translate7BitVidTo6Bit (
+  IN OUT   UINT8 * MaxVidPtr
+  )
+{
+  if ((*MaxVidPtr >= 0x5E) && (*MaxVidPtr <= 0x7F)) {
+    *MaxVidPtr = 0x3F;
+  } else if ((*MaxVidPtr >= 0x3F) && (*MaxVidPtr <= 0x5D)) {
+    *MaxVidPtr = *MaxVidPtr - 0x1F;
+  } else if (*MaxVidPtr <= 0x3E) {
+    *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
new file mode 100755
index 0000000000..d5c98aa59d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
@@ -0,0 +1,403 @@
+/**
+ * @file
+ *
+ * AMD Family_10 after warm reset sequence
+ *
+ * Performs the "CPU Core Minimum P-State Transition Sequence After Warm Reset"
+ * as described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "cpuF10EarlyInit.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Enum for handling code branching while transitioning to the
+/// minimum P-state after a warm reset
+typedef enum {
+  EXIT_SEQUENCE,        ///< Exit the sequence
+  STEP7,                ///< Go to step 7
+  STEP17,               ///< Go to step 17
+  STEP20                ///< Go to step 20
+} GO_TO_STEP;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10PmAfterResetCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+WaitForCpuFidAndDidToMatch (
+  IN       UINT32             PstateNumber,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the necessary steps after
+ * a warm reset has occurred.
+ *
+ * The steps are as follows:
+ *    1. Modify F3xDC[PstateMaxVal] to reflect the lowest performance P-state
+ *       supported, as indicated in MSRC001_00[68:64][PstateEn]
+ *    2. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
+ *    3. If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
+ *    4. If F3xDC[PstateMaxVal] = 0 or F3xDC[PstateMaxVal] != 4, go to step 7
+ *    5. If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
+ *    6. Exit the sequence
+ *    7. Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
+ *       register pointed to by F3xDC[PstateMaxVal]+1
+ *    8. Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
+ *    9. Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+ *   10. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by (the new) F3xDC[PstateMaxVal]
+ *   11. Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+ *   12. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by (the new) F3xDC[PstateMaxVal]-1
+ *   13. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
+ *   14. If required, transition the NB COF and VID to the NbDid and NbVid from the
+ *       P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
+ *       and VID transition sequence after a warm reset
+ *   15. Write MSRC001_00[68:64][PstateEn]=0 for the P-state pointed to by F3xDC[PstateMaxVal]
+ *   16. Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] and exit the sequence
+ *   17. Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+ *   18. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by F3xDC[PstateMaxVal]-1
+ *   19. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
+ *   20. Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+ *   21. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+ *       register pointed to by F3xDC[PstateMaxVal]
+ *   22. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
+ *   23. Issue an LDTSTOP assertion in the IO hub and exit sequence
+ *   24. If required, transition the NB COF and VID to the NbDid and NbVid from the
+ *       P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
+ *       transition sequence after a warm reset
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    PsMaxVal;
+  UINT32    CoreNum;
+  UINT32    MsrAddr;
+  UINT32    Core;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT64    MsrRegister;
+  PCI_ADDR  PciAddress;
+  AP_TASK   TaskPtr;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+
+  ASSERT (Core == 0);
+
+  // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
+  //        P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
+  for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
+    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+  PsMaxVal = MsrAddr - PS_REG_BASE;
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = CPTC2_REG;
+  AndMask = 0xFFFFFFFF;
+  OrMask = 0x00000000;
+  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
+  ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PsMaxVal;
+  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+  // Launch each local core to perform the remaining steps.
+  TaskPtr.FuncAddress.PfApTask = F10PmAfterResetCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+}
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmAfterReset to perform MSR initialization on all
+ * cores of a family 10h socket.
+ *
+ * This function implements steps 2 - 24 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmAfterResetCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Ignored;
+  UINT32 PsMaxVal;
+  UINT32 PciRegister;
+  UINT64 MsrRegister;
+  UINT64 CurrentLimitMsr;
+  PCI_ADDR PciAddress;
+  GO_TO_STEP GoToStep;
+  AGESA_STATUS IgnoredSts;
+  CPU_LOGICAL_ID LogicalId;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
+  if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+    if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
+      LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+      MsrRegister |= BIT62;
+      LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+    }
+  }
+
+  GoToStep = EXIT_SEQUENCE;
+
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &CurrentLimitMsr, StdHeader);
+  PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
+
+  // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
+  LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+  if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate !=
+      ((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
+    GoToStep = STEP20;
+  } else {
+    // Step 4 If F3xDC[PstateMaxVal] = 0 || F3xDC[PstateMaxVal] != 4, go to step 7
+    if ((PsMaxVal == 0) || (PsMaxVal != 4)) {
+      GoToStep = STEP7;
+    } else {
+      // Step 5 If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
+      if (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->CurPstateLimit <=
+          (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal - 1)) {
+        GoToStep = STEP17;
+      }
+    }
+  }
+  switch (GoToStep) {
+  default:
+  case EXIT_SEQUENCE:
+    // Step 6 Exit the sequence
+    break;
+  case STEP7:
+    // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
+    //        register pointed to by F3xDC[PstateMaxVal]+1
+    LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader);
+    LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+
+    // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = CPTC2_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PsMaxVal + 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+    // Step 9 Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal + 1), (BOOLEAN) FALSE, StdHeader);
+
+    // Step 10 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by (the new) F3xDC[PstateMaxVal]
+    WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal + 1), StdHeader);
+
+    // Step 11 Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
+
+    // Step 12 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by (the new) F3xDC[PstateMaxVal]-1
+    WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
+
+    // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
+    if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
+        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+        MsrRegister |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      }
+    }
+
+    // Step 14 If required, transition the NB COF and VID to the NbDid and NbVid from the
+    //         P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
+    //         and VID transition sequence after a warm reset
+
+    // Step 15 Write 0 to PstateEn of the P-state register pointed to by (the new) F3xDC[PstateMaxVal]
+    LibAmdMsrRead ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+    ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
+    LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
+
+    // Step 16 Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal]
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PsMaxVal;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    break;
+  case STEP17:
+    // Step 17 Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal - 1), (BOOLEAN) FALSE, StdHeader);
+
+    // Step 18 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by F3xDC[PstateMaxVal]-1
+    WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal - 1), StdHeader);
+
+    // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
+    if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
+        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+        MsrRegister |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+      }
+    }
+
+    // Fall through from step 19 to step 20
+  case STEP20:
+    // Step 20 Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
+
+    // Step 21 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
+    //         register pointed to by F3xDC[PstateMaxVal]
+    WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
+
+    // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
+    //         the sequence
+    if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+      if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
+        LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
+        MsrRegister |= BIT62;
+        LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
+        break;
+      }
+    }
+
+    // Step 23 Issue an LDTSTOP and exit the sequence
+
+    // Step 24 If required, transition the NB COF and VID to the NbDid and NbVid from the
+    //         P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
+    //         transition sequence after a warm reset
+    break;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
+ * match a specific P-state.
+ *
+ * This function implements steps 11, 13, 18, and 20 on each core as needed.
+ *
+ * @param[in]  PstateNumber       P-state settings to match
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+WaitForCpuFidAndDidToMatch (
+  IN       UINT32             PstateNumber,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT64  TargetPsMsr;
+  UINT64  CurrentStatus;
+
+  // Get target P-state settings
+  LibAmdMsrRead ((MSR_PSTATE_0 + PstateNumber), &TargetPsMsr, StdHeader);
+
+  // Wait for current CPU FID/DID to match target FID/DID
+  do {
+    LibAmdMsrRead (MSR_COFVID_STS, &CurrentStatus, StdHeader);
+  } while ((((COFVID_STS_MSR *) &CurrentStatus)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
+           (((COFVID_STS_MSR *) &CurrentStatus)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h
new file mode 100755
index 0000000000..a55a4832b7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10EarlyInit.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Early Init related functions Prototypes.
+ *
+ * Contains code that provide power management functionality
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_EARLY_INIT_H_
+#define _CPU_F10_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmAfterReset (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_EARLY_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
new file mode 100755
index 0000000000..12a2e88977
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
@@ -0,0 +1,389 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific feature leveling functions.
+ *
+ * Provides feature leveling functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuPostInit.h"
+#include "cpuF10FeatureLeveling.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+BOOLEAN
+STATIC
+cpuFeatureListNeedUpdate (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  );
+
+VOID
+STATIC
+updateCpuFeatureList (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function get features which CPU supports.
+ *
+ *  @CpuServiceMethod{::F_CPU_SAVE_FEATURES}.
+ *
+ *  Read features from MSR_C0011004 and MSR_C0011005.
+ *
+ *    @param[in]      FamilySpecificServices   - Pointer to CPU_SPECIFIC_SERVICES struct.
+ *    @param[in,out]  cpuFeatureList           - Pointer to CPU_FEATURES_LIST struct.
+ *    @param[in]      StdHeader                - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+F10SaveFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 CpuMsrData;
+  BOOLEAN *FirstTime;
+  BOOLEAN *NeedLeveling;
+  CPU_F10_FEATURES *CpuF10Features;
+  CPU_F10_EXT_FEATURES *CpuF10ExtFeatures;
+  CPU_FEATURES_LIST thisCoreCpuFeatureList;
+
+  FirstTime = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST));
+  NeedLeveling = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
+
+  LibAmdMemFill (&thisCoreCpuFeatureList, 0x0, sizeof (CPU_FEATURES_LIST), StdHeader);
+  LibAmdMsrRead (MSR_CPUID_FEATS, &CpuMsrData, StdHeader);
+  CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData;
+
+  thisCoreCpuFeatureList.APIC = (UINT8) CpuF10Features->CpuF10FeaturesLo.APIC;
+  thisCoreCpuFeatureList.CLFSH = (UINT8) CpuF10Features->CpuF10FeaturesLo.CLFSH;
+  thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMOV;
+  thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B;
+  thisCoreCpuFeatureList.DE = (UINT8) CpuF10Features->CpuF10FeaturesLo.DE;
+  thisCoreCpuFeatureList.FPU = (UINT8) CpuF10Features->CpuF10FeaturesLo.FPU;
+  thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.FXSR;
+  thisCoreCpuFeatureList.HTT = (UINT8) CpuF10Features->CpuF10FeaturesLo.HTT;
+  thisCoreCpuFeatureList.MCA = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCA;
+  thisCoreCpuFeatureList.MCE = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCE;
+  thisCoreCpuFeatureList.MMX = (UINT8) CpuF10Features->CpuF10FeaturesLo.MMX;
+  thisCoreCpuFeatureList.MSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MSR;
+  thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MTRR;
+  thisCoreCpuFeatureList.PAE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAE;
+  thisCoreCpuFeatureList.PAT = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAT;
+  thisCoreCpuFeatureList.PGE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PGE;
+  thisCoreCpuFeatureList.PSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE;
+  thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE36;
+  thisCoreCpuFeatureList.SSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE;
+  thisCoreCpuFeatureList.SSE2 = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE2;
+  thisCoreCpuFeatureList.SysEnterSysExit = (UINT8) CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit;
+  thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10Features->CpuF10FeaturesLo.TimeStampCounter;
+  thisCoreCpuFeatureList.VME = (UINT8) CpuF10Features->CpuF10FeaturesLo.VME;
+
+  thisCoreCpuFeatureList.CMPXCHG16B = (UINT8) CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B;
+  thisCoreCpuFeatureList.Monitor = (UINT8) CpuF10Features->CpuF10FeaturesHi.Monitor;
+  thisCoreCpuFeatureList.POPCNT = (UINT8) CpuF10Features->CpuF10FeaturesHi.POPCNT;
+  thisCoreCpuFeatureList.SSE3 = (UINT8) CpuF10Features->CpuF10FeaturesHi.SSE3;
+
+  LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
+  CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData;
+
+  thisCoreCpuFeatureList.ThreeDNow = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow;
+  thisCoreCpuFeatureList.ThreeDNowExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt;
+  thisCoreCpuFeatureList.APIC = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC;
+  thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV;
+  thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B;
+  thisCoreCpuFeatureList.DE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE;
+  thisCoreCpuFeatureList.FFXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR;
+  thisCoreCpuFeatureList.FPU = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU;
+  thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR;
+  thisCoreCpuFeatureList.LM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM;
+  thisCoreCpuFeatureList.MCA = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA;
+  thisCoreCpuFeatureList.MCE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE;
+  thisCoreCpuFeatureList.MMX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX;
+  thisCoreCpuFeatureList.MmxExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt;
+  thisCoreCpuFeatureList.MSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR;
+  thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR;
+  thisCoreCpuFeatureList.NX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX;
+  thisCoreCpuFeatureList.PAE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE;
+  thisCoreCpuFeatureList.Page1GB = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB;
+  thisCoreCpuFeatureList.PAT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT;
+  thisCoreCpuFeatureList.PGE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE;
+  thisCoreCpuFeatureList.PSE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE;
+  thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36;
+  thisCoreCpuFeatureList.RDTSCP = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP;
+  thisCoreCpuFeatureList.SysCallSysRet = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet;
+  thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter;
+  thisCoreCpuFeatureList.VME = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME;
+
+  thisCoreCpuFeatureList.ThreeDNowPrefetch = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch;
+  thisCoreCpuFeatureList.ABM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM;
+  thisCoreCpuFeatureList.AltMovCr8 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8;
+  thisCoreCpuFeatureList.CmpLegacy = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy;
+  thisCoreCpuFeatureList.ExtApicSpace = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace;
+  thisCoreCpuFeatureList.IBS = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS;
+  thisCoreCpuFeatureList.LahfSahf = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf;
+  thisCoreCpuFeatureList.MisAlignSse = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse;
+  thisCoreCpuFeatureList.OSVW = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM;
+  thisCoreCpuFeatureList.SKINIT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT;
+  thisCoreCpuFeatureList.SSE4A = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A;
+  thisCoreCpuFeatureList.SVM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM;
+  thisCoreCpuFeatureList.WDT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT;
+  thisCoreCpuFeatureList.NodeId = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId;
+
+  if (*FirstTime) {
+    updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList);
+    *FirstTime = FALSE;
+  } else if (cpuFeatureListNeedUpdate (cpuFeatureList, &thisCoreCpuFeatureList)) {
+    updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList);
+    *NeedLeveling = TRUE;
+  }
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  This function set features which All CPUs support.
+ *
+ *  @CpuServiceMethod{::F_CPU_WRITE_FEATURES}.
+ *
+ *  Write least common features to MSR_C0011004 and MSR_C0011005.
+ *
+ *    @param[in]      FamilySpecificServices   - Pointer to CPU_SPECIFIC_SERVICES struct.
+ *    @param[in,out]  cpuFeatureList           - Pointer to CPU_FEATURES_LIST struct.
+ *    @param[in]      StdHeader                - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+F10WriteFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 CpuMsrData;
+  CPU_F10_FEATURES *CpuF10Features;
+  CPU_F10_EXT_FEATURES *CpuF10ExtFeatures;
+
+  CpuMsrData = 0;
+  CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData;
+
+  CpuF10Features->CpuF10FeaturesLo.APIC = cpuFeatureList->APIC;
+  CpuF10Features->CpuF10FeaturesLo.CLFSH = cpuFeatureList->CLFSH;
+  CpuF10Features->CpuF10FeaturesLo.CMOV = cpuFeatureList->CMOV;
+  CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B;
+  CpuF10Features->CpuF10FeaturesLo.DE = cpuFeatureList->DE;
+  CpuF10Features->CpuF10FeaturesLo.FPU = cpuFeatureList->FPU;
+  CpuF10Features->CpuF10FeaturesLo.FXSR = cpuFeatureList->FXSR;
+  CpuF10Features->CpuF10FeaturesLo.HTT = cpuFeatureList->HTT;
+  CpuF10Features->CpuF10FeaturesLo.MCA = cpuFeatureList->MCA;
+  CpuF10Features->CpuF10FeaturesLo.MCE = cpuFeatureList->MCE;
+  CpuF10Features->CpuF10FeaturesLo.MMX = cpuFeatureList->MMX;
+  CpuF10Features->CpuF10FeaturesLo.MSR = cpuFeatureList->MSR;
+  CpuF10Features->CpuF10FeaturesLo.MTRR = cpuFeatureList->MTRR;
+  CpuF10Features->CpuF10FeaturesLo.PAE = cpuFeatureList->PAE;
+  CpuF10Features->CpuF10FeaturesLo.PAT = cpuFeatureList->PAT;
+  CpuF10Features->CpuF10FeaturesLo.PGE = cpuFeatureList->PGE;
+  CpuF10Features->CpuF10FeaturesLo.PSE = cpuFeatureList->PSE;
+  CpuF10Features->CpuF10FeaturesLo.PSE36 = cpuFeatureList->PSE36;
+  CpuF10Features->CpuF10FeaturesLo.SSE = cpuFeatureList->SSE;
+  CpuF10Features->CpuF10FeaturesLo.SSE2 = cpuFeatureList->SSE2;
+  CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit = cpuFeatureList->SysEnterSysExit;
+  CpuF10Features->CpuF10FeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter;
+  CpuF10Features->CpuF10FeaturesLo.VME = cpuFeatureList->VME;
+
+  CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B = cpuFeatureList->CMPXCHG16B;
+  CpuF10Features->CpuF10FeaturesHi.Monitor = cpuFeatureList->Monitor;
+  CpuF10Features->CpuF10FeaturesHi.POPCNT = cpuFeatureList->POPCNT;
+  CpuF10Features->CpuF10FeaturesHi.SSE3 = cpuFeatureList->SSE3;
+
+  LibAmdMsrWrite (MSR_CPUID_FEATS, &CpuMsrData, StdHeader);
+
+  CpuMsrData = 0;
+  CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData;
+
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow = cpuFeatureList->ThreeDNow;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt = cpuFeatureList->ThreeDNowExt;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC = cpuFeatureList->APIC;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV = cpuFeatureList->CMOV;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE = cpuFeatureList->DE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR = cpuFeatureList->FFXSR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU = cpuFeatureList->FPU;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR = cpuFeatureList->FXSR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM = cpuFeatureList->LM;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA = cpuFeatureList->MCA;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE = cpuFeatureList->MCE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX = cpuFeatureList->MMX;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt = cpuFeatureList->MmxExt;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR = cpuFeatureList->MSR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR = cpuFeatureList->MTRR;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX = cpuFeatureList->NX;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE = cpuFeatureList->PAE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB = cpuFeatureList->Page1GB;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT = cpuFeatureList->PAT;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE = cpuFeatureList->PGE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE = cpuFeatureList->PSE;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36 = cpuFeatureList->PSE36;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP = cpuFeatureList->RDTSCP;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet = cpuFeatureList->SysCallSysRet;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME = cpuFeatureList->VME;
+
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch = cpuFeatureList->ThreeDNowPrefetch;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM = cpuFeatureList->ABM;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8 = cpuFeatureList->AltMovCr8;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy = cpuFeatureList->CmpLegacy;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace = cpuFeatureList->ExtApicSpace;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS = cpuFeatureList->IBS;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf = cpuFeatureList->LahfSahf;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse = cpuFeatureList->MisAlignSse;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM = cpuFeatureList->OSVW;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT = cpuFeatureList->SKINIT;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A = cpuFeatureList->SSE4A;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM = cpuFeatureList->SVM;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT = cpuFeatureList->WDT;
+  CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId = cpuFeatureList->NodeId;
+  LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  cpuFeatureListNeedUpdate
+ *
+ *    Compare global CPU feature list with this core feature list to see if global CPU feature list
+ *    needs updated.
+ *
+ *    @param[in]  globalCpuFeatureList  - Pointer to global CPU Feature List.
+ *    @param[in]  thisCoreCpuFeatureList  - Pointer to this core CPU Feature List.
+ *
+ *    @retval FALSE  globalCpuFeatureList is equal to thisCoreCpuFeatureList
+ *    @retval True  globalCpuFeatureList is NOT equal to thisCoreCpuFeatureList
+ */
+BOOLEAN
+STATIC
+cpuFeatureListNeedUpdate (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  )
+{
+  BOOLEAN flag;
+  UINT8 *global;
+  UINT8 *thisCore;
+  UINT8 i;
+
+  flag = FALSE;
+  global = (UINT8 *) globalCpuFeatureList;
+  thisCore = (UINT8 *) thisCoreCpuFeatureList;
+
+  for (i = 0; i < sizeof (CPU_FEATURES_LIST); i++) {
+    if ((*global) != (*thisCore)) {
+      flag = TRUE;
+      break;
+    }
+    global++;
+    thisCore++;
+  }
+  return flag;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  updateCpuFeatureList
+ *
+ *    Update global CPU feature list
+ *
+ *    @param[in]  globalCpuFeatureList  - Pointer to global CPU Feature List.
+ *    @param[in]  thisCoreCpuFeatureList  - Pointer to this core CPU Feature List.
+ *
+ */
+VOID
+STATIC
+updateCpuFeatureList (
+  IN       CPU_FEATURES_LIST *globalCpuFeatureList,
+  IN       CPU_FEATURES_LIST *thisCoreCpuFeatureList
+  )
+{
+  UINT8 *globalFeatureList;
+  UINT8 *thisCoreFeatureList;
+  UINT32 sizeInByte;
+
+  globalFeatureList = (UINT8 *) globalCpuFeatureList;
+  thisCoreFeatureList = (UINT8 *) thisCoreCpuFeatureList;
+
+  for (sizeInByte = 0; sizeInByte < sizeof (CPU_FEATURES_LIST); sizeInByte++) {
+    *globalFeatureList &= *thisCoreFeatureList;
+    globalFeatureList++;
+    thisCoreFeatureList++;
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h
new file mode 100755
index 0000000000..6d27821b8d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific feature leveling functions.
+ *
+ * Provides feature leveling functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_FEATURE_LEVELING_H_
+#define _CPU_F10_FEATURE_LEVELING_H_
+
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// F10 CPU Feature Low
+typedef struct {
+  UINT32 FPU:1;               ///< Bit0
+  UINT32 VME:1;               ///< Bit1
+  UINT32 DE:1;                ///< Bit2
+  UINT32 PSE:1;               ///< Bit3
+  UINT32 TimeStampCounter:1;  ///< Bit4
+  UINT32 MSR:1;               ///< Bit5
+  UINT32 PAE:1;               ///< Bit6
+  UINT32 MCE:1;               ///< Bit7
+  UINT32 CMPXCHG8B:1;         ///< Bit8
+  UINT32 APIC:1;              ///< Bit9
+  UINT32 Reserved1:1;         ///< Bit10
+  UINT32 SysEnterSysExit:1;   ///< Bit11
+  UINT32 MTRR:1;              ///< Bit12
+  UINT32 PGE:1;               ///< Bit13
+  UINT32 MCA:1;               ///< Bit14
+  UINT32 CMOV:1;              ///< Bit15
+  UINT32 PAT:1;               ///< Bit16
+  UINT32 PSE36:1;             ///< Bit17
+  UINT32 Reserved2:1;         ///< Bit18
+  UINT32 CLFSH:1;             ///< Bit19
+  UINT32 Reserved3:3;         ///< Bit20~22
+  UINT32 MMX:1;               ///< Bit23
+  UINT32 FXSR:1;              ///< Bit24
+  UINT32 SSE:1;               ///< Bit25
+  UINT32 SSE2:1;              ///< Bit26
+  UINT32 Reserved4:1;         ///< Bit27
+  UINT32 HTT:1;               ///< Bit28
+  UINT32 Reserved5:3;         ///< Bit29~31
+} CPU_F10_FEATURES_LO;
+
+/// F10 CPU Feature High
+typedef struct {
+  UINT32 SSE3:1;            ///< Bit0
+  UINT32 Reserved1:2;       ///< Bit1~2
+  UINT32 Monitor:1;         ///< Bit3
+  UINT32 Reserved2:9;       ///< Bit4~12
+  UINT32 CMPXCHG16B:1;      ///< Bit13
+  UINT32 Reserved3:9;       ///< Bit14~22
+  UINT32 POPCNT:1;          ///< Bit23
+  UINT32 Reserved4:8;       ///< Bit24~31
+} CPU_F10_FEATURES_HI;
+
+/// F10 CPU Feature
+typedef struct {
+  CPU_F10_FEATURES_LO CpuF10FeaturesLo; ///< Low
+  CPU_F10_FEATURES_HI CpuF10FeaturesHi; ///< High
+} CPU_F10_FEATURES;
+
+/// F10 CPU Extended Feature Low
+typedef struct {
+  UINT32 FPU:1;               ///< Bit0
+  UINT32 VME:1;               ///< Bit1
+  UINT32 DE:1;                ///< Bit2
+  UINT32 PSE:1;               ///< Bit3
+  UINT32 TimeStampCounter:1;  ///< Bit4
+  UINT32 MSR:1;               ///< Bit5
+  UINT32 PAE:1;               ///< Bit6
+  UINT32 MCE:1;               ///< Bit7
+  UINT32 CMPXCHG8B:1;         ///< Bit8
+  UINT32 APIC:1;              ///< Bit9
+  UINT32 Reserved1:1;         ///< Bit10
+  UINT32 SysCallSysRet:1;     ///< Bit11
+  UINT32 MTRR:1;              ///< Bit12
+  UINT32 PGE:1;               ///< Bit13
+  UINT32 MCA:1;               ///< Bit14
+  UINT32 CMOV:1;              ///< Bit15
+  UINT32 PAT:1;               ///< Bit16
+  UINT32 PSE36:1;             ///< Bit17
+  UINT32 Reserved2:2;         ///< Bit18~19
+  UINT32 NX:1;                ///< Bit20
+  UINT32 Reserved3:1;         ///< Bit21
+  UINT32 MmxExt:1;            ///< Bit22
+  UINT32 MMX:1;               ///< Bit23
+  UINT32 FXSR:1;              ///< Bit24
+  UINT32 FFXSR:1;             ///< Bit25
+  UINT32 Page1GB:1;           ///< Bit26
+  UINT32 RDTSCP:1;            ///< Bit27
+  UINT32 Reserved4:1;         ///< Bit28
+  UINT32 LM:1;                ///< Bit29
+  UINT32 ThreeDNowExt:1;      ///< Bit30
+  UINT32 ThreeDNow:1;         ///< Bit31
+} CPU_F10_EXT_FEATURES_LO;
+
+/// F10 CPU Extended Feature High
+typedef struct {
+  UINT32 LahfSahf:1;        ///< Bit0
+  UINT32 CmpLegacy:1;       ///< Bit1
+  UINT32 SVM:1;             ///< Bit2
+  UINT32 ExtApicSpace:1;    ///< Bit3
+  UINT32 AltMovCr8:1;       ///< Bit4
+  UINT32 ABM:1;             ///< Bit5
+  UINT32 SSE4A:1;           ///< Bit6
+  UINT32 MisAlignSse:1;     ///< Bit7
+  UINT32 ThreeDNowPrefetch:1; ///< Bit8
+  UINT32 OSVM:1;            ///< Bit9
+  UINT32 IBS:1;             ///< Bit10
+  UINT32 Reserved1:1;       ///< Bit11
+  UINT32 SKINIT:1;          ///< Bit12
+  UINT32 WDT:1;             ///< Bit13
+  UINT32 Reserved2:5;       ///< Bit14~18
+  UINT32 NodeId:1;          ///< Bit19
+  UINT32 Reserved3:12;      ///< Bit20~31
+} CPU_F10_EXT_FEATURES_HI;
+
+/// F10 CPU Extended Feature
+typedef struct {
+  CPU_F10_EXT_FEATURES_LO CpuF10ExtFeaturesLo;  ///< Low
+  CPU_F10_EXT_FEATURES_HI CpuF10ExtFeaturesHi;  ///< High
+} CPU_F10_EXT_FEATURES;
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10SaveFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10WriteFeatures (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN OUT   CPU_FEATURES_LIST *cpuFeatureList,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+#endif  // _CPU_F10_FEATURE_LEVELING_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
new file mode 100755
index 0000000000..ecf85c12e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
@@ -0,0 +1,747 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DR PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   P C I   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HtPhyRegisters[] =
+{
+// 0xCF
+// HT_PHY_HT1_FIFO_PTR_OPT_VALUE
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xCF,                                 // Address
+      0x0000006D,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// HT_PHY_HT1_FIFO_PTR_OPT_VALUE
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xDF,                                 // Address
+      0x0000006D,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xCF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000005A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xD1
+// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD1,                                 // Address
+      0x08040000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+// 0xC1
+// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC1,                                 // Address
+      0x08040000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+// 0xD1
+// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xD1,                                 // Address
+      0x04020000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+// 0xC1
+// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xC1,                                 // Address
+      0x04020000,                           // regData
+      0x3FFFC000,                           // regMask
+    }}
+  },
+//
+// Deemphasis Settings
+//
+
+// HT1: clear any warm reset deemphasis settings.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xC5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xD5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT1,               //
+      0xC4,                                 // Address
+      0x00000000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT1,               //
+      0xD4,                                 // Address
+      0x00000000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0000,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0640,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0640,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0D40,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0D40,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F0647,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F0647,                           // regData
+      0xE01F1F5F,                           // regMask
+    }}
+  },
+
+// Far-device deemphasis setting DCV[15:10]
+// No deemphasis                 20h
+// -2dB postcursor               19h
+// -3dB postcursor               17h
+// -5dB postcursor               11h
+// -6dB postcursor               10h
+// -7dB postcursor               0Eh
+// -8dB postcursor               0Dh
+// -9dB postcursor               0Bh
+// -11dB postcursor              09h
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00008000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00008000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__2,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00006400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__2,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00006400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00005C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00005C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__5,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00004400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__5,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00004400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00004000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00004000,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__7,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00003800,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__7,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00003800,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00003400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00003400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__9,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00002C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__9,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00002C00,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC4,                                 // Address
+      0x00002400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DCV_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD4,                                 // Address
+      0x00002400,                           // regData
+      0x0000FC00,                           // regMask
+    }}
+  },
+
+};
+
+CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10HtPhyRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
new file mode 100755
index 0000000000..29840c8185
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10MsrTables.c
@@ -0,0 +1,270 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DR, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10MsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_TOM2 (0xC001001D)
+// bits[63:0] - TOP_MEM2 = 0
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_TOM2,                              // MSR Address
+      0x0000000000000000ull,                    // OR Mask
+      0xFFFFFFFFFFFFFFFFull,                    // NAND Mask
+    }}
+  },
+// MSR_SYS_CFG (0xC0010010)
+// bit[21] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_SYS_CFG,                           // MSR Address
+      (1 << 21),                             // OR Mask
+      (1 << 21),                             // NAND Mask
+    }}
+  },
+// MSR_HWCR (0xC0010015)
+// Do not set bit[24] = 1, it will be set in AmdInitPost.
+// bit[4] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_HWCR,                              // MSR Address
+      0x0000000000000010ull,                    // OR Mask
+      0x0000000000000010ull,                    // NAND Mask
+    }}
+  },
+// MSR_MC4_CTL_MASK (0xC0010048)
+// bit[10] = 1
+// bits[22:19] = 1111b
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_MC4_CTL_MASK,                      // MSR Address
+      0x0000000000780400ull,                    // OR Mask
+      0x0000000000780400ull,                    // NAND Mask
+    }}
+  },
+// MSR_DC_CFG (0xC0011022)
+// bits[35:34] = 01
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_MULTI_LINK},                     // platformFeatures
+    {{
+      MSR_DC_CFG,                            // MSR Address
+      0x0000000400000000ull,                    // OR Mask
+      0x0000000C00000000ull,                    // NAND Mask
+    }}
+  },
+// MSR_NB_CFG (0xC001001F)
+// bit[54] = 1
+// bit[52:51] = 11b for Erratum #372
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},   // platformFeatures
+    {{
+      MSR_NB_CFG,                            // MSR Address
+      0x0058000000000000ull,                    // OR Mask
+      0x0058000000000000ull,                    // NAND Mask
+    }}
+  },
+// MSR_DC_CFG (0xC0011022)
+// bit[24] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_DC_CFG,                            // MSR Address
+      (1 << 24),                             // OR Mask
+      (1 << 24),                             // NAND Mask
+    }}
+  },
+// MSR_CPUID_FEATS (0xC0011004)
+// bit[28] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_MULTI_CORE | AMD_PF_DUAL_CORE)},  // platformFeatures
+    {{
+      MSR_CPUID_FEATS,                       // MSR Address
+      (1 << 28),                             // OR Mask
+      (1 << 28),                             // NAND Mask
+    }}
+  },
+// MSR_CPUID_EXT_FEATS (0xC0011005)
+// bit[33] = 1
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_DUAL_CORE},                     // platformFeatures
+    {{
+      MSR_CPUID_EXT_FEATS,                   // MSR Address
+      0x0000000200000000ull,                    // OR Mask
+      0x0000000200000000ull,                    // NAND Mask
+    }}
+  },
+// MSR_OSVW_ID_Length (0xC0010140)
+// bit[15:0] = 4
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_OSVW_ID_Length,                    // MSR Address
+      0x0000000000000004ull,                    // OR Mask
+      0x000000000000FFFFull,                    // NAND Mask
+    }}
+  },
+// MSR_OSVW_Status (0xC0010141)
+// bit[3] = 1 for Erratum #383
+// bit[2] = 1 for Erratum #415
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_OSVW_Status,                       // MSR Address
+      0x000000000000000Cull,                    // OR Mask
+      0x000000000000000Cull,                    // NAND Mask
+    }}
+  },
+// This MSR should be set after the code that most errata would be applied in
+// MSR_MC0_CTL (0x00000400)
+// bits[63:0]  = 0xFFFFFFFFFFFFFFFF
+  {
+    MSRREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_MC0_CTL,                           // MSR Address
+      0xFFFFFFFFFFFFFFFFull,                    // OR Mask
+      0xFFFFFFFFFFFFFFFFull,                    // NAND Mask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
+  AllCores,
+  (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PciTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PciTables.c
new file mode 100755
index 0000000000..a977be06d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PciTables.c
@@ -0,0 +1,768 @@
+/**
+ * @file
+ *
+ * AMD Family_10 DR PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PciRegisters[] =
+{
+// Function 0 - HT Config
+
+// F0x68 - Link Transaction Control
+// bit[11]   , RespPassPW = 1
+// bit[19:17], for 8bit APIC config
+// bit[22:21], DsNpReqLmt = 10h
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x004E0800,                           // regData
+      0x006E0800,                           // regMask
+    }}
+  },
+// F0x68 - Link Transaction Control
+// For uni-processor systems (that is, single link package processors), single core, and no L3:
+// [10, DisFillP] = 1b
+// [3, DisWrDwP] = 1b
+// [2, DisWrBP] = 1b
+// [1, DisRdDwP] = 1b
+// [0, DisRdBP] = 1b
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    {(AMD_PF_AND | AMD_PF_SINGLE_CORE | AMD_PF_SINGLE_LINK)},   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x0000040F,                           // regData
+      0x0000040F,                           // regMask
+    }}
+  },
+// F0x[E4,C4,A4,84] - Link 0 Control Register
+// bit[13] LdtStopTriEn = 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x04,                                 // Address
+      0x00002000,                           // regData
+      0x00002000,                           // regMask
+    }}
+  },
+// F0x[E4,C4,A4,84] - Link 0 Control Register
+// bit [12] IsocEn = 0 default
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_NFCM | AMD_PF_UMA)},         // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x04,                                 // Address
+      0x00000000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+// F0x[E4,C4,A4,84] - Link 0 Control Register
+// bit [12] IsocEn = 1 for Isochronous control flow modes.
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {(AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU)}, // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x04,                                 // Address
+      0x00001000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+// F0x[F0,D0,B0,90] - Link Base Channel Buffer Count
+// bit[31] LockBc = 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      0x10,                                 // Address
+      0x80000000,                           // regData
+      0x80000000,                           // regMask
+    }}
+  },
+// F0x150 - Link Global Retry Control Register
+// bit[18:16] TotalRetryAttempts = 7
+// bit[13] HtRetryCrcDatInsDynEn = 1
+// bit[12]HtRetryCrcCmdPackDynEn = 1
+// bit[11:9] HtRetryCrcDatIns = 4
+// bit[8] HtRetryCrcCmdPack = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
+      0x00073900,                           // regData
+      0x00073F00,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[5:0] T0Time = 0x26
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C026,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[22:17] FullT0Time = 0x33
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                          // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00660000,                           // regData
+      0x007E0000,                           // regMask
+    }}
+  },
+
+// Function 1 - Map Init
+
+// Before reading F1x114_x2 or F1x114_x3 software must initialize
+// the registers or NB Array MCA errors may occur.  BIOS should
+// initialize index 0h of F1x114_x2 and F1x114_x3 to prevent reads
+// from F1x114 from generating NB Array MCA errors.
+// BKDG Doc #3116 Rev 1.07
+
+// F1x110 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
+      0x20000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F1x114 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
+      0x00000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F1x110 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
+      0x30000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F1x114 - Extended Address Map
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
+      0x00000000,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+
+// F2x1B0 - Extended Memory Controller Configuration Low
+// bits[10:8], CohPrefPrbLmt = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0),  // Address
+      0x00000100,                           // regData
+      0x00000700,                           // regMask
+    }}
+  },
+
+// Function 3 - Misc. Control
+// F3x40 - MCA NB Control
+//
+// bit[8], MstrAbrtEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40),  // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F3x44 - MCA NB Configuration
+// bit[30]  SyncOnDramAdrParErrEn = 1
+// bit[27]  NB MCA to CPU0 Enable = 1
+// bit[25]  DisPciCfgCpuErrRsp = 1
+// bit[21]  SyncOnErr = 1
+// bit[20]  SyncOnWDTEn = 1
+// bit[6]   CpuErrDis = 1
+// bit[4]   SyncPktPropDis = 1
+// bit[3]   SyncPktGenDis = 1
+// bit[2]   SyncOnUcEccEn = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44),  // Address
+      0x4A30005C,                           // regData
+      0x4A30005C,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+// ACPI State S1
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0xE6000000,                           // regData
+      0xFFFF0000,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }}
+  },
+// F3x84 - ACPI Power State Control
+// ACPI State S3
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+// ACPI State Throttling
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 2
+// ACPI State S4/S5
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+// ACPI State C1
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 5
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
+      0x01E641E6,                           // regData
+      0xFFFFFFFF,                           // regMask
+    }}
+  },
+// F3x84 - ACPI Power State Control
+// ACPI State C1
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_SINGLE_CORE},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84),  // Address
+      0x80000000,                           // regData
+      0xFF000000,                           // regMask
+    }}
+  },
+// F3x8C - NB Configuration High
+// Errata 373, bits[25] DisFastTprWr = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
+      0x02000000,                           // regData
+      0x02000000,                           // regMask
+    }}
+  },
+// F3x8C - NB Configuration High
+// Must be cleared by BIOS
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platform Features
+    {{
+      PERFORMANCE_L3_CACHE,                 // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C),  // Address
+      0x00000000,                           // regData
+      0x02000000,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00000800,                           // regData
+      0x00003800,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00000200,                           // regData
+      0x00000200,                           // regMask
+    }}
+  },
+// F3xA4 - Reported Temperature Control
+// bits[12:8] PerStepTimeDn = 15
+// bits[7] TmpSlewDnEn = 1
+// bits[6:5] TmpMaxDiffUp = 3
+// bits[4:0] PerStepTimeUp = 15
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4),  // Address
+      0x00000FEF,                           // regData
+      0x00001FFF,                           // regMask
+    }}
+  },
+// F3xD4 - Clock Power Timing Control 0
+// bits[11:8] ClkRampHystSel = 1
+// bits[30:28] NbClkDiv = 1
+// bits[31] NbClkDivApplyAll = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0xC0010F00,                           // regData
+      0xF0030F00,                           // regMask
+    }}
+  },
+// F3xD8 - Clock Power Timing Control 1
+// bits[2:0] VSSlamTime = 6
+// bits[6:4] VSRampTime = 1
+// bits[26:24] ReConDel = 3
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8),  // Address
+      0x03000016,                           // regData
+      0x0F000077,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 6
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00006000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[18:16] CacheFlushOnHaltCtl = 0 to ensure AP cache stability at Early
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_Bx                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00000000,                           // regData
+      0x00070000,                           // regMask
+    }}
+  },
+// F3x180 - NB Extended Configuration
+// bits[1] SyncFloodOnUsPwDataErr = 1
+// bits[5] DisPciCfgCpuMstAbtRsp = 1
+// bits[6] SyncFloodOnDatErr = 1
+// bits[7] SyncFloodOnTgtAbtErr = 1
+// bits[8] SyncOnProtEn = 1
+// bits[9] SyncOnUncNbAryEn = 1
+// bits[20] SyncFloodOnL3LeakErr = 1
+// bits[21] SyncFloodOnCpuLeakErr = 1
+// bits[22] SyncFloodOnTblWalkErr = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x007003E2,                           // regData
+      0x007003E2,                           // regMask
+    }}
+  },
+// F3x188 - NB Extended Configuration Low Register
+// bits[4] EnStpGntOnFlushMaskWakeup = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00000010,                           // regData
+      0x00000010,                           // regMask
+    }}
+  },
+// F3x1A0 - L3 Buffer Count Register
+// bits[14:12]  L3ToSriReqCBC = 4, 4 or fewer cores with L3 cache is 4.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
+      0x00004000,                               // regData
+      0x00007000,                               // regMask
+    }}
+  },
+// F3x1A0 - L3 Buffer Count Register
+// bits[14:12]  L3ToSriReqCBC = 5, 5-core with L3 cache is 5.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
+      0x00005000,                               // regData
+      0x00007000,                               // regMask
+    }}
+  },
+// F3x1A0 - L3 Buffer Count Register
+// bits[14:12]  L3ToSriReqCBC = 6, 6-core with L3 cache is 6.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0),     // Address
+      0x00006000,                               // regData
+      0x00007000,                               // regMask
+    }}
+  },
+// F3x1B8 - L3 Control
+// bits[12] Must be set by BIOS.
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
+      0x00001000,                           // regData
+      0x00001000,                           // regMask
+    }}
+  },
+  // F4x1C4 - L3 Power Control Register
+  // bits[8] L3PwrSavEn = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_L3_CACHE,                 // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F3x1CC - IBS Control
+// bits[8] LvtOffsetVal = 1
+  {
+    PCIREGISTER,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10PciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10PciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
new file mode 100755
index 0000000000..67ef653d23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
@@ -0,0 +1,376 @@
+/**
+ * @file
+ *
+ * AMD Family_10 P-State power check
+ *
+ * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerCheck.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuF10Utilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10PmPwrCheckCore (
+  IN     VOID *ErrorData,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F10PmPwrChkCopyPstate (
+  IN     UINT8 Dest,
+  IN     UINT8 Src,
+  IN     AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the family 10h Processor-
+ * Systemboard Power Delivery Check.
+ *
+ * The steps are as follows:
+ *    1. Starting with P0, loop through all P-states until a passing state is
+ *       found.  A passing state is one in which the current required by the
+ *       CPU is less than the maximum amount of current that the system can
+ *       provide to the CPU.  If P0 is under the limit, no further action is
+ *       necessary.
+ *    2. If at least one P-State is under the limit & at least one P-State is
+ *       over the limit, the BIOS must:
+ *       a. If the processor's current P-State is disabled by the power check,
+ *          then the BIOS must request a transition to an enabled P-state
+ *          using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
+ *          to reflect the new value.
+ *       b. Copy the contents of the enabled P-state MSRs to the highest
+ *          performance P-state locations.
+ *       c. Request a P-state transition to the P-state MSR containing the
+ *          COF/VID values currently applied.
+ *       d. Adjust the following P-state parameters affected by the P-state
+ *          MSR copy by subtracting the number of P-states that are disabled
+ *          by the power check.
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[StcPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *    3. If all P-States are over the limit, the BIOS must:
+ *       a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
+ *          write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
+ *          MSRC001_0063[CurPstate] to reflect the new value.
+ *       b. If F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
+ *          MSR pointed to by F3xDC[PstateMaxVal] to MSRC001_0064 and set
+ *          MSRC001_0064[PstateEn]
+ *       c. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
+ *          [CurPstate] to reflect the new value.
+ *       d. Adjust the following P-state parameters to zero:
+ *          1. F3x64[HtcPstateLimit]
+ *          2. F3x68[StcPstateLimit]
+ *          3. F3xDC[PstateMaxVal]
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT8       DisPsNum;
+  UINT8       PsMaxVal;
+  UINT8       Pstate;
+  UINT32      ProcIddMax;
+  UINT32      PciRegister;
+  UINT32      Socket;
+  UINT32      Module;
+  UINT32      Core;
+  UINT32      AndMask;
+  UINT32      OrMask;
+  UINT32      PstateLimit;
+  PCI_ADDR    PciAddress;
+  UINT64      MsrRegister;
+  AP_TASK     TaskPtr;
+  AGESA_STATUS IgnoredSts;
+  PWRCHK_ERROR_DATA ErrorData;
+
+  // get the socket number
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  ErrorData.SocketNumber = (UINT8)Socket;
+
+  ASSERT (Core == 0);
+
+  // get the Max P-state value
+  for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
+    LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+      break;
+    }
+  }
+
+  ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
+
+  DisPsNum = 0;
+  for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
+    if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
+      if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties.CurrentLimit) {
+        // Add to event log the Pstate that exceeded the current limit
+        PutEventLog (AGESA_WARNING,
+                     CPU_EVENT_PM_PSTATE_OVERCURRENT,
+                     Socket, Pstate, 0, 0, StdHeader);
+        DisPsNum++;
+      } else {
+        break;
+      }
+    }
+  }
+
+  // If all P-state registers are disabled, move P[PsMaxVal] to P0
+  // and transition to P0, then wait for CurPstate = 0
+
+  ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
+
+  // We only need to log this event on the BSC
+  if (ErrorData.AllowablePstateNumber == 0) {
+    PutEventLog (AGESA_FATAL,
+                 CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
+                 Socket, 0, 0, 0, StdHeader);
+  }
+
+  if (DisPsNum != 0) {
+    TaskPtr.FuncAddress.PfApTaskI = F10PmPwrCheckCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
+    TaskPtr.DataTransfer.DataPtr = &ErrorData;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
+
+    // Final Step
+    //    F3x64[HtPstatelimit] -= disPsNum
+    //    F3x68[StcPstateLimit]-= disPsNum
+    //    F3xDC[PstateMaxVal]-= disPsNum
+
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    PciAddress.Address.Function = FUNC_3;
+
+    PciAddress.Address.Register = HTC_REG;
+    AndMask = 0xFFFFFFFF;
+    ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3x64
+    PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
+    if (PstateLimit > DisPsNum) {
+      PstateLimit -= DisPsNum;
+      ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
+
+    PciAddress.Address.Register = STC_REG;
+    AndMask = 0xFFFFFFFF;
+    ((STC_REGISTER *) &AndMask)->StcPstateLimit = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3x68
+    PstateLimit = ((STC_REGISTER *) &PciRegister)->StcPstateLimit;
+    if (PstateLimit > DisPsNum) {
+      PstateLimit -= DisPsNum;
+      ((STC_REGISTER *) &OrMask)->StcPstateLimit = PstateLimit;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
+
+    PciAddress.Address.Register = CPTC2_REG;
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
+    OrMask = 0x00000000;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xDC
+    PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
+    if (PstateLimit > DisPsNum) {
+      PstateLimit -= DisPsNum;
+      ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
+
+    // Now that P0 has changed, recalculate VSSlamTime
+    F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Core-level error handler called if any p-states were determined to be out
+ * of range for the mother board.
+ *
+ * This function implements steps 2a-c and 3a-c on each core.
+ *
+ * @param[in]  ErrorData            Details about the error condition.
+ * @param[in]  StdHeader            Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmPwrCheckCore (
+  IN       VOID *ErrorData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  i;
+  UINT8  PsMaxVal;
+  UINT8  DisPsNum;
+  UINT8  CurrentPs;
+  UINT64 MsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
+  DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
+             ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
+
+  LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
+  CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
+
+  if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
+
+    // Step 1
+    // Transition to Pstate Max if not there already
+
+    if (CurrentPs != PsMaxVal) {
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
+    }
+
+
+    // Step 2
+    // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
+    // to P0.
+
+    if (PsMaxVal != 0) {
+      F10PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+    }
+  } else {
+
+    // move remaining P-state register(s) up
+    // Step 1
+    // Transition to a valid Pstate if current Pstate has been disabled
+
+    if (CurrentPs < DisPsNum) {
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
+      CurrentPs = DisPsNum;
+    }
+
+    // Step 2
+    // Move enabled Pstates up and disable the remainder
+
+    for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
+      F10PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
+    }
+
+    // Step 3
+    // Transition to current COF/VID at shifted location
+
+    CurrentPs = (CurrentPs - DisPsNum);
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
+  }
+  i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
+  if (i == 0) {
+    ++i;
+  }
+  while (i <= PsMaxVal) {
+    FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
+    ++i;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copies the contents of one P-State MSR to another.
+ *
+ * @param[in]  Dest              Destination p-state number
+ * @param[in]  Src               Source p-state number
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+F10PmPwrChkCopyPstate (
+  IN       UINT8 Dest,
+  IN       UINT8 Src,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h
new file mode 100755
index 0000000000..a02e05a056
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerCheck.h
@@ -0,0 +1,81 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_POWER_CHECK_H_
+#define _CPU_F10_POWER_CHECK_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Power Check Error Data
+typedef struct {
+  UINT8 SocketNumber;                 ///< Socket Number
+  UINT8 HwPstateNumber;               ///< Hardware P-state Number
+  UINT8 AllowablePstateNumber;        ///< Allowable P-state Number
+} PWRCHK_ERROR_DATA;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmPwrCheck (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
new file mode 100755
index 0000000000..a3ce49a1cf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
@@ -0,0 +1,516 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Management related stuff
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPUF10POWERMGMT_H_
+#define _CPUF10POWERMGMT_H_
+
+/*
+ * Family 10h CPU Power Management MSR definitions
+ *
+ */
+
+/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */
+#define MSR_INTPEND 0xC0010055
+
+/// Interrupt Pending and CMP-Halt MSR Register
+typedef struct {
+  UINT64 IoMsgAddr:16;               ///< IO message address
+  UINT64 IoMsgData:8;                ///< IO message data
+  UINT64 IntrPndMsgDis:1;            ///< Interrupt pending message disable
+  UINT64 IntrPndMsg:1;               ///< Interrupt pending message
+  UINT64 IoRd:1;                     ///< IO read
+  UINT64 SmiOnCmpHalt:1;             ///< SMI on chip multi-processing halt
+  UINT64 C1eOnCmpHalt:1;             ///< C1E on chip multi-processing halt
+  UINT64 BmStsClrOnHltEn:1;          ///< Clear BM status bit on server C1e entry
+  UINT64 :34;                        ///< Reserved
+} INTPEND_MSR;
+
+
+/* P-state Current Limit Register 0xC0010061 */
+#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
+
+/// Pstate Current Limit MSR Register
+typedef struct {
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 :1;                         ///< Reserved
+  UINT64 PstateMaxVal:3;             ///< Pstate Max Value
+  UINT64 :57;                        ///< Reserved
+} PSTATE_CURLIM_MSR;
+
+
+/* P-state Control Register 0xC0010062 */
+#define MSR_PSTATE_CTL 0xC0010062
+
+/// Pstate Control MSR Register
+typedef struct {
+  UINT64 PstateCmd:3;                ///< Pstate change command
+  UINT64 :61;                        ///< Reserved
+} PSTATE_CTRL_MSR;
+
+
+/* P-state Status Register 0xC0010063 */
+#define MSR_PSTATE_STS 0xC0010063
+
+/// Pstate Status MSR Register
+typedef struct {
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :61;                        ///< Reserved
+} PSTATE_STS_MSR;
+
+
+/* P-state Registers 0xC001006[8:4] */
+#define MSR_PSTATE_0 0xC0010064
+#define MSR_PSTATE_1 0xC0010065
+#define MSR_PSTATE_2 0xC0010066
+#define MSR_PSTATE_3 0xC0010067
+#define MSR_PSTATE_4 0xC0010068
+
+#define PS_REG_BASE MSR_PSTATE_0     /* P-state Register base */
+#define PS_MAX_REG  MSR_PSTATE_4     /* Maximum P-State Register */
+#define PS_MIN_REG  MSR_PSTATE_0     /* Minimum P-State Register */
+#define NM_PS_REG 5                  /* number of P-state MSR registers */
+
+/// Pstate MSR
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid:7;                   ///< CpuVid
+  UINT64 :6;                         ///< Reserved
+  UINT64 NbDid:1;                    ///< NbDid
+  UINT64 :2;                         ///< Reserved
+  UINT64 NbVid:7;                    ///< NbVid
+  UINT64 IddValue:8;                 ///< IddValue
+  UINT64 IddDiv:2;                   ///< IddDiv
+  UINT64 :21;                        ///< Reserved
+  UINT64 PsEnable:1;                 ///< Pstate Enable
+} PSTATE_MSR;
+
+
+/* COFVID Control Register 0xC0010070 */
+#define MSR_COFVID_CTL 0xC0010070
+
+/// COFVID Control MSR Register
+typedef struct {
+  UINT64 CpuFid:6;                   ///< CpuFid
+  UINT64 CpuDid:3;                   ///< CpuDid
+  UINT64 CpuVid:7;                   ///< CpuVid
+  UINT64 PstateId:3;                 ///< Pstate ID
+  UINT64 :3;                         ///< Reserved
+  UINT64 NbDid:1;                    ///< NbDid
+  UINT64 :2;                         ///< Reserved
+  UINT64 NbVid:7;                    ///< NbVid
+  UINT64 :32;                        ///< Reserved
+} COFVID_CTRL_MSR;
+
+
+/* COFVID Status Register 0xC0010071 */
+#define MSR_COFVID_STS 0xC0010071
+
+/// COFVID Status MSR Register
+typedef struct {
+  UINT64 CurCpuFid:6;                ///< Current CpuFid
+  UINT64 CurCpuDid:3;                ///< Current CpuDid
+  UINT64 CurCpuVid:7;                ///< Current CpuVid
+  UINT64 CurPstate:3;                ///< Current Pstate
+  UINT64 :3;                         ///< Reserved
+  UINT64 CurNbDid:1;                 ///< Current NbDid
+  UINT64 :2;                         ///< Reserved
+  UINT64 CurNbVid:7;                 ///< Current NbVid
+  UINT64 StartupPstate:3;            ///< Startup Pstate
+  UINT64 MaxVid:7;                   ///< MaxVid
+  UINT64 MinVid:7;                   ///< MinVid
+  UINT64 MaxCpuCof:6;                ///< MaxCpuCof
+  UINT64 :1;                         ///< Reserved
+  UINT64 CurPstateLimit:3;           ///< Current Pstate Limit
+  UINT64 MaxNbFid:5;                 ///< MaxNbFid
+} COFVID_STS_MSR;
+
+
+/*
+ * Family 10h CPU Power Management PCI definitions
+ *
+ */
+
+/* DRAM Configuration High Register F2x[1,0]94 */
+#define DRAM_CFG_HI_REG0 0x94
+#define DRAM_CFG_HI_REG1 0x194
+
+/// DRAM Configuration High PCI Register
+typedef struct {
+  UINT32 MemClkFreq:3;               ///< Memory clock frequency
+  UINT32 MemClkFreqVal:1;            ///< Memory clock frequency valid
+  UINT32 :4;                         ///< Reserved
+  UINT32 Ddr3Mode:1;                 ///< DDR3 mode
+  UINT32 LegacyBiosMode:1;           ///< Legacy BIOS mode
+  UINT32 ZqcsInterval:2;             ///< ZQ calibration short interval
+  UINT32 RDqsEn:1;                   ///< Read DQS enable
+  UINT32 DisSimulRdWr:1;             ///< Disable simultaneous read and write
+  UINT32 DisDramInterface:1;         ///< Disable the DRAM interface
+  UINT32 PowerDownEn:1;              ///< Power down mode enable
+  UINT32 PowerDownMode:1;            ///< Power down mode
+  UINT32 :1;                         ///< Reserved
+  UINT32 FourRankRDimm:1;            ///< Four rank registered DIMM connected
+  UINT32 DcqArbBypassEn:1;           ///< DRAM controller arbiter bypass enable
+  UINT32 SlowAccessMode:1;           ///< Slow access mode
+  UINT32 FreqChgInProg:1;            ///< Frequency change in progress
+  UINT32 BankSwizzleMode:1;          ///< Bank swizzle mode
+  UINT32 ProcOdtDis:1;               ///< Processor on-die termination disable
+  UINT32 DcqBypassMax:4;             ///< DRAM controller queue bypass maximum
+  UINT32 FourActWindow:4;            ///< Four bank activate window
+} DRAM_CFG_HI_REGISTER;
+
+
+/* Extended Memory Controller Configuration Low Register F2x1B0 */
+#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0
+
+/// Extended Memory Controller Configuration Low PCI Register
+typedef struct {
+  UINT32 AdapPrefMissRatio:2;        ///< Adaptive prefetch miss ratio
+  UINT32 AdapPrefPositiveStep:2;     ///< Adaptive prefetch positive step
+  UINT32 AdapPrefNegativeStep:2;     ///< Adaptive prefetch negative step
+  UINT32 :2;                         ///< Reserved
+  UINT32 CohPrefPrbLmt:3;            ///< Coherent prefetch probe limit
+  UINT32 DisIoCohPref:1;             ///< Disable coherent prefetched for IO
+  UINT32 EnSplitDctLimits:1;         ///< Split DCT write limits enable
+  UINT32 SpecPrefDis:1;              ///< Speculative prefetch disable
+  UINT32 SpecPrefMis:1;              ///< Speculative prefetch predict miss
+  UINT32 SpecPrefThreshold:3;        ///< Speculative prefetch threshold
+  UINT32 :4;                         ///< Reserved
+  UINT32 PrefFourConf:3;             ///< Prefetch four-ahead confidence
+  UINT32 PrefFiveConf:3;             ///< Prefetch five-ahead confidence
+  UINT32 DcqBwThrotWm:4;             ///< Dcq bandwidth throttle watermark
+} EXT_MEMCTRL_CFG_LOW_REGISTER;
+
+
+/* Scrub Rate Control Register F3x58 */
+#define SCRUB_RATE_CTRL_REG 0x58
+
+/// Scrub Rate Control PCI Register
+typedef struct {
+  UINT32 DramScrub:5;                ///< DRAM scrub rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 L2Scrub:5;                  ///< L2 cache scrub rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 DcacheScrub:5;              ///< Data cache scrub rate
+  UINT32 :3;                         ///< Reserved
+  UINT32 L3Scrub:5;                  ///< L3 cache scrub rate
+  UINT32 :3;                         ///< Reserved
+} SCRUB_RATE_CTRL_REGISTER;
+
+/* DRAM Scrub Address Low Register F3x5C */
+#define DRAM_SCRUB_ADDR_LOW_REG 0x5C
+
+/// DRAM Scrub Address Low PCI Register
+typedef struct {
+  UINT32 ScrubReDirEn:1;             ///< DRAM scrubber redirect enable
+  UINT32 :5;                         ///< Reserved
+  UINT32 ScrubAddrLo:26;             ///< DRAM scrubber address bits[31:6]
+} DRAM_SCRUB_ADDR_LOW_REGISTER;
+
+
+/* Hardware thermal control register F3x64 */
+#define HTC_REG 0x64
+
+/// Hardware Thermal Control PCI Register
+typedef struct {
+  UINT32 HtcEn:1;                    ///< HTC Enable
+  UINT32 :3;                         ///< Reserved
+  UINT32 HtcAct:1;                   ///< HTC Active State
+  UINT32 HtcActSts:1;                ///< HTC Active Status
+  UINT32 PslApicHiEn:1;              ///< P-state limit higher APIC int enable
+  UINT32 PslApicLoEn:1;              ///< P-state limit lower APIC int enable
+  UINT32 :8;                         ///< Reserved
+  UINT32 HtcTmpLmt:7;                ///< HTC temperature limit
+  UINT32 HtcSlewSel:1;               ///< HTC slew-controlled temp select
+  UINT32 HtcHystLmt:4;               ///< HTC hysteresis
+  UINT32 HtcPstateLimit:3;           ///< HTC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} HTC_REGISTER;
+
+
+/* Software thermal control register F3x68 */
+#define STC_REG 0x68
+
+/// Software Thermal Control PCI Register
+typedef struct {
+  UINT32 StcSbcTmpHiEn:1;            ///< STC SBC temperature high enable
+  UINT32 StcSbcTmpLoEn:1;            ///< STC SBC temperature low enable
+  UINT32 StcApcTmpHiEn:1;            ///< STC APIC temperature high enable
+  UINT32 StcApcTmpLoEn:1;            ///< STC APIC temperature low enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 StcPstateEn:1;              ///< STC P-state enable
+  UINT32 StcTmpHiSts:1;              ///< STC temperature high status
+  UINT32 StcTmpLoSts:1;              ///< STC temperature low status
+  UINT32 :8;                         ///< Reserved
+  UINT32 StcTmpLmt:7;                ///< STC temperature limit
+  UINT32 StcSlewSel:1;               ///< STC slew-controlled temp select
+  UINT32 StcHystLmt:4;               ///< STC hysteresis
+  UINT32 StcPstateLimit:3;           ///< STC P-state limit select
+  UINT32 :1;                         ///< Reserved
+} STC_REGISTER;
+
+/* ACPI Power State Control Registers F3x84:80 */
+
+/// System Management Action Field (SMAF) Register
+typedef struct {
+  UINT8 CpuPrbEn:1;                  ///< CPU direct probe enable
+  UINT8 NbLowPwrEn:1;                ///< Northbridge low-power enable
+  UINT8 NbGateEn:1;                  ///< Northbridge gate enable
+  UINT8 :1;                          ///< Reserved
+  UINT8 AltVidEn:1;                  ///< alternate VID enable
+  UINT8 ClkDivisor:3;                ///< Clock divisor
+} SMAF_REGISTER;
+
+/// union type for ACPI State SMAF setting
+typedef union {
+  UINT8 SMAFValue;                   ///< SMAF raw value
+  SMAF_REGISTER SMAF;                ///< SMAF structure
+} ACPI_STATE_SMAF;
+
+/// ACPI Power State Control Register F3x80
+typedef struct {
+  ACPI_STATE_SMAF C2;                ///< [7:0]   SMAF Code 000b - C2
+  ACPI_STATE_SMAF C3C1eLinkInit;     ///< [15:8]  SMAF Code 001b - C3, C1e or Link init
+  ACPI_STATE_SMAF FidVidChg;         ///< [23:16] SMAF Code 010b - FIDVID Change
+  ACPI_STATE_SMAF S1;                ///< [31:24] SMAF Code 011b - S1
+} ACPI_PSC_0_REGISTER;
+
+/// ACPI Power State Control Register F3x84
+typedef struct {
+  ACPI_STATE_SMAF S3;                 ///< [7:0]   SMAF Code 100b - S3
+  ACPI_STATE_SMAF Throttling;         ///< [15:8]  SMAF Code 101b - Throttling
+  ACPI_STATE_SMAF S4S5;               ///< [23:16] SMAF Code 110b - S4/S5
+  ACPI_STATE_SMAF C1;                 ///< [31:24] SMAF Code 111b - C1
+} ACPI_PSC_4_REGISTER;
+
+
+/* Power Control Miscellaneous Register F3xA0 */
+#define PW_CTL_MISC_REG 0xA0
+
+/// Power Control Miscellaneous PCI Register
+typedef struct {
+  UINT32 PsiVid:7;                   ///< PSI_L VID threshold
+  UINT32 PsiVidEn:1;                 ///< PSI_L VID enable
+  UINT32 PviMode:1;                  ///< Parallel VID interface mode
+  UINT32 SviHighFreqSel:1;           ///< SVI high frequency select
+  UINT32 IdleExitEn:1;               ///< IDLEEXIT_L Enable
+  UINT32 PllLockTime:3;              ///< PLL synchronization lock time
+  UINT32 BpPinsTriEn:1;              ///< Breakpoint pins tristate enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 PstateId:12;                ///< Pstate ID
+  UINT32 :1;                         ///< Reserved
+  UINT32 SlamVidMode:1;              ///< Slam voltage ID mode
+  UINT32 :1;                         ///< Reserved
+  UINT32 CofVidProg:1;               ///< COF and VID of Pstate programmed
+} POWER_CTRL_MISC_REGISTER;
+
+/* Popup P-state Register F3xA8 */
+#define POPUP_PSTATE_REG 0xA8
+
+/// Popup P-state Register
+typedef struct {
+  UINT32 PopupEn:1;                  ///< Popup enable
+  UINT32 :1;                         ///< Reserved
+  UINT32 PopupPstate:3;              ///< Popup P-state
+  UINT32 PopupCpuVid:7;              ///< Popup core VID
+  UINT32 PopupCpuFid:6;              ///< Popup core FID
+  UINT32 PopupCpuDid:3;              ///< Popup core DID
+  UINT32 :11;                        ///< Reserved
+} POPUP_PSTATE_REGISTER;
+
+/* Clock Power/Timing Control 0 Register F3xD4 */
+#define CPTC0_REG 0xD4
+
+/// Clock Power Timing Control PCI Register
+typedef struct {
+  UINT32 NbFid:5;                    ///< NbFid
+  UINT32 NbFidEn:1;                  ///< NbFidEn
+  UINT32 :2;                         ///< Reserved
+  UINT32 ClkRampHystSel:4;           ///< Clock Ramp Hysteresis Select
+  UINT32 ClkRampHystCtl:1;           ///< Clock Ramp Hysteresis Control
+  UINT32 MTC1eEn:1;                  ///< Message Triggered C1e Enable
+  UINT32 CacheFlushImmOnAllHalt:1;   ///< Cache Flush Immediate on All Halt
+  UINT32 StutterScrubEn:1;           ///< Stutter Mode Scrub Enable
+  UINT32 LnkPllLock:2;               ///< Link PLL Lock
+  UINT32 :2;                         ///< Reserved
+  UINT32 PowerStepDown:4;            ///< Power Step Down
+  UINT32 PowerStepUp:4;              ///< Power Step Up
+  UINT32 NbClkDiv:3;                 ///< NbClkDiv
+  UINT32 NbClkDivApplyAll:1;         ///< NbClkDivApplyAll
+} CLK_PWR_TIMING_CTRL_REGISTER;
+
+
+/* Clock Power/Timing Control 1 Register F3xD8 */
+#define CPTC1_REG 0xD8
+
+/// Clock Power Timing Control 1 PCI Register
+typedef struct {
+  UINT32 VSSlamTime:3;               ///< Voltage stabilization slam time
+  UINT32 :1;                         ///< Reserved
+  UINT32 VSRampTime:3;               ///< Voltage stabilization ramp time
+  UINT32 :1;                         ///< Reserved
+  UINT32 TdpVid:7;                   ///< Thermal design power VID
+  UINT32 :1;                         ///< Reserved
+  UINT32 AltVidStart:7;              ///< Alternate VID start limit
+  UINT32 :1;                         ///< Reserved
+  UINT32 ReConDel:4;                 ///< Link reconnect delay
+  UINT32 PwrPlanes:1;                ///< Power planes
+  UINT32 :3;                         ///< Reserved
+} CLK_PWR_TIMING_CTRL1_REGISTER;
+
+
+/* Clock Power/Timing Control 2 Register F3xDC */
+#define CPTC2_REG 0xDC
+
+/// Clock Power Timing Control 2 PCI Register
+typedef struct {
+  UINT32 AltVid:7;                   ///< Alternate VID
+  UINT32 :1;                         ///< Reserved
+  UINT32 PstateMaxVal:3;             ///< P-state maximum value
+  UINT32 :1;                         ///< Reserved
+  UINT32 NbsynPtrAdj:3;              ///< NB/Core sync FIFO ptr adjust
+  UINT32 :1;                         ///< Reserved
+  UINT32 CacheFlushOnHaltCtl:3;      ///< Cache flush on halt control
+  UINT32 CacheFlushOnHaltTmr:7;      ///< Cache flush on halt timer
+  UINT32 :1;                         ///< Reserved
+  UINT32 SlamTimeMode:2;             ///< Slam time mode
+  UINT32 AltvidVSSlamTime:3;         ///< Altvid voltage stabilization slam time
+} CLK_PWR_TIMING_CTRL2_REGISTER;
+
+
+/* Northbridge Capabilities Register F3xE8 */
+#define NB_CAPS_REG 0xE8
+
+/// Northbridge Capabilities PCI Register
+typedef struct {
+  UINT32 DctDualCap:1;               ///< Two-channel DRAM capable
+  UINT32 DualNodeCap:1;              ///< Dual-node multi-processor capable
+  UINT32 EightNodeCap:1;             ///< Eight-node multi-processor capable
+  UINT32 EccCapable:1;               ///< ECC capable
+  UINT32 ChipkillCapable:1;          ///< Chipkill ECC capable
+  UINT32 DdrMaxRate:3;               ///< Maximum DRAM data rate
+  UINT32 MctCap:1;                   ///< Memory controller capable
+  UINT32 SvmCapable:1;               ///< SVM capable
+  UINT32 HtcCapable:1;               ///< HTC capable
+  UINT32 LnkRtryCap:1;               ///< Link error-retry capable
+  UINT32 CmpCapLo:2;                 ///< CMP capable[1:0]
+  UINT32 MultiVidPlaneCap:1;         ///< Multiple VID plane capable
+  UINT32 CmpCapHi:1;                 ///< CMP capable[2]
+  UINT32 MpCap:3;                    ///< MP capability
+  UINT32 :1;                         ///< Reserved
+  UINT32 UnGangEn:4;                 ///< Link unganging enabled
+  UINT32 :1;                         ///< Reserved
+  UINT32 L3Capable:1;                ///< L3 capable
+  UINT32 HtAcCapable:1;              ///< HT AC capable
+  UINT32 :2;                         ///< Reserved
+  UINT32 MultiNodeCpu:1;             ///< Multinode processor
+  UINT32 IntNodeNum:2;               ///< Internal node number
+} NB_CAPS_REGISTER;
+
+
+/* NB Extended Configuration Low Register F3x188 */
+#define NB_EXT_CFG_LO_REG 0x188
+
+/// Northbridge Extended Configuration Low PCI Register
+typedef struct {
+  UINT32 :4;                         ///< Reserved
+  UINT32 EnStpGntOnFlushMaskWakeup:1; ///< Enable stop grant on flush mask wakeup
+  UINT32 :27;                        ///< Reserved
+} NB_EXT_CFG_LO_REGISTER;
+
+
+/* L3 Cache Parameter Register F3x1C4 */
+#define L3_CACHE_PARAM_REG 0x1C4
+
+/// L3 Cache Parameter PCI Register
+typedef struct {
+  UINT32 L3SubcacheSize0:1;          ///< L3 subcache size 0
+  UINT32 :3;                         ///< Reserved
+  UINT32 L3SubcacheSize1:1;          ///< L3 subcache size 1
+  UINT32 :3;                         ///< Reserved
+  UINT32 L3SubcacheSize2:2;          ///< L3 subcache size 2
+  UINT32 :2;                         ///< Reserved
+  UINT32 L3SubcacheSize3:2;          ///< L3 subcache size 3
+  UINT32 :17;                        ///< Reserved
+  UINT32 L3TagInit:1;                ///< L3 tag initialization
+} L3_CACHE_PARAM_REGISTER;
+
+
+/* Probe Filter Control Register F3x1D4 */
+#define PROBE_FILTER_CTRL_REG 0x1D4
+
+/// Probe Filter Control PCI Register
+typedef struct {
+  UINT32 PFMode:2;                   ///< Probe Filter Mode
+  UINT32 PFWayNum:2;                 ///< Probe Filter way number
+  UINT32 PFSubCacheSize0:2;          ///< Probe filter subcache 0 size
+  UINT32 PFSubCacheSize1:2;          ///< Probe filter subcache 1 size
+  UINT32 PFSubCacheSize2:2;          ///< Probe filter subcache 2 size
+  UINT32 PFSubCacheSize3:2;          ///< Probe filter subcache 3 size
+  UINT32 PFSubCacheEn:4;             ///< Probe filter subcache enable
+  UINT32 :3;                         ///< Reserved
+  UINT32 PFInitDone:1;               ///< Probe filter initialization done
+  UINT32 PFPreferredSORepl:2;        ///< PF preferredSO replacement mode
+  UINT32 PFErrInt:2;                 ///< Probe filter error interrupt type
+  UINT32 PFErrIntLvtOff:4;           ///< Probe filter error interrupt LVT offset
+  UINT32 PFEccError:1;               ///< Probe filter ECC error
+  UINT32 PFLoIndexHashEn:1;          ///< Probe filter low index hash enable
+  UINT32 :2;                         ///< Reserved
+} PROBE_FILTER_CTRL_REGISTER;
+
+
+/* Product Info Register F3x1FC */
+#define PRCT_INFO_REG 0x1FC
+
+/// Product Information PCI Register
+typedef struct {
+  UINT32 NbCofVidUpdate:1;           ///< NbCofVidUpdate
+  UINT32 NbVidUpdateAll:1;           ///< NbVidUpdateAll
+  UINT32 SinglePlaneNbFid:5;         ///< SinglePlaneNbFid
+  UINT32 SinglePlaneNbVid:7;         ///< SinglePlaneNbVid
+  UINT32 DualPlaneNbFidOff:3;        ///< DualPlaneNbFidOff
+  UINT32 DualPlaneNbVidOff:5;        ///< DualPlaneNbVidOff
+  UINT32 SinglePlaneNbIdd:4;         ///< SinglePlaneNbIdd
+} PRODUCT_INFO_REGISTER;
+
+
+#endif /* _CPUF10POWERMGMT_H */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
new file mode 100755
index 0000000000..b697720f4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
@@ -0,0 +1,164 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Management related stuff
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6410 $   @e \$Date: 2008-06-17 06:08:25 -0500 (Tue, 17 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "IdsF10AllService.h"
+#include "cpuPowerMgmtSystemTables.h"
+#include "cpuF10EarlyInit.h"
+#include "cpuF10SoftwareThermal.h"
+#include "cpuF10PowerPlane.h"
+#include "cpuF10PowerCheck.h"
+#include "F10PmNbCofVidInit.h"
+#include "F10PmNbPstateInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10SysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*  Family 10h Only Table */
+/* ---------------------- */
+CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
+{
+  IDS_INITIAL_F10_PM_STEP
+
+  // Step 1 - Configure F3x[84:80].  Handled by PCI register table.
+  // Step 2 - Configure Northbridge COF and VID.
+  //   Execute both cold & warm
+  {
+    0,
+    F10PmNbCofVidInit
+  },
+
+  // Step 3 - Dual-plane Only Support.  Not required by any Arch2008 supported CPU.
+  // Step 4 - Configure Nb-Pstates.
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmNbPstateInit
+  },
+  // Step 5 - Power Plane Initialization
+  //   Execute both cold & warm
+  {
+    0,                                                // ExeFlags
+    F10CpuAmdPmPwrPlaneInit                           // Function Pointer
+  },
+
+  // Step 6 - Pmin Transition After Reset
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmAfterReset                             // Function Pointer
+  },
+
+  // Step 7 - Current Delivery Check
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmPwrCheck                               // Function Pointer
+  },
+
+  // Step x - Software Thermal Control Init
+  //   Execute only after warm reset
+  {
+    PM_EXEFLAGS_WARM_ONLY,                            // ExeFlags
+    F10PmThermalInit                            // Function Pointer
+  },
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate table of steps to perform to initialize the power management
+ *  subsystem.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  SysPmTblPtr              Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10SysPmTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **SysPmTblPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10SysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
+  *SysPmTblPtr = CpuF10SysPmTableArray;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
new file mode 100755
index 0000000000..3ce6d5f4e1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
@@ -0,0 +1,469 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Plane Initialization
+ *
+ * Performs the "BIOS Requirements for Power Plane Initialization" as described
+ * in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "Table.h"
+#include "cpuF10PowerPlane.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Register encodings for F3xD4[PowerStepUp/PowerStepDown]
+CONST UINT16 ROMDATA PowerStepEncodings[16] =
+{
+  400,    // 0000b: 400ns
+  300,    // 0001b: 300ns
+  200,    // 0010b: 200ns
+  100,    // 0011b: 100ns
+  90,     // 0100b: 90ns
+  80,     // 0101b: 80ns
+  70,     // 0110b: 70ns
+  60,     // 0111b: 60ns
+  50,     // 1000b: 50ns
+  45,     // 1001b: 45ns
+  40,     // 1010b: 40ns
+  35,     // 1011b: 35ns
+  30,     // 1100b: 30ns
+  25,     // 1101b: 25ns
+  20,     // 1110b: 20ns
+  15      // 1111b: 15ns
+};
+
+// Register encodings for F3xDC[AltvidVSSlamTime]
+CONST UINT32 ROMDATA AltvidSlamTime[8] =
+{
+  0,    // 000b: <1us
+  10,   // 001b: 10us
+  20,   // 010b: 20us
+  40,   // 011b: 40us
+  50,   // 100b: 50us
+  70,   // 101b: 70us
+  80,   // 110b: 80us
+  90    // 111b: 90us
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10PmPwrPlaneInitPviCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+STATIC
+F10CalculateAltvidVSSlamTimeOnCore (
+  IN       BOOLEAN PviModeFlag,
+  IN       PCI_ADDR *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+F10PmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing power plane initialization.
+ *
+ * The steps are as follows:
+ *    1. If single plane, program lower VID code of CpuVid & NbVid for all
+ *       enabled P-States.
+ *    2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on
+ *       platform requirements.
+ *    3. Configure F3xD4[PowerStepUp & PowerStepDown]
+ *    4. Optionally configure F3xA0[PsiVidEn & PsiVid]
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Service parameters
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10CpuAmdPmPwrPlaneInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  BOOLEAN   PviModeFlag;
+  PCI_ADDR  PciAddress;
+  UINT16    PowerStepTime;
+  UINT32    PowerStepEncoded;
+  UINT32    PciRegister;
+  UINT32    VsSlamTime;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Core;
+  UINT32    NumOfCores;
+  UINT32    LowCore;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT64    MsrRegister;
+  AP_TASK   TaskPtr;
+  AGESA_STATUS  IgnoredSts;
+  PLATFORM_FEATS Features;
+  CPU_LOGICAL_ID LogicalId;
+
+  // Initialize the union
+  Features.PlatformValue = 0;
+  GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  ASSERT (Core == 0);
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+
+  // Set SlamVidMode
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = PW_CTL_MISC_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  AndMask = 0xFFFFFFFF;
+  OrMask = 0x00000000;
+  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
+    PviModeFlag = TRUE;
+    ((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;
+
+    // Have all single plane cores adjust their NB and CPU VID fields
+    TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
+
+  } else {
+    PviModeFlag = FALSE;
+    ((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;
+  }
+  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+  F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
+
+  // Configure PowerStepUp/PowerStepDown
+  PciAddress.Address.Register = CPTC0_REG;
+  if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||
+      (Features.PlatformFeatures.PlatformUma == 1) ||
+      (Features.PlatformFeatures.PlatformUmaIfcm == 1) ||
+      (Features.PlatformFeatures.PlatformIfcm == 1) ||
+      (Features.PlatformFeatures.PlatformIommu == 1)) {
+    PowerStepEncoded = 0x8;
+  } else {
+    GetGivenModuleCoreRange ((UINT32) Socket,
+                             (UINT32) Module,
+                             &LowCore,
+                             &NumOfCores,
+                             StdHeader);
+    NumOfCores = ((NumOfCores - LowCore) + 1);
+    PowerStepTime = (UINT16) (400 / NumOfCores);
+    for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {
+      if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {
+        break;
+      }
+    }
+  }
+  AndMask = 0xFFFFFFFF;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
+  OrMask = 0x00000000;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded;
+  ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded;
+  ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+  if ((LogicalId.Revision & AMD_F10_C3) != 0) {
+    // Set up Pop up P-state register
+    PciAddress.Address.Register = CPTC2_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    AndMask = 0xFFFFFFFF;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0;
+    ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0;
+    OrMask = 0x00000000;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
+    LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
+    ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
+    PciAddress.Address.Register = POPUP_PSTATE_REG;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+    // Set AltVidStart
+    PciAddress.Address.Register = CPTC1_REG;
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
+    OrMask = 0x00000000;
+    ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+    // Set up Altvid slam time
+    PciAddress.Address.Register = CPTC2_REG;
+    VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader);
+    AndMask = 0xFFFFFFFF;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0;
+    OrMask = 0x00000000;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime;
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2;
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+  }
+
+  if (IsWarmReset (StdHeader) && !PviModeFlag) {
+    // Configure PsiVid
+    F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10CpuAmdPmPwrPlaneInit.
+ *
+ * This function implements step 1 on each core.
+ *
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmPwrPlaneInitPviCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddr;
+  UINT32 NbVid;
+  UINT32 CpuVid;
+  UINT64 MsrRegister;
+
+  for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
+    LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
+      NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+      CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+      if (NbVid != CpuVid) {
+        if (NbVid > CpuVid) {
+          NbVid = CpuVid;
+        }
+        ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
+        ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
+        LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the encoded altvid voltage stabilization slam time for the executing
+ * family 10h core.
+ *
+ * This function calculates how much time it will take for the voltage to
+ * stabilize when transitioning from altvid to Pmin, and returns the necessary
+ * encoded value for the amount of time discovered.
+ *
+ * @param[in]  PviModeFlag        Whether or not the platform uses VRMs that
+ *                                employ the parallel VID interface.
+ * @param[in]  PciAddress         Full PCI address of the executing core's config space.
+ * @param[in]  CpuEarlyParams     Service parameters
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ * @retval     Encoded register value.
+ *
+ */
+UINT32
+STATIC
+F10CalculateAltvidVSSlamTimeOnCore (
+  IN       BOOLEAN PviModeFlag,
+  IN       PCI_ADDR *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     NbVid;
+  UINT8     AltVidCode;
+  UINT8     PminVidCode;
+  UINT32    MsrAddr;
+  UINT32    PciRegister;
+  UINT64    MsrRegister;
+  PCI_ADDR  LocalPciAddress;
+
+  // Calculate Slam Time
+  //   VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vpmin - Altvid
+  //   In our case, we will scale the values by 100 to avoid
+  //   decimals.
+
+  // Get Pmin's index
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
+  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+
+  // Get Pmin's VID
+  LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+
+  // If SVI, we only care about CPU VID.
+  // If PVI, determine the higher voltage b/t NB and CPU
+  if (PviModeFlag) {
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    if (PminVidCode > NbVid) {
+      PminVidCode = NbVid;
+    }
+  }
+
+  // Get Alt VID
+  LocalPciAddress.AddressValue = PciAddress->AddressValue;
+  LocalPciAddress.Address.Function = FUNC_3;
+  LocalPciAddress.Address.Register = CPTC2_REG;
+  LibAmdPciRead (AccessWidth32, LocalPciAddress, &PciRegister, StdHeader);
+  AltVidCode = (UINT8) (((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->AltVid);
+
+  return (F10GetSlamTimeEncoding (PminVidCode, AltVidCode, CpuEarlyParams, AltvidSlamTime, StdHeader));
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Sets up PSI_L operation.
+ *
+ * This function implements the LowPowerThreshold parameter.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParams          Contains VrmLowPowerThreshold parameter.
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+F10PmVrmLowPowerModeEnable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Pstate;
+  UINT32    PstateCurrent;
+  UINT32    NextPstateCurrent;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT32    PreviousVID;
+  UINT32    PstateVID;
+  UINT64    PstateMsr;
+  UINT64    PstateLimitMsr;
+  BOOLEAN   EnablePsi;
+  PCI_ADDR  PciAddress;
+
+  if (CpuEarlyParams->PlatformConfig.VrmProperties.LowPowerThreshold != 0) {
+    EnablePsi = FALSE;
+    PreviousVID = 0x7F;           // Initialize to invalid zero volt VID code
+    PstateVID = 0x7F;
+    LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &PstateLimitMsr, StdHeader);
+
+    for (Pstate = 0; Pstate <= (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal; Pstate++) {
+      if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) {
+        LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
+        PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid);
+        if ((Pstate + 1) > (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal) {
+          NextPstateCurrent = 0;
+        } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) {
+          NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties.InrushCurrentLimit + NextPstateCurrent;
+        }
+        if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties.LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties.LowPowerThreshold) && (PstateVID != PreviousVID)) {
+          EnablePsi = TRUE;
+          break;
+        }
+        PreviousVID = PstateVID;
+      }
+    }
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    AndMask = 0xFFFFFFFF;
+    OrMask = 0x00000000;
+    ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0;
+    if (EnablePsi) {
+      ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID;
+      ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1;
+    } else {
+      ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0;
+    }
+    ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h
new file mode 100755
index 0000000000..17c9777742
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10PowerPlane.h
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Power Plane related functions and structures
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_POWER_PLANE_H_
+#define _CPU_F10_POWER_PLANE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10CpuAmdPmPwrPlaneInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_POWER_PLANE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
new file mode 100755
index 0000000000..ef52322d12
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Pstate.c
@@ -0,0 +1,154 @@
+/**
+ * @file
+ *
+ * AMD Family_10 Pstate feature support functions.
+ *
+ * Provides the functions necessary to initialize the Pstate feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 18309 $   @e \$Date: 2009-08-27 15:48:22 +0800 (Thu, 27 Aug 2009) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuPstateTables.h"
+#include "Table.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsPstatePsdDependent (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID         CpuLogicalId;
+  PLATFORM_FEATS         Features;
+
+  // Initialize the union
+  Features.PlatformValue = 0;
+  GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
+  GetPlatformFeatures (&Features, PlatformConfig, StdHeader);
+
+  //
+  // RevC Single link has PSD option, default is dependent.
+  // If multi-link, always return independent.
+  //
+  if ((Features.PlatformFeatures.PlatformSingleLink) && ((CpuLogicalId.Revision & AMD_F10_Cx) != 0)) {
+    if (PlatformConfig->ForcePstateIndependent) {
+      return FALSE;
+    }
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/**
+ *  Family specific call to set core TscFreqSel.
+ *
+ * @param[in]     PstateCpuServices  Pstate CPU services.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10SetTscFreqSel (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64             MsrValue;
+
+  LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader);
+  if (UserOptions.OptionMultisocket) {
+    //
+    // If Agesa need to do p-state leveling on multi-socket, changing the P0
+    // frequency after setting this bit has no effect on the TSC rate.
+    //
+    ASSERT ((MsrValue & BIT24) == 0);
+  }
+  MsrValue = MsrValue | BIT24;
+  LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
+}
+
+CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices =
+{
+  0,
+  F10IsPstatePsdDependent,
+  F10SetTscFreqSel
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
new file mode 100755
index 0000000000..d7e03d4b79
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * AMD Family_10 thermal initialization
+ *
+ * Performs processor thermal initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuF10SoftwareThermal.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *    Main entry point for initializing the Thermal Control
+ *    safety net feature.
+ *
+ *    This must be run by all Family 10h core 0s in the system.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service parameters.
+ * @param[in]  StdHeader               Config handle for library and services.
+ */
+VOID
+F10PmThermalInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32    Core;
+  UINT32    Module;
+  UINT32    PciRegister;
+  UINT32    Socket;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS  IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  ASSERT (Core == 0);
+
+  if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
+      // Enable HTC
+      PciAddress.Address.Register = HTC_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      ((HTC_REGISTER *) &PciRegister)->HtcSlewSel = 0;
+      ((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h
new file mode 100755
index 0000000000..4715f3b95d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * AMD Family_10 thermal initialization related functions and structures
+ *
+ * Performs processor thermal initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_SOFTWARE_THERMAL_H_
+#define _CPU_F10_SOFTWARE_THERMAL_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmThermalInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_SOFTWARE_THERMAL_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
new file mode 100755
index 0000000000..549c59e134
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.c
@@ -0,0 +1,1768 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuF10Utilities.h"
+#include "cpuPostInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+// Register encodings for F3xD8[VSRampTime/VSSlamTime]
+CONST UINT32 ROMDATA VSSlamTime[8] =
+{
+  10,   // 000b: 10us
+  20,   // 001b: 20us
+  30,   // 010b: 30us
+  40,   // 011b: 40us
+  60,   // 100b: 60us
+  100,  // 101b: 100us
+  200,  // 110b: 200us
+  500   // 111b: 500us
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+F10GetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+VOID
+F10GetHtLinkFeatures (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  OUT      UINTN                  *Link,
+  IN       PCI_ADDR               *LinkBase,
+  OUT      HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+BOOLEAN
+F10DoesLinkHaveHtPhyFeats (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR           CapabilitySet,
+  IN       UINT32             Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+  OUT      BOOLEAN            *MatchedSublink1,
+  OUT      HT_FREQUENCIES     *Frequency0,
+  OUT      HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+VOID
+F10SetHtPhyRegister (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  );
+VOID
+F10SetRegisterForHtLinkTokenEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Performs the necessary steps for the 'Software Initiated CPU
+ *  Voltage Transitions.'
+ *
+ *  @param[in]   VidCode       VID code to transition to
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10PmSwVoltageTransition (
+  IN       UINT32 VidCode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    PciRegister;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Ignored;
+  UINT64    MsrRegister;
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = PW_CTL_MISC_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) {
+    LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+    ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode;
+    LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+    F10WaitOutVoltageTransition  (TRUE, StdHeader);
+  } else
+    return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Performs the necessary steps for the 'Software Initiated NB
+ *  Voltage Transitions.'
+ *
+ *  This can only be run by a local core 0.
+ *
+ *  @param[in]   VidCode       VID code to transition to
+ *  @param[in]   SlamMode      Whether voltage is to be slammed, or stepped
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10PmSwVoltageTransitionServerNb (
+  IN       UINT32 VidCode,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Core;
+  UINT32 NbVidStatus;
+  UINT32 Socket;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  UINT32 CoreNum;
+  AP_TASK TaskPtr;
+  AGESA_STATUS IgnoredSts;
+  SW_VOLT_TRANS_NB RemoteInput;
+
+  RemoteInput.VidCode = VidCode;
+  RemoteInput.SlamMode = SlamMode;
+  TaskPtr.FuncAddress.PfApTaskIO = F10SwVoltageTransitionServerNbCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (SW_VOLT_TRANS_NB);
+  TaskPtr.DataTransfer.DataPtr = &RemoteInput;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+
+  IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+
+  do {
+    NbVidStatus = TaskPtr.FuncAddress.PfApTaskIO (&RemoteInput, StdHeader);
+    for (Core = 1; Core < (UINT8) CoreNum; Core++) {
+      NbVidStatus |= ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+    }
+    F10WaitOutVoltageTransition (SlamMode, StdHeader);
+  } while (NbVidStatus != 0);
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns current VsSlamTime in microseconds.
+ *
+ *  @param[out]  VsTimeUsecs   Provides the wait time needed for a Slam Voltage transition.
+ *  @param[in]   SlamMode      Whether voltage is to be slammed, or stepped
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10GetCurrentVsTimeInUsecs (
+     OUT   UINT32  *VsTimeUsecs,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8     RegisterEncoding;
+  UINT32    PciRegister;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    Ignored;
+  CONST UINT16    SlamTimes[8] = {10, 20, 30, 40, 60, 100, 200, 500};
+  PCI_ADDR  PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = CPTC1_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+  if (SlamMode) {
+    RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSSlamTime;
+  } else {
+    RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampTime;
+  }
+
+  *VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Spins until VsSlamTime microseconds have expired.
+ *
+ *  @param[in]   SlamMode      Whether voltage is to be slammed, or stepped
+ *  @param[in]   StdHeader     Header for library and services
+ *
+ */
+VOID
+F10WaitOutVoltageTransition (
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 VsTimeUsecs;
+
+  F10GetCurrentVsTimeInUsecs (&VsTimeUsecs, SlamMode, StdHeader);
+  WaitMicroseconds (VsTimeUsecs, StdHeader);
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Code required to be run on every local core in order to perform
+ *  the steps necessary for 'Software Initiated NB Voltage
+ *  Transitions.'
+ *
+ *  @param[out]  InputData     Family specific data needed to perform a Voltage transition.
+ *  @param[in]   StdHeader     Header for library and services.
+ *
+ *  @retval     zero           All Voltage Transitions are completed.
+ *  @retval     one            There are Voltage transitions remaining to reach target.
+ *
+ */
+UINT32
+F10SwVoltageTransitionServerNbCore (
+  IN       VOID  *InputData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 VidCode;
+  UINT64 MsrRegister;
+
+  if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) {
+    VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode;
+  } else {
+    LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
+    VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid);
+    if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
+      --VidCode;
+    } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
+      ++VidCode;
+    }
+  }
+  LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+  ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode;
+  LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
+
+  if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
+    return 0;
+  } else {
+    return 1;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
+ *
+ * This function determines the largest voltage step that the core will have
+ * to make, calculates how much time it will take for the voltage to stabilize,
+ * and programs the necessary encoded value for the amount of time discovered.
+ *
+ * @param[in]  PciAddress         Segment/bus/device of a module on the socket
+ *                                to program.
+ * @param[in]  CpuEarlyParams     Service parameters
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+F10ProgramVSSlamTimeOnSocket (
+  IN       PCI_ADDR             *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  UINT8    NbVid;
+  UINT8    P0VidCode;
+  UINT8    PminVidCode;
+  UINT32   AndMask;
+  UINT32   MsrAddr;
+  UINT32   OrMask;
+  UINT32   PciRegister;
+  UINT64   MsrRegister;
+  BOOLEAN  IsPviMode;
+  PCI_ADDR LocalPciAddress;
+
+  // Get F3xA0[PviMode]
+  LocalPciAddress.AddressValue = PciAddress->AddressValue;
+  LocalPciAddress.Address.Function = FUNC_3;
+  LocalPciAddress.Address.Register = PW_CTL_MISC_REG;
+  LibAmdPciRead (AccessWidth32, LocalPciAddress, &PciRegister, StdHeader);
+  if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
+    IsPviMode = TRUE;
+  } else {
+    IsPviMode = FALSE;
+  }
+
+  // Get P0's voltage
+  LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader);
+  P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+
+  // If SVI, we only care about CPU VID.
+  // If PVI, determine the higher voltage between NB and CPU
+  if (IsPviMode) {
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    if (P0VidCode > NbVid) {
+      P0VidCode = NbVid;
+    }
+  }
+
+  // Get Pmin's index
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
+  MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
+
+  // Get Pmin's VID
+  LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
+  PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+
+  // If SVI, we only care about CPU VID.
+  // If PVI, determine the higher voltage b/t NB and CPU
+  if (IsPviMode) {
+    NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
+    if (PminVidCode > NbVid) {
+      PminVidCode = NbVid;
+    }
+  }
+
+  // Program F3xD8[VSSlamTime]
+  LocalPciAddress.Address.Register = CPTC1_REG;
+  AndMask = 0xFFFFFFFF;
+  ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->VSSlamTime = 0;
+  OrMask = 0x00000000;
+  ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSSlamTime =
+    F10GetSlamTimeEncoding (P0VidCode, PminVidCode, CpuEarlyParams, VSSlamTime, StdHeader);
+  ModifyCurrentSocketPci (&LocalPciAddress, AndMask, OrMask, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the encoded voltage stabilization slam time for the executing
+ * family 10h core.
+ *
+ * This function looks up the appropriate encoded value for the desired
+ * VID codes.
+ *
+ * @param[in]  HighVoltageVid     VID code of the higher voltage.
+ * @param[in]  LowVoltageVid      VID code of the lower voltage.
+ * @param[in]  CpuEarlyParams     Service parameters
+ * @param[in]  SlamTimeTable      Look-up table of slam times.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ * @retval     Encoded register value.
+ *
+ */
+UINT32
+F10GetSlamTimeEncoding (
+  IN       UINT8  HighVoltageVid,
+  IN       UINT8  LowVoltageVid,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       CONST UINT32 *SlamTimeTable,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 SlamTime;
+  UINT32 EncodedSlamTime;
+  UINT32 VoltageDifference;
+
+  ASSERT (LowVoltageVid >= HighVoltageVid);
+  ASSERT (CpuEarlyParams->PlatformConfig.VrmProperties.SlewRate != 0);
+
+  // Calculate Slam Time
+  //   VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vhigh - Vlow
+  //   In our case, we will scale the values by 100 to avoid
+  //   decimals.
+
+  VoltageDifference = (UINT32) ((LowVoltageVid - HighVoltageVid) * 12500);
+  SlamTime = (VoltageDifference / CpuEarlyParams->PlatformConfig.VrmProperties.SlewRate) + CpuEarlyParams->PlatformConfig.VrmProperties.AdditionalDelay;
+  if (VoltageDifference % CpuEarlyParams->PlatformConfig.VrmProperties.SlewRate) {
+    SlamTime++;
+  }
+
+  // Now round up to nearest register setting
+  for (EncodedSlamTime = 0; EncodedSlamTime < 8; EncodedSlamTime++) {
+    if (SlamTime <= SlamTimeTable[EncodedSlamTime]) {
+      break;
+    }
+  }
+
+  if (EncodedSlamTime > 7) {
+    // The VRMs are too slow for this CPU.  Set to max, and fire an error trap.
+    IDS_ERROR_TRAP;
+    EncodedSlamTime = 7;
+  }
+
+  return (EncodedSlamTime);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Calculates the power in milliWatts of the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_POWER}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              Which P-state to analyze
+ *  @param[out]  PowerInMw                The Power in milliWatts of that P-State
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstatePower (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  CpuVid;
+  UINT32  IddValue;
+  UINT32  IddDiv;
+  UINT32  Socket;
+  UINT32  Module;
+  UINT32  Ignored;
+  BOOLEAN PviFlag;
+  UINT32  V_x10000;
+  UINT32  Power;
+  PCI_ADDR PciAddress;
+  UINT32  TempVar_a;
+  UINT64  MsrRegister;
+  AGESA_STATUS IgnoredSts;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
+  IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
+  IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
+
+  IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = POWER_CTRL_MISCELLANEOUS_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_a, StdHeader);
+  if ((TempVar_a & 0x00000100) != 0) {
+    PviFlag = TRUE;
+  } else {
+    PviFlag = FALSE;
+  }
+  if (PviFlag) {
+    // Set CpuVid value in case CPU is in PVI mode
+    if (CpuVid > 0x5D) {
+      CpuVid = 0x3F;
+    } else if (CpuVid > 0x3E) {
+      CpuVid = CpuVid - 0x1F;
+    } else {
+      CpuVid = (CpuVid >> 1);
+    }
+
+    // PVI Encoding
+    if (CpuVid >= 0x20) {
+      V_x10000 = 7625L - (125L * (CpuVid - 0x20));
+    } else {
+      V_x10000 = 15500L - (250L * CpuVid);
+    }
+  } else {
+    if (CpuVid >= 0x7C) {
+      V_x10000 = 0;
+    } else {
+      V_x10000 = 15500L - (125L * CpuVid);
+    }
+  }
+
+  Power = V_x10000 * IddValue;
+
+  switch (IddDiv) {
+  case 0:
+    *PowerInMw = Power / 10L;
+    break;
+  case 1:
+    *PowerInMw = Power / 100L;
+    break;
+  case 2:
+    *PowerInMw = Power / 1000L;
+    break;
+  default:
+    // IddDiv is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    *PowerInMw = 0;
+    break;
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Calculates the frequency in megahertz of the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The P-State to analyze.
+ *  @param[out]  FrequencyInMHz           The P-State's frequency in MegaHertz
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS   Always Succeeds.
+ */
+AGESA_STATUS
+F10GetPstateFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 TempValue;
+  UINT32 CpuDid;
+  UINT32 CpuFid;
+  UINT64 MsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid);
+  CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid);
+
+  switch (CpuDid) {
+  case 0:
+    TempValue = 1;
+    break;
+  case 1:
+    TempValue = 2;
+    break;
+  case 2:
+    TempValue = 4;
+    break;
+  case 3:
+    TempValue = 8;
+    break;
+  case 4:
+    TempValue  =  16;
+    break;
+  default:
+    // CpuDid is set to an undefined value.  This is due to either a misfused CPU, or
+    // an invalid P-state MSR write.
+    ASSERT (FALSE);
+    TempValue = 1;
+    break;
+  }
+  *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Disables the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The P-State to disable.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
+  LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Transitions the executing core to the desired P-state.
+ *
+ *  @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   StateNumber              The new P-State to make effective.
+ *  @param[in]   WaitForTransition        True if the caller wants the transition completed upon return.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS       Always Succeeds
+ */
+AGESA_STATUS
+F10TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  ASSERT (StateNumber < NM_PS_REG);
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
+  ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
+  LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+  ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
+  LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
+  if (WaitForTransition) {
+    do {
+      LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
+    } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
+  }
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the rate at which the executing core's time stamp counter is
+ *  incrementing.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  FrequencyInMHz           TSC actual frequency.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ *  @return      The most severe status of all called services
+ */
+AGESA_STATUS
+F10GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 Ignored;
+  UINT64 MsrRegister;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
+  if ((MsrRegister & 0x01000000) != 0) {
+    return (FamilySpecificServices->GetPstateFrequency (FamilySpecificServices, 0, FrequencyInMHz, StdHeader));
+  } else {
+    IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
+    return (FamilySpecificServices->GetNbFrequency (FamilySpecificServices, &PciAddress, FrequencyInMHz, &Ignored, StdHeader));
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query
+ *  @param[out]  FrequencyInMHz           Northbridge clock frequency in MHz.
+ *  @param[out]  VoltageInuV              Northbridge voltage in uV.
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      AGESA_UNSUPPORTED   Unknown revs of F10 will return unsupported.
+ */
+AGESA_STATUS
+F10GetNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   UINT32 *FrequencyInMHz,
+     OUT   UINT32 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // This was called by an unknown rev of F10 CPU.
+  return (AGESA_UNSUPPORTED);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Initially launches the desired core to run from the reset vector.
+ *
+ * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   SocketNum                The Processor on which the core is to be launched
+ * @param[in]   ModuleNum                The Module in that processor containing that core
+ * @param[in]   CoreNum                  The Core to launch
+ * @param[in]   PrimaryCoreNum           The id of the module's primary core.
+ * @param[in]   StdHeader                Header for library and services
+ *
+ * @retval      TRUE          The core was launched
+ * @retval      FALSE         The core was previously launched
+ */
+BOOLEAN
+F10LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    NodeRelativeCoreNum;
+  UINT32    PciRegister;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   LaunchFlag;
+  AGESA_STATUS Ignored;
+
+  // Code Start
+  LaunchFlag = FALSE;
+  NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
+  GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored);
+  PciAddress.Address.Function = FUNC_0;
+
+  switch (NodeRelativeCoreNum) {
+  case 0:
+    PciAddress.Address.Register = HT_INIT_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & HT_INIT_CTRL_REQ_DIS) != 0) {
+      PciRegister &= ~HT_INIT_CTRL_REQ_DIS;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 1:
+    PciAddress.Address.Register = HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
+      PciRegister |= HT_TRANS_CTRL_CPU1_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 2:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister,
+                      StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 3:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 4:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU4_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU4_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+  case 5:
+    PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    if ((PciRegister & ECS_HT_TRANS_CTRL_CPU5_EN) == 0) {
+      PciRegister |= ECS_HT_TRANS_CTRL_CPU5_EN;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+      LaunchFlag = TRUE;
+    } else {
+      LaunchFlag = FALSE;
+    }
+    break;
+
+
+  default:
+    break;
+  }
+
+  return (LaunchFlag);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *    This function will return the CpuFid and CpuDid in MHz, using the formula
+ *    described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in]       PStateNumber             P-state number to check.
+ *    @param[in]       Frequency                Leveled target frequency for PStateNumber.
+ *    @param[out]      *CpuFidPtr               New leveled FID.
+ *    @param[out]      *CpuDidPtr1              New leveled DID info 1.
+ *    @param[out]      *CpuDidPtr2              New leveled DID info 2.
+ *    @param[in]       *StdHeader               Header for library and services.
+ *
+ *    @retval       AGESA_WARNING           This P-State does not need to be modified.
+ *    @retval       AGESA_SUCCESS           This P-State must be modified to be level.
+ */
+AGESA_STATUS
+F10GetFrequencyXlatRegInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  PStateNumber,
+  IN       UINT32                 Frequency,
+     OUT   UINT32                 *CpuFidPtr,
+     OUT   UINT32                 *CpuDidPtr1,
+     OUT   UINT32                 *CpuDidPtr2,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 i;
+  UINT32 j;
+  AGESA_STATUS Status;
+  UINT32 FrequencyInMHz;
+
+  FrequencyInMHz = 0;
+  *CpuDidPtr2 = 0xFFFF;
+
+  Status = AGESA_SUCCESS;
+
+  FamilySpecificServices->GetPstateFrequency (FamilySpecificServices, PStateNumber, &FrequencyInMHz, StdHeader);
+  if (FrequencyInMHz == Frequency) {
+    Status |= AGESA_WARNING;
+  }
+
+  // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid)
+  // In this for loop i = 2^CpuDid
+
+
+  for (i = 1; i < 17; (i += i)) {
+    for (j = 0; j < 64; j++) {
+      if (Frequency == ((100 * (j + 0x10)) / i )) {
+        *CpuFidPtr = j;
+        if (i == 1) {
+          *CpuDidPtr1 = 0;
+        } else if (i == 2) {
+          *CpuDidPtr1 = 1;
+        } else if (i == 4) {
+          *CpuDidPtr1 = 2;
+        } else if (i == 8) {
+          *CpuDidPtr1 = 3;
+        } else if (i == 16) {
+          *CpuDidPtr1 = 4;
+        } else {
+          *CpuFidPtr = 0xFFFF;
+          *CpuDidPtr1 = 0xFFFF;
+        }
+        // Success
+        return Status;
+      }
+    }
+  }
+
+  // Error Condition
+  *CpuFidPtr = 0x00FF;
+  *CpuDidPtr1 = 0x00FF;
+  *CpuDidPtr2 = 0x00FF;
+
+  return AGESA_ERROR;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function sets the Pstate MSR to each APs base on Pstate Buffer.
+ *
+ * @CpuServiceMethod{::F_CPU_SET_PSTATE_LEVELING_REG}.
+ *
+ * This function should be called for every core in the system.
+ *
+ * @param[in]       FamilySpecificServices   The current Family Specific Services.
+ * @param[in]       CpuAmdPState             Gathered P-state data structure for whole system.
+ * @param[in]       StdHeader                Config for library and services.
+ *
+ * @retval          AGESA_STATUS    @todo document return *values*.
+ *
+ */
+AGESA_STATUS
+F10PstateLevelingCoreMsrModify (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       S_CPU_AMD_PSTATE   *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32             i;
+  UINT32             Ignored;
+  UINT32             k;
+  UINT32             TempVar_d;
+  UINT32             TempVar_e;
+  UINT32             TempVar_f;
+  UINT64             MsrValue;
+  AGESA_STATUS       Status;
+  UINT32             Socket;
+  UINT32             Module;
+  UINT32             Core;
+  PSTATE_LEVELING    *PStateBufferPtr;
+  PSTATE_LEVELING    *PStateBufferPtrTmp;
+  S_CPU_AMD_PSTATE   *CpuAmdPstatePtr;
+  UINT32             LogicalSocketCount;
+  PCI_ADDR           PciAddress;
+  UINT32             PciRegister;
+
+  Ignored = 0;
+  CpuAmdPstatePtr = (S_CPU_AMD_PSTATE *) CpuAmdPState;
+  PStateBufferPtrTmp = CpuAmdPstatePtr->PStateLevelingStruc;
+  PStateBufferPtr = CpuAmdPstatePtr->PStateLevelingStruc;
+  LogicalSocketCount = CpuAmdPstatePtr->TotalSocketInSystem;
+  PciAddress.AddressValue = 0;
+
+  //
+  //Try to find the Pstate buffer specific to this core(socket).
+  //
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &Status);
+  for (i = 0; i < LogicalSocketCount; i++) {
+    CpuGetPStateLevelStructure (&PStateBufferPtrTmp, CpuAmdPstatePtr, i, StdHeader);
+    if (PStateBufferPtrTmp->SocketNumber == Socket) {
+      break;
+    }
+  }
+
+  if (PStateBufferPtr[0].OnlyOneEnabledPState) {
+    //
+    //If all processors have only 1 enabled P-state, the following sequence should be performed on all cores:
+    //
+
+    //1. Write the appropriate CpuFid value resulting from the matched CPU COF to MSRC001_0064[CpuFid].
+    LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
+    Status = F10GetFrequencyXlatRegInfo (FamilySpecificServices, 0, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader);
+    // Bits 5:0
+    ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d;
+    // Bits 8:6
+    ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e;
+    // Bits 39:32
+    ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue;
+    // Bits 41:40
+    ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv;
+    // Enable the P-State
+    ((PSTATE_MSR *) &MsrValue)->PsEnable = 1;
+    LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
+
+    //2. Copy MSRC001_0064 to MSRC001_0065.
+    LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
+
+    //3. Write 001b to F3xDC[PstatemaxVal].
+    GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Status);
+    PciAddress.Address.Register = CPTC2_REG;
+    PciAddress.Address.Function = FUNC_3;
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = 1;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+    //4. Write 001b to MSRC001_0062[PstateCmd].
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
+
+    //5. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0065[CpuFid].
+    do {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader);
+    } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d);
+
+    //6. Write 000b to MSRC001_0062[PstateCmd].
+    FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
+
+    //7. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0064[CpuFid].
+    do {
+      LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader);
+    } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d);
+
+    //8. Write 0b to MSRC001_0065[PstateEn].
+    LibAmdMsrRead (MSR_PSTATE_1, &MsrValue, StdHeader);
+    ((PSTATE_MSR *) &MsrValue)->PsEnable = 0;
+    LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
+
+    //9. Write 000b to F3xDC[PstateMaxVal] and exit the sequence (no further steps are required).
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+    ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = 0;
+    LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+
+  } else {
+    TempVar_f = MSR_PSTATE_0;
+
+    for (k = 0; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++, TempVar_f++) {
+      // If pState is not disabled then do update
+      LibAmdMsrRead (TempVar_f, &MsrValue, StdHeader);
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable == 1) {
+        Status = F10GetFrequencyXlatRegInfo (FamilySpecificServices, (UINT8) k, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader);
+        if (Status != AGESA_ERROR) {
+          // Bits 5:0
+          ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d;
+          // Bits 8:6
+          ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e;
+        }
+
+        // Bits 39:32
+        ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddValue;
+        // Bits 41:40
+        ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddDiv;
+        // Enable the P-State
+        ((PSTATE_MSR *) &MsrValue)->PsEnable = 1;
+        LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader);
+      } else {
+        // Disable the P-State
+        ((PSTATE_MSR *) &MsrValue)->PsEnable = 0;
+        LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader);
+      }
+    }
+  }
+  return AGESA_SUCCESS;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F10GetPowerStepValueInTime
+ *
+ *  Description:
+ *    Convert power step value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PowerStepPtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+STATIC VOID
+F10GetPowerStepValueInTime (
+  IN OUT   UINT32  *PowerStepPtr
+  )
+{
+  UINT32 TempVar_a;
+
+  TempVar_a = *PowerStepPtr;
+
+  if (TempVar_a < 0x4) {
+    *PowerStepPtr = 400 - (TempVar_a * 100);
+  } else if (TempVar_a <  0x9) {
+    *PowerStepPtr = 130 - (TempVar_a * 10);
+  } else {
+    *PowerStepPtr = 90 - (TempVar_a * 5);
+  }
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  F10GetPllValueInTime
+ *
+ *  Description:
+ *    Convert PLL Value in time
+ *
+ *  Parameters:
+ *    @param[out]     *PllLockTimePtr
+ *
+ *    @retval       VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+STATIC VOID
+F10GetPllValueInTime (
+  IN OUT   UINT32  *PllLockTimePtr
+  )
+{
+  if (*PllLockTimePtr < 4) {
+    *PllLockTimePtr = *PllLockTimePtr + 1;
+  } else if (*PllLockTimePtr == 4) {
+    *PllLockTimePtr = 8;
+  } else if (*PllLockTimePtr == 5) {
+    *PllLockTimePtr = 16;
+  } else
+    *PllLockTimePtr = 0;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get Pstate Transition Latency.
+ *
+ *  @CpuServiceMethod{::F_CPU_PSTATE_TRANSITION_LATENCY}.
+ *
+ *  Calculate TransitionLatency by power step value and pll value.
+ *
+ *  @param[in]     FamilySpecificServices            The current Family Specific Services.
+ *  @param[in]     PStateLevelingBufferStructPtr     Pstate row data buffer pointer
+ *  @param[in]     PciAddress                        Pci address
+ *  @param[out]    TransitionLatency                 The transition latency.
+ *  @param[in]     StdHeader                         Header for library and services
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstateTransLatency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32               TempVar_b;
+  UINT32               TempVar_c;
+  UINT32               TempVar_d;
+  UINT32               TempVar8_a;
+  UINT32               TempVar8_b;
+  UINT32               Ignored;
+  UINT32               k;
+  UINT32               CpuFidSameFlag;
+  UINT8                PStateMaxValueOnCurrentCore;
+  UINT32               TransAndBusMastLatency;
+
+  CpuFidSameFlag = 1;
+
+  F10GetFrequencyXlatRegInfo (
+    FamilySpecificServices,
+    0,
+    PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq,
+    &TempVar_b,
+    &TempVar_c,
+    &Ignored,
+    StdHeader
+    );
+
+  TempVar_d = TempVar_b;
+  PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue;
+
+  //
+  //Check if MSRC001_00[68:64][CpuFid] is the same value for all P-states where
+  //MSRC001_00[68:64][PstateEn]=1
+  //
+  for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) {
+    if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+      F10GetFrequencyXlatRegInfo (
+        FamilySpecificServices,
+        (UINT8) k,
+        PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq,
+        &TempVar_b,
+        &TempVar_c,
+        &Ignored,
+        StdHeader
+        );
+    }
+
+    if (TempVar_d != TempVar_b) {
+      CpuFidSameFlag = 0;
+      break;
+    }
+  }
+
+  PciAddress->Address.Register = 0xD4;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
+
+  // PowerStepDown - Bits 20:23
+  TempVar8_a = (TempVar_d & 0x00F00000) >> 20;
+
+  // PowerStepUp   - Bits 24:27
+  TempVar8_b = (TempVar_d & 0x0F000000) >> 24;
+
+  // Convert the raw numbers in TempVar8_a and TempVar8_b into time
+  F10GetPowerStepValueInTime (&TempVar8_a);
+  F10GetPowerStepValueInTime (&TempVar8_b);
+
+  //
+  //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us
+  //
+  TransAndBusMastLatency =
+  (12 * (TempVar8_a + TempVar8_b) + 999) / 1000;
+
+  if (CpuFidSameFlag == 0) {
+    //
+    //+ F3xA0[PllLockTime]
+    //
+    PciAddress->Address.Register = 0xA0;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
+
+    TempVar8_a = (0x00003800 & TempVar_d) >> 11;
+    F10GetPllValueInTime (&TempVar8_a);
+    TransAndBusMastLatency += TempVar8_a;
+  }
+
+  *TransitionLatency = TransAndBusMastLatency;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate register Informations.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_REGISTER_INFO}.
+ *
+ *    This function will check if PState is Enabled by reading MSR.
+ *    This function also returns the MSR Value, that contains IddValue, IddDiv.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     PState                    Input Pstate number for query.
+ *  @param[out]    PStateEnabled             Boolean flag return pstate enable.
+ *  @param[in,out] IddVal                    Pstate current value.
+ *  @param[in,out] IddDiv                    Pstate current divisor.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstateRegisterInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT64 MsrRegister;
+
+  ASSERT (PState < NM_PS_REG);
+
+  // Read PSTATE MSRs
+  LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
+
+  if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
+    // PState enable = bit 63
+    *PStateEnabled = TRUE;
+  } else {
+    *PStateEnabled = FALSE;
+  }
+
+  // Bits 39:32 (high 32 bits [7:0])
+  *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
+  // Bits 41:40 (high 32 bits [9:8])
+  *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate max state.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PSTATE_MAX_STATE}.
+ *
+ *    This function returns the MaxPStateNumber.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[out]    MaxPStateNumber             Boolean flag return pstate enable.
+ *  @param[in]     StdHeader              Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPstateMaxState (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32              *MaxPStateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT64              MsrValue;
+
+  //
+  // Read PstateMaxVal [6:4] from MSR C001_0061
+  // So, we will know the max pstate state in this socket.
+  //
+  LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
+  *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) & MsrValue)->PstateMaxVal);
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU Specific Platform Type Info.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}.
+ *
+ *    This function returns Returns the platform features.
+ *
+ *  @param[in]     FamilySpecificServices         The current Family Specific Services.
+ *  @param[in,out] Features                       The Features supported by this platform.
+ *  @param[in]     StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ *  @retval      AGESA_SUCCESS Always succeeds.
+ */
+AGESA_STATUS
+F10GetPlatformTypeSpecificInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PLATFORM_FEATS         *Features,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Provide the features of the given HT link.
+ *
+ *  @CpuServiceMethod{::F_GET_HT_LINK_FEATURES}.
+ *
+ * This method is different than the HT Phy Features method, because for the phy registers
+ * sublink 1 matches and should be programmed if the link is ganged but for PCI config
+ * registers sublink 1 is reserved if the link is ganged.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[out]    Link                      The link number, for accessing non-capability set registers.
+ * @param[in]     LinkBase                  The base HT Host capability PCI address for the link.
+ * @param[out]    HtHostFeats               The link's features.
+ * @param[in]     StdHeader                 Standard Head Pointer
+ */
+VOID
+F10GetHtLinkFeatures (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINTN                  *Link,
+  IN       PCI_ADDR               *LinkBase,
+     OUT   HT_HOST_FEATS          *HtHostFeats,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT32    RegValue;
+  UINT32    ExtendedFreq;
+  UINTN     LinkOffset;
+
+  ASSERT (FamilySpecificServices != NULL);
+
+  // No features present unless link is good and connected.
+  HtHostFeats->HtHostValue = 0;
+
+  // Compute link number
+  *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5));
+
+  // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+  PciAddress = *LinkBase;
+  PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+  LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader);
+  if (RegValue  == 3) {
+    HtHostFeats->HtHostFeatures.Coherent = 1;
+  } else if (RegValue == 7) {
+    HtHostFeats->HtHostFeatures.NonCoherent = 1;
+  }
+
+  // If link was not connected, don't check other attributes, make sure
+  // to return zero, no match.
+  if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) {
+    // Check gen3
+    PciAddress = *LinkBase;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+    PciAddress = *LinkBase;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+    RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+    if (RegValue > 6) {
+      HtHostFeats->HtHostFeatures.Ht3 = 1;
+    } else {
+      HtHostFeats->HtHostFeatures.Ht1 = 1;
+    }
+    // Check ganged.
+    LinkOffset = (*Link) * 4;
+    PciAddress = *LinkBase;
+    PciAddress.Address.Function = 0;
+    PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170);
+    LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader);
+    if (RegValue == 0) {
+      HtHostFeats->HtHostFeatures.UnGanged = 1;
+    } else {
+      HtHostFeats->HtHostFeatures.Ganged = 1;
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Checks to see if the HT phy register table entry should be applied
+ *
+ * @CpuServiceMethod{::F_DOES_LINK_HAVE_HTFPY_FEATS}.
+ *
+ * This function determines if the link type field matches the HT link
+ * passed in.
+ *
+ * This method will match for sublink 1 if the link is ganged and sublink 0 matches.
+ *
+ * @param[in]     FamilySpecificServices    The current Family Specific Services.
+ * @param[in]     CapabilitySet    Address of the HT capability block
+ * @param[in]     Link             Zero based HT link to check
+ * @param[in]     HtPhyLinkType    Link type field from a register table entry to compare against
+ * @param[out]    MatchedSublink1  TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
+ * @param[out]    Frequency0       The frequency of sublink0 (200 MHz if not connected).
+ * @param[out]    Frequency1       The frequency of sublink1 (200 MHz if not connected).
+ * @param[in]     StdHeader        Standard Head Pointer
+ *
+ * @retval        TRUE             Link matches
+ * @retval        FALSE            Link does not match
+ *
+ */
+BOOLEAN
+F10DoesLinkHaveHtPhyFeats (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PCI_ADDR           CapabilitySet,
+  IN       UINT32             Link,
+  IN       HT_PHY_LINK_FEATS  *HtPhyLinkType,
+     OUT   BOOLEAN            *MatchedSublink1,
+     OUT   HT_FREQUENCIES     *Frequency0,
+     OUT   HT_FREQUENCIES     *Frequency1,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32    RegValue;
+  UINT32    ExtendedFreq;
+  PCI_ADDR  PciAddress;
+  PCI_ADDR  SubLink1Address;
+  HT_PHY_LINK_FEATS LinkType;
+  BOOLEAN   IsReallyCheckingBoth;
+
+  ASSERT (Link < 4);
+  ASSERT (HtPhyLinkType != NULL);
+  // error checks: No unknown link type bits set and not a "match none"
+  ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0);
+  ASSERT (HtPhyLinkType->HtPhyLinkValue != 0);
+
+  *Frequency0 = 0;
+  *Frequency1 = 0;
+  IsReallyCheckingBoth = FALSE;
+  *MatchedSublink1 = FALSE;
+  LinkType.HtPhyLinkValue = 0;
+
+  // Set the link indicators.  This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4.
+  LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << Link);
+  LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << Link);
+
+  // if ganged, don't read sublink 1, but use sublink 0 to check.
+  SubLink1Address = CapabilitySet;
+
+  // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also,
+  // but only access it if it is also unganged.
+  Link *= 4;
+  PciAddress = CapabilitySet;
+  PciAddress.Address.Function = 0;
+  PciAddress.Address.Register = (Link + 0x170);
+  LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+  RegValue = (RegValue & 0x01);
+  if (RegValue == 0) {
+    // Then really read sublink1, rather than using sublink0
+    SubLink1Address.Address.Function = 4;
+    IsReallyCheckingBoth = TRUE;
+  }
+
+  // Checks for Sublink 0
+
+  // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+  PciAddress = CapabilitySet;
+  PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+  LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+  if ((RegValue & 0x1F) == 3) {
+    LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1;
+  } else if ((RegValue & 0x1F) == 7) {
+    LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1;
+  }
+
+  // If link was not connected, don't check other attributes, make sure
+  // to return zero, no match. (Phy may be powered off.)
+  if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) {
+    // Check gen3
+    PciAddress = CapabilitySet;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+    PciAddress = CapabilitySet;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+    RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+    *Frequency0 = RegValue;
+    if (RegValue > 6) {
+      LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1;
+    } else {
+      LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1;
+    }
+  } else {
+    LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL);
+  }
+
+  // Checks for Sublink 1
+  // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
+  PciAddress = SubLink1Address;
+  PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
+  LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+  if ((RegValue & 0x1F) == 3) {
+    LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1;
+  } else if ((RegValue & 0x1F) == 7) {
+    LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1;
+  }
+
+  if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) {
+    // Check gen3
+    PciAddress = SubLink1Address;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
+    LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
+    PciAddress = SubLink1Address;
+    PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+    RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
+    *Frequency1 = RegValue;
+    if (RegValue > 6) {
+      LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1;
+    } else {
+      LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1;
+    }
+  } else {
+    LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL);
+  }
+
+  // For Deemphasis checking, indicate whether it was actually sublink 1 that matched.
+  // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false.
+  if ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0) {
+    if (IsReallyCheckingBoth &&
+        (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) {
+      *MatchedSublink1 = TRUE;
+    }
+    return TRUE;  // Link matches at least one of the desired characteristics
+  } else {
+    return FALSE; // Link does not match any criteria
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
+ *
+ * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}.
+ *
+ * This function performs the necessary sequence of PCI reads, writes, and waits
+ * necessary to program an HT Phy register.
+ *
+ * @param[in]  FamilySpecificServices    The current Family Specific Services.
+ * @param[in]  HtPhyEntry    HT Phy register table entry to apply
+ * @param[in]  CapabilitySet The link's HT Host base address.
+ * @param[in]  Link          Zero based, node, link number (not package link).
+ * @param[in]  StdHeader     Config handle for library and services
+ *
+ */
+VOID
+F10SetHtPhyRegister (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       HT_PHY_TYPE_ENTRY_DATA  *HtPhyEntry,
+  IN       PCI_ADDR                 CapabilitySet,
+  IN       UINT32                   Link,
+  IN       AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+  UINT32    Temp;
+  UINT32    PhyReg;
+  PCI_ADDR  PhyBase;
+
+  // Determine the PCI config address of the HT Phy portal
+  PhyBase = CapabilitySet;
+  PhyBase.Address.Function = FUNC_4;
+  PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180);
+
+  LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+
+  // Handle direct map registers if needed
+  PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK);
+  if (HtPhyEntry->Address > 0x1FF) {
+    PhyReg |= HTPHY_DIRECT_MAP;
+  }
+
+  PhyReg |= (HtPhyEntry->Address);
+  // Ask the portal to read the HT Phy Register contents
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+
+  // Get the current register contents and do the update requested by the table
+  PhyBase.AddressValue += 4;
+  LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  Temp &= ~(HtPhyEntry->Mask);
+  Temp |= (HtPhyEntry->Data);
+  LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader);
+
+  PhyBase.AddressValue -= 4;
+  // Ask the portal to write our updated value to the HT Phy
+  PhyReg |= HTPHY_WRITE_CMD;
+  LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
+  do
+  {
+    LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
+  } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set the HT Link Token Count registers (F3X1[54,50,4C,48]).
+ *
+ * @TableEntryTypeMethod{::HtTokenPciRegister}.
+ *
+ * Make the current core's PCI address with the function and register for the entry.
+ * For all HT links, check the link's feature set for a match to the entry.
+ * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
+ *
+ * @param[in]     Entry             The Link Token register entry to perform
+ * @param[in]     PlatformConfig    Config handle for platform specific information
+ * @param[in]     StdHeader         Config handle for library and services.
+ *
+ */
+VOID
+F10SetRegisterForHtLinkTokenEntry (
+  IN       TABLE_ENTRY_DATA       *Entry,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                 Link;
+  UINTN                 LinkCount;
+  UINT32                MySocket;
+  UINT32                MyModule;
+  AGESA_STATUS          IgnoredStatus;
+  UINT32                Ignored;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  PCI_ADDR              CapabilitySet;
+  HT_HOST_FEATS         HtHostFeats;
+  PERFORMANCE_PROFILE_FEATS PlatformProfile;
+  UINTN                 ProcessorCount;
+  UINT32                RegisterData;
+  PCI_ADDR              PciAddress;
+
+  // Errors:  Possible values in unused entry space, extra type features, value range checks.
+  // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
+  ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
+          ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
+          (Entry->HtTokenEntry.Mask != 0));
+
+  HtHostFeats.HtHostValue = 0;
+  IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
+  GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
+  GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+  GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
+
+  // Check if the actual processor count is in either range.
+  ProcessorCount = GetNumberOfProcessors (StdHeader);
+  if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->HtTokenEntry.ProcessorCounts.ProcessorCountRanges)) {
+    // Check for any performance profile features.
+    GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
+    if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
+                                        Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) {
+      // Check the link features.
+      LinkCount = 0;
+      while (LinkCount < 4) {
+        if (FindHtHostCapability (LinkCount, &CapabilitySet, StdHeader)) {
+          FamilySpecificServices->GetHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader);
+          if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) {
+            // Do the HT Host PCI register update.
+            PciAddress = CapabilitySet;
+            PciAddress.Address.Function = 3;
+            PciAddress.Address.Register = LINK_TO_XCS_TOKEN_COUNT_REG_3X148 + ((UINT32)Link * 4);
+            LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+            RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask));
+            RegisterData = RegisterData | Entry->HtTokenEntry.Data;
+            LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader);
+          }
+        } else {
+          // No more Capabilities.
+          break;
+        }
+        LinkCount ++;
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.h
new file mode 100755
index 0000000000..4b4a440d59
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Utilities.h
@@ -0,0 +1,223 @@
+/**
+ * @file
+ *
+ * AMD Family_10 specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_UTILITES_H_
+#define _CPU_F10_UTILITES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// The structure for Software Initiated NB Voltage Transitions
+typedef struct {
+  UINT32  VidCode;          ///< VID code to transition to
+  BOOLEAN SlamMode;         ///< Whether voltage is to be slammed, or stepped
+} SW_VOLT_TRANS_NB;
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmSwVoltageTransition (
+  IN       UINT32 VidCode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10PmSwVoltageTransitionServerNb (
+  IN       UINT32 VidCode,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT32
+F10SwVoltageTransitionServerNbCore (
+  IN       VOID  *InputData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10WaitOutVoltageTransition (
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10GetCurrentVsTimeInUsecs (
+     OUT   UINT32 *VsTimeUsecs,
+  IN       BOOLEAN SlamMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+F10ProgramVSSlamTimeOnSocket (
+  IN       PCI_ADDR             *PciAddress,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+UINT32
+F10GetSlamTimeEncoding (
+  IN       UINT8                HighVoltageVid,
+  IN       UINT8                LowVoltageVid,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+  IN       CONST UINT32         *SlamTimeTable,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstatePower (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *PowerInMw,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateFrequency (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10DisablePstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8 StateNumber,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10TransitionPstate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT8              StateNumber,
+  IN       BOOLEAN            WaitForTransition,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10GetTscRate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   UINT32 *FrequencyInMHz,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F10LaunchApCore (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       UINT32 SocketNum,
+  IN       UINT32 ModuleNum,
+  IN       UINT32 CoreNum,
+  IN       UINT32 PrimaryCoreNum,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10GetFrequencyXlatRegInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8  PStateNumber,
+  IN       UINT32 Frequency,
+     OUT   UINT32               *CpuFidPtr,
+     OUT   UINT32               *CpuDidPtr1,
+     OUT   UINT32               *CpuDidPtr2,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+F10PstateLevelingCoreMsrModify (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       S_CPU_AMD_PSTATE   *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateTransLatency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PSTATE_LEVELING        *PStateLevelingBufferStructPtr,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *TransitionLatency,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateRegisterInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT32              PState,
+     OUT   BOOLEAN             *PStateEnabled,
+  IN OUT   UINT32              *IddVal,
+  IN OUT   UINT32              *IddDiv,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPstateMaxState (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+     OUT   UINT32              *MaxPStateNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+F10GetPlatformTypeSpecificInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN OUT   PLATFORM_FEATS         *Features,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif  // _CPU_F10_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
new file mode 100755
index 0000000000..387038152e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
@@ -0,0 +1,124 @@
+/**
+ * @file
+ *
+ * AMD Family_10 WHEA initial Data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6436 $   @e \$Date: 2008-06-18 05:49:23 -0500 (Wed, 18 Jun 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+GetF10WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F10WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AMD_HEST_BANK_INIT_DATA F10HestBankInitData[] = {
+  {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
+  {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
+  {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
+  {0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F},
+  {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
+  {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
+};
+
+AMD_WHEA_INIT_DATA F10WheaInitData = {
+  0x000000000,              // AmdGlobCapInitDataLsd
+  0x000000000,              // AmdGlobCapInitDataMsd
+  0x00000003F,              // AmdGlobCtrlInitDataLsd
+  0x000000000,              // AmdGlobCtrlInitDataMsd
+  0x00,                     // AmdMcbClrStatusOnInit
+  0x02,                     // AmdMcbStatusDataFormat
+  0x00,                     // AmdMcbConfWriteEn
+  (sizeof (F10HestBankInitData) / sizeof (F10HestBankInitData[0])), // HestBankNum
+  &F10HestBankInitData[0]   // Pointer to Initial data of HEST Bank
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the family specific WHEA table properties.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  F10WheaInitDataPtr       Points to the family 10h WHEA properties.
+ *  @param[out]  NumberOfElements         Will be one to indicate one structure.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10WheaInitData (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **F10WheaInitDataPtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = 1;
+  *F10WheaInitDataPtr = &F10WheaInitData;
+}