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author | Paul Menzel <paulepanter@users.sourceforge.net> | 2014-01-25 15:59:31 +0100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-01-07 17:40:45 +0100 |
commit | 2e0d9447db22183e2d3393d84e221e8bb1613d45 (patch) | |
tree | d481c26efa3b5501505f116226d747dd36d730a3 /src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | |
parent | f8532b16bec1743b0528a215c71f67c8845e2a0c (diff) | |
download | coreboot-2e0d9447db22183e2d3393d84e221e8bb1613d45.tar.xz |
src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c')
-rw-r--r-- | src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c index 10f4f5c4f1..87dda2a575 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c @@ -208,7 +208,7 @@ AllocateExecutionCache ( GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader); - // Setup MTTRs for region 0 to region 2 + // Setup MTRRs for region 0 to region 2 VariableMttrBase = AMD_MTRR_VARIABLE_BASE6; for (i = 0; i < 3; i++) { // Exit if no more cache available @@ -265,7 +265,7 @@ AllocateExecutionCache ( if (StartAddr < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region if ((StartAddr + ExeCacheSize) > 0xFFFFF) { ExeCacheSize = 0xFFFFF - StartAddr; AgesaStatus = AGESA_WARNING; @@ -276,7 +276,7 @@ AllocateExecutionCache ( i, StartAddr, ExeCacheSize, 0, StdHeader); } - // Find start and end of MTTR + // Find start and end of MTRR StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7); @@ -290,14 +290,14 @@ AllocateExecutionCache ( } } - // Setup MTTRs + // Setup MTRRs MsrData = WP_IO; for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); } } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) { AgesaStatus = AGESA_ERROR; AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; @@ -373,7 +373,7 @@ AllocateExecutionCache ( } } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); |