Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10 cpus. This code supports the G34 and C32 sockets. Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/95 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
author: efdesign98 <efdesign98@gmail.com> 2011-07-13 16:43:39 -0700
committer: Patrick Georgi <patrick@georgi-clan.de> 2011-07-15 14:17:00 +0200
commit: 229f7cb6d660ad4063c9f65e3fabfff80583f281 (patch)
tree: eaa627ceb717250c38f1bc6ca79868b331d12e23 /src/vendorcode/amd/agesa/f10/Proc/CPU/Feature
parent: 25f23f17bcb2bac9fb5af0f5d6d1d8c1c9ea16ff (diff)
download: coreboot-229f7cb6d660ad4063c9f65e3fabfff80583f281.tar.xz
25 files changed, 8112 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
new file mode 100755
index 0000000000..995f48357c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.c
@@ -0,0 +1,210 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Preserve Registers used for AP Mailbox.
+ *
+ * Save and Restore the normal feature content of the registers being used for
+ * the AP Mailbox.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "GeneralServices.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "PreserveMailbox.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  The contents of the mailbox registers should always be preserved.
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Always TRUE
+ *
+ */
+BOOLEAN
+STATIC
+IsPreserveAroundMailboxEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Save and Restore or Initialize the content of the mailbox registers.
+ *
+ * The registers used for AP mailbox should have the content related to their function
+ * preserved.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+PreserveMailboxes (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;
+  UINT32 Socket;
+  UINT32 Module;
+  PCI_ADDR BaseAddress;
+  PCI_ADDR MailboxRegister;
+  PCI_ADDR *NextRegister;
+  AGESA_STATUS IgnoredStatus;
+  AGESA_STATUS HeapStatus;
+  UINT32 Value;
+  ALLOCATE_HEAP_PARAMS AllocateParams;
+  LOCATE_HEAP_PTR LocateParams;
+  UINT32 RegisterEntryIndex;
+
+  BaseAddress.AddressValue = ILLEGAL_SBDFO;
+
+  if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {
+    AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
+    AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));
+    AllocateParams.Persist = HEAP_SYSTEM_MEM;
+    HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);
+    ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));
+    LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);
+    RegisterEntryIndex = 0;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
+          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+          NextRegister = FamilySpecificServices->RegisterList;
+          while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
+            ASSERT (RegisterEntryIndex <
+                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
+            MailboxRegister = BaseAddress;
+            MailboxRegister.Address.Function = NextRegister->Address.Function;
+            MailboxRegister.Address.Register = NextRegister->Address.Register;
+            LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
+            (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;
+            RegisterEntryIndex++;
+            NextRegister++;
+          }
+        }
+      }
+    }
+  } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {
+    LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
+    HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);
+    ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));
+    RegisterEntryIndex = 0;
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+        if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
+          GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+          NextRegister = FamilySpecificServices->RegisterList;
+          while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
+            ASSERT (RegisterEntryIndex <
+                    (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
+            MailboxRegister = BaseAddress;
+            MailboxRegister.Address.Function = NextRegister->Address.Function;
+            MailboxRegister.Address.Register = NextRegister->Address.Register;
+            if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {
+              Value = 0;
+            } else {
+              Value = (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex];
+            }
+            LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);
+            RegisterEntryIndex++;
+            NextRegister++;
+          }
+        }
+      }
+    }
+    HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox =
+{
+  PreserveAroundMailbox,
+  (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsPreserveAroundMailboxEnabled,
+  PreserveMailboxes
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.h
new file mode 100755
index 0000000000..f23a12da78
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/PreserveMailbox.h
@@ -0,0 +1,87 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Preserve Registers used for AP Mailbox.
+ *
+ * Save and Restore the normal feature content of the registers being used for
+ * the AP Mailbox.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _PRESERVE_MAILBOX_H_
+#define _PRESERVE_MAILBOX_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#define MAX_PRESERVE_REGISTER_ENTRIES 2      ///< There is room on the heap for up to this per node. 
+
+/// Reference to a save buffer.
+typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES];
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Descriptor for family specific save-restore.
+ *
+ * Provide a list of the register offsets to save-restore on each node.  Optionally, zero the
+ * register instead of restoring it.
+ */
+typedef struct  {
+  UINT16          Revision;                        ///< Interface version
+  // Public Data.
+  BOOLEAN   IsZeroOnCold;                          ///< On a cold boot, zero the register instead of restore.
+  PCI_ADDR *RegisterList;                          ///< The list of registers, terminated by ILLEGAL_SBDFO.
+} PRESERVE_MAILBOX_FAMILY_SERVICES;
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _PRESERVE_MAILBOX_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
new file mode 100755
index 0000000000..12c6944f81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.c
@@ -0,0 +1,200 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU C6 feature support code.
+ *
+ * Contains code that declares the AGESA CPU C6 related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "OptionMultiSocket.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableC6OnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should C6 be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 is supported.
+ * @retval       FALSE              C6 cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsC6FeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32             Socket;
+  BOOLEAN            IsEnabled;
+  C6_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->CStateMode == CStateModeC6) {
+    ASSERT (PlatformConfig->CStatePlatformData < 0x10000);
+    ASSERT (PlatformConfig->CStatePlatformData != 0);
+    if ((PlatformConfig->CStatePlatformData != 0) && (PlatformConfig->CStatePlatformData <= 0xFFF8)) {
+      IsEnabled = TRUE;
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (IsProcessorPresent (Socket, StdHeader)) {
+          GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+          if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, StdHeader)) {
+            IsEnabled = FALSE;
+            break;
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the C6 C-state
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeC6Feature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK      TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+  TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+  OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable C6 on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableC6OnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  C6_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeC6 (FamilyServices,
+                                *((UINT64 *) EntryPoint),
+                                &CpuEarlyParams->PlatformConfig,
+                                StdHeader);
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State =
+{
+  C6Cstate,
+  (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsC6FeatureEnabled,
+  InitializeC6Feature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
new file mode 100755
index 0000000000..cbaf3ad8dc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuC6State.h
@@ -0,0 +1,198 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU C6 Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C6 related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_C6_STATE_H_
+#define _CPU_C6_STATE_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _C6_FAMILY_SERVICES C6_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// Defines for CST ACPI Objects
+#define   CST_NAME__            '_'
+#define   CST_NAME_C            'C'
+#define   CST_NAME_S            'S'
+#define   CST_NAME_T            'T'
+#define   CST_LENGTH            (CST_BODY_SIZE - 1)
+#define   CST_NUM_OF_ELEMENTS   0x02
+#define   CST_COUNT             0x01
+#define   CST_PKG_LENGTH        (CST_BODY_SIZE - 5) // CST_BODY_SIZE - PkgHeader - Count Buffer
+#define   CST_PKG_ELEMENTS      0x04
+#define   CST_SUBPKG_LENGTH     0x14
+#define   CST_SUBPKG_ELEMENTS   0x0A
+#define   CST_GDR_LENGTH        0x000C
+#define   CST_C2_TYPE           0x02
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* AML code definition */
+
+/// CST Header
+typedef struct _CST_HEADER_STRUCT {
+  UINT8   NameOpcode;      ///< Name Opcode
+  UINT8   CstName_a__;     ///< String "_"
+  UINT8   CstName_a_C;     ///< String "C"
+  UINT8   CstName_a_S;     ///< String "S"
+  UINT8   CstName_a_T;     ///< String "T"
+} CST_HEADER_STRUCT;
+#define CST_HEADER_SIZE 5
+
+/// CST Body
+typedef struct _CST_BODY_STRUCT {
+  UINT8   PkgOpcode;       ///< Package Opcode
+  UINT8   PkgLength;       ///< Package Length
+  UINT8   PkgElements;     ///< Number of Elements
+  UINT8   Count;           ///< Number of Cstate info packages
+  UINT8   PkgOpcode2;      ///< Package Opcode
+  UINT8   PkgLength2;      ///< Package Length
+  UINT8   PkgElements2;    ///< Number of Elements
+  UINT8   BufferOpcode;    ///< Buffer Opcode
+  UINT8   BufferLength;    ///< Buffer Length
+  UINT8   BufferElements;  ///< Number of Elements
+  UINT8   BufferOpcode2;   ///< Buffer Opcode
+  UINT8   GdrOpcode;       ///< Generic Register Descriptor Opcode
+  UINT16  GdrLength;       ///< Descriptor Length
+  UINT8   AddrSpaceId;     ///< Address Space ID
+  UINT8   RegBitWidth;     ///< Register Bit Width
+  UINT8   RegBitOffset;    ///< Register Bit Offset
+  UINT8   AddressSize;     ///< Address Size
+  UINT64  RegisterAddr;    ///< Register Address
+  UINT16  EndTag;          ///< End Tag Descriptor
+  UINT8   BytePrefix;      ///< Byte Prefix Opcode
+  UINT8   Type;            ///< Type
+  UINT8   BytePrefix2;     ///< Byte Prefix Opcode
+  UINT8   Latency;         ///< Latency
+  UINT8   Power;           ///< Power
+} CST_BODY_STRUCT;
+#define CST_BODY_SIZE 33
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if C6 is supported.
+ *
+ * @param[in]    C6Services         C6 C-state services.
+ * @param[in]    Socket             Zero-based socket number.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               C6 is supported.
+ * @retval       FALSE              C6 is not supported.
+ *
+ */
+typedef BOOLEAN F_C6_IS_SUPPORTED (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT32             Socket,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable C6.
+ *
+ * @param[in]    C6Services         C6 services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_C6_INIT (
+  IN       C6_FAMILY_SERVICES *C6Services,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+typedef UINT32 F_C6_GET_CST_SIZE (
+  IN      VOID
+  );
+
+typedef VOID F_C6_CREATE_CST (
+  IN OUT   VOID              **PstateAcpiBufferPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_C6_INIT *PF_C6_INIT;
+typedef F_C6_GET_CST_SIZE *PF_C6_GET_CST_SIZE;
+typedef F_C6_CREATE_CST   *PF_C6_CREATE_CST;
+
+/**
+ * Provide the interface to the C6 Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _C6_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_C6_IS_SUPPORTED IsC6Supported;                                     ///< Method: Family specific call to check if C6 is supported.
+  PF_C6_INIT InitializeC6;                                              ///< Method: Family specific call to enable C6.
+  PF_C6_GET_CST_SIZE  GetAcpiCstObj;                                    ///< Method: Family specific call to return the size of ACPI CST objects.
+  PF_C6_CREATE_CST    CreateAcpiCstObj;                                 ///< Method: Family specific call to create ACPI CST object
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_C6_STATE_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
new file mode 100755
index 0000000000..48e5a93568
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
@@ -0,0 +1,185 @@
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should cache flush on halt be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               core leveling is supported.
+ * @retval       FALSE              core leveling cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCFOHEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  return (TRUE);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  InitializeCacheFlushOnHaltFeature
+ *
+ *    CPU feature leveling. Enable Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       EntryPoint       Timepoint designator.
+ *    @param[in]       PlatformConfig   Contains the runtime modifiable feature input data.
+ *    @param[in,out]   StdHeader        Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @return          The most severe status of any family specific service.
+ */
+STATIC AGESA_STATUS
+InitializeCacheFlushOnHaltFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32 Socket;
+  UINT32 Module;
+  UINT32 AndMask;
+  UINT32 OrMask;
+  UINT32 PciRegister;
+  PCI_ADDR PciAddress;
+  PCI_ADDR CfohPciAddress;
+  AGESA_STATUS AgesaStatus;
+  CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices;
+
+  ASSERT (IsBsp (StdHeader, &AgesaStatus));
+
+  FamilySpecificServices = NULL;
+  AndMask = 0xFFFFFFFF;
+  OrMask = 0x00000000;
+  PciRegister = 0;
+  AgesaStatus = AGESA_SUCCESS;
+
+  for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+
+      // Get services for the socket
+      GetFeatureServicesOfSocket (&CacheFlushOnHaltFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+      if (FamilySpecificServices != NULL) {
+        FamilySpecificServices->GetCacheFlushOnHaltRegister (FamilySpecificServices, &CfohPciAddress, &AndMask, &OrMask, StdHeader);
+
+        // Get the Or Mask value from IDS
+        IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
+
+        // Set Cache Flush On Halt register
+        for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+          if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+            PciAddress.Address.Function = CfohPciAddress.Address.Function;
+            PciAddress.Address.Register = CfohPciAddress.Address.Register;
+            LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+            PciRegister &= AndMask;
+            PciRegister |= OrMask;
+            LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt =
+{
+  CacheFlushOnHalt,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsCFOHEnabled,
+  InitializeCacheFlushOnHaltFeature
+};
+\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
new file mode 100755
index 0000000000..10f4f5c4f1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c
@@ -0,0 +1,541 @@
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Topology.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuCacheInit.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *             L2 cache Association to Way translation table
+ *----------------------------------------------------------------------------
+ */
+CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] =
+{
+  0,
+  1,
+  2,
+  0xFF,
+  4,
+  0xFF,
+  8,
+  0xFF,
+  16,
+  0xFF,
+  32,
+  48,
+  64,
+  96,
+  128,
+  0xFF,
+};
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+UINT8
+STATIC
+Ceiling (
+  IN UINT32 Divisor,
+  IN UINT32 Dividend
+  );
+
+UINT32
+STATIC
+CalculateOccupyExeCache (
+  IN AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will setup ROM execution cache.
+ *
+ * This function should only be called once.  The execution cache regions are passed
+ * in, the max number of execution cache regions are three.  If the start address of
+ * all three regions are zero, then no execution cache is allocated.
+ *
+ *   -1  available cache size is less than requested, the ROM execution cache
+ *       region is reduced or eliminated.
+ *   -2  at least one execution cache regions across the 1MB line, the ROM execution
+ *       cache size is reduced.
+ *   -3  at least one execution cache regions across the 4GB line, the ROM execution
+ *       cache size is reduced.
+ *   -4  the start address of a region is not at the boundary of cache size
+ *   -5  execution cache start address less than D0000
+ *   -6  more than 2 execution cache regions are above 1MB
+ *
+ * @param[in]   StdHeader          Handle to config for library and services
+ * @param[in]   AmdExeAddrMapPtr   Pointer to the start of EXECUTION_CACHE_REGION array
+ *
+ * @retval      AGESA_SUCCESS      No error
+ * @retval      AGESA_WARNING      AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB;
+ *                                 AGESA_CACHE_REGIONS_ACROSS_4GB;
+ * @retval      AGESA_ERROR        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY;
+ *                                 AGESA_CACHE_START_ADDRESS_LESS_D0000;
+ *                                 AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
+ *
+ * @todo on Tilapia, this routine returns AGESA_ERROR.
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+  IN AMD_CONFIG_PARAMS *StdHeader,
+  IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  )
+{
+  AGESA_STATUS               AgesaStatus;
+  AMD_GET_EXE_SIZE_PARAMS    AmdGetExeSize;
+  UINT64                     MsrData;
+  UINT32                     RemainingExecutionCacheSize;
+  UINT32                     VariableMttrBase;
+  UINT32                     AgesaInfo;
+  UINT32                     StartAddr;
+  UINT32                     ExeCacheSize;
+  UINT32                     StartFixMtrr;
+  UINT32                     CurrentMtrr;
+  UINT32                     EndFixMtrr;
+  UINT32                     CurrentAllocatedExeCacheSize;
+  UINT8                      i;
+  UINT8                      Ignored;
+  UINT64                     OccupyExeCacheStartAddr;
+  UINT64                     OccupExeCacheSize;
+  CACHE_INFO                 *CacheInfoPtr;
+  CPU_SPECIFIC_SERVICES      *FamilySpecificServices;
+
+  //
+  // if start address of all three regions are zero, then the default values are used
+  //
+  if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) {
+    if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) {
+      if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) {
+        // No regions defined by the caller
+        return AGESA_SUCCESS;
+      }
+    }
+  }
+
+  // turn on modification bit
+  LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+  MsrData |= 0x80000;
+  LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+  // get available L2 cache size for ROM execution
+  AmdGetExeSize.StdHeader = *StdHeader;
+  AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize);
+  RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize;
+  CurrentAllocatedExeCacheSize = CalculateOccupyExeCache (StdHeader);
+  if (CurrentAllocatedExeCacheSize >= RemainingExecutionCacheSize) {
+    RemainingExecutionCacheSize = 0;
+  } else {
+    RemainingExecutionCacheSize = RemainingExecutionCacheSize - CurrentAllocatedExeCacheSize;
+  }
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader);
+
+  // Setup MTTRs for region 0 to region 2
+  VariableMttrBase = AMD_MTRR_VARIABLE_BASE6;
+  for (i = 0; i < 3; i++) {
+    // Exit if no more cache available
+    if (RemainingExecutionCacheSize == 0) {
+      break;
+    }
+
+    // Skip the region if ExeCacheSize = 0
+    if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) {
+      continue;
+    }
+
+    // Calculate available execution cache size for region 0 to 2
+    if (RemainingExecutionCacheSize >= AmdExeAddrMapPtr[i].ExeCacheSize) {
+      RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize;
+    } else {
+      AgesaStatus = AGESA_WARNING;
+      AgesaInfo = AGESA_CACHE_SIZE_REDUCED;
+      AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize;
+      RemainingExecutionCacheSize = 0;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+    }
+
+    // Align starting addresses on 32K boundary
+    AmdExeAddrMapPtr[i].ExeCacheStartAddr =
+      AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000;
+
+    // Boundary alignment check mechanism
+    if ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) {
+      AgesaStatus = AGESA_ERROR;
+      AgesaInfo = AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      break;
+    }
+
+    // Check start address
+    if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) {
+      AgesaStatus = AGESA_ERROR;
+      AgesaInfo = AGESA_CACHE_START_ADDRESS_LESS_D0000;
+      PutEventLog (AgesaStatus,
+                   (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                   i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
+      break;
+    }
+
+    StartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
+    ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize;
+
+    ExeCacheSize --;
+
+    if (StartAddr < 0x100000) {
+      // Region below 1MB
+      // Fixed MTTR region
+      if ((StartAddr + ExeCacheSize) > 0xFFFFF) {
+        ExeCacheSize = 0xFFFFF - StartAddr;
+        AgesaStatus = AGESA_WARNING;
+        AgesaInfo = AGESA_CACHE_REGIONS_ACROSS_1MB;
+        AmdExeAddrMapPtr[i].ExeCacheSize = ExeCacheSize + 1;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                     i, StartAddr, ExeCacheSize, 0, StdHeader);
+      }
+
+      // Find start and end of MTTR
+      StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7);
+      EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7);
+
+      //
+      //Check Mtrr before we use it, if Mtrr has been used, we need to add RemainingExecutionCacheSize back.
+      //
+      for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
+        LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader);
+        if (MsrData != 0) {
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000;
+        }
+      }
+
+      // Setup MTTRs
+      MsrData = WP_IO;
+      for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
+        LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader);
+      }
+    } else {
+      // Region above 1MB
+      // Variable MTTR region
+      if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) {
+        AgesaStatus = AGESA_ERROR;
+        AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                     i, StartAddr, ExeCacheSize, 0, StdHeader);
+        continue;
+      }
+      if ((0xFFFFFFFF - StartAddr) < ExeCacheSize) {
+        ExeCacheSize = 0xFFFFFFFF - StartAddr;
+        AgesaStatus = AGESA_WARNING;
+        AgesaInfo = AGESA_CACHE_REGIONS_ACROSS_4GB;
+        AmdExeAddrMapPtr[i].ExeCacheSize = ExeCacheSize + 1;
+        PutEventLog (AgesaStatus,
+                     (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR | (UINT8) AgesaInfo),
+                     i, StartAddr, ExeCacheSize, 0, StdHeader);
+      }
+
+      //
+      //Check Mtrr before we use it.
+      //
+      LibAmdMsrRead (VariableMttrBase, &MsrData, StdHeader);
+      if (MsrData != 0) {
+
+        //
+        //Check expanded
+        //
+        OccupyExeCacheStartAddr = MsrData & (0xFFFF8000);
+        LibAmdMsrRead ((VariableMttrBase + 1), &MsrData, StdHeader);
+        OccupExeCacheSize = (~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000;
+
+        //
+        //Region below || Region above
+        //
+        if ( ((StartAddr + ExeCacheSize + 1) <= OccupyExeCacheStartAddr) ||
+             (StartAddr >= (OccupyExeCacheStartAddr + OccupExeCacheSize)) ) {
+          //
+          //Not overlap the original one, but it need to re-process and set an pair of empty Mtrr
+          //
+          VariableMttrBase += 2;
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + AmdExeAddrMapPtr[i].ExeCacheSize;
+          //
+          //Resume loop count
+          //
+          i--;
+          continue;
+        } else if (OccupyExeCacheStartAddr == StartAddr) {
+
+          //
+          //Overlap with same start address
+          //
+          if (OccupExeCacheSize > (ExeCacheSize + 1)) {
+            //AgesaInfo = AGESA_DEALLOCATE_CACHE_REGIONS;
+            break;
+          }
+          RemainingExecutionCacheSize = RemainingExecutionCacheSize + (UINT32)OccupExeCacheSize;
+        } else {
+          //
+          //Overlap with different start address
+          //
+          //AgesaInfo = AGESA_DEALLOCATE_CACHE_REGIONS;
+          break;
+        }
+      }
+
+      MsrData = (UINT64) (StartAddr | (WP_IO & 0xFull));
+
+      LibAmdMsrWrite (VariableMttrBase, &MsrData, StdHeader);
+      MsrData = (UINT64) ( 0xFFFFFFFF00000000ull | ((0xFFFFFFFFull - ExeCacheSize) | 0x800ull));
+      MsrData &= CacheInfoPtr->VariableMtrrMask;
+      LibAmdMsrWrite ((VariableMttrBase + 1), &MsrData, StdHeader);
+      VariableMttrBase += 2;
+    }
+  }
+
+  // Turn on MTTR enable bit and turn off modification bit
+  LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+  MsrData &= 0xFFFFFFFFFFF7FFFFull;
+  LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function calculates available L2 cache space for ROM execution.
+ *
+ * @param[in]   AmdGetExeSizeParams  Pointer to the start of AmdGetExeSizeParamsPtr structure
+ *
+ * @retval      AGESA_SUCCESS      No error
+ * @retval      AGESA_ALERT        No cache available for execution cache.
+ *
+ */
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  )
+{
+  UINT8     WayUsedForCar;
+  UINT8     L2Assoc;
+  UINT32    L2Size;
+  UINT32    L2WaySize;
+  UINT32    CurrentCoreNum;
+  UINT8     L2Ways;
+  UINT8     Ignored;
+  UINT32    DieNumber;
+  UINT32    TotalCores;
+  CPUID_DATA  CpuIdDataStruct;
+  CACHE_INFO  *CacheInfoPtr;
+  AP_MAIL_INFO ApMailboxInfo;
+  AGESA_STATUS IgnoredStatus;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
+
+  // Check for L2 cache size and way size
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader);
+  L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F);
+
+  // get L2Ways from L2 Association to Way translation table
+  L2Ways = L2AssocToL2WayTranslationTable[L2Assoc];
+  ASSERT (L2Ways != 0xFF);
+
+  // get L2Size
+  L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF);
+
+  // get each L2WaySize
+  L2WaySize = L2Size / L2Ways;
+
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
+
+  // Determine the size for execution cache
+  if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) {
+    // BSC (Boot Strap Core)
+    WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) +
+                    Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
+                    Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                    Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+  } else {
+    // AP (Application Processor)
+    GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader);
+
+    GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader);
+    DieNumber = (1 << ApMailboxInfo.Fields.ModuleType);
+    GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader);
+    ASSERT ((TotalCores % DieNumber) == 0);
+    if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) {
+      WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) +
+                      Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
+                      Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                      Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+    } else {
+      WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) +
+                      Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
+                      Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
+    }
+  }
+
+  ASSERT (WayUsedForCar < L2Ways);
+
+  if (WayUsedForCar < L2Ways) {
+    AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar);
+    return AGESA_SUCCESS;
+  } else {
+    AmdGetExeSizeParams->AvailableExeCacheSize = 0;
+    return AGESA_ALERT;
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function rounds a quotient up if the remainder is not zero.
+ *
+ * @param[in]   Divisor            The divisor
+ * @param[in]   Dividend           The dividend
+ *
+ * @retval      Value              Rounded quotient
+ *
+ */
+UINT8
+STATIC
+Ceiling (
+  IN UINT32 Divisor,
+  IN UINT32 Dividend
+  )
+{
+  if ((Divisor % Dividend) == 0) {
+    return (UINT8) (Divisor / Dividend);
+  } else {
+    return (UINT8) ((Divisor / Dividend) + 1);
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function calculates the amount of cache that has already been allocated on the
+ * executing core.
+ *
+ * @param[in]   StdHeader       Handle to config for library and services
+ *
+ * @retval      Value              Allocated size in bytes
+ *
+ */
+UINT32
+STATIC
+CalculateOccupyExeCache (
+  IN AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64                     OccupExeCacheSize;
+  UINT64                     MsrData;
+  UINT8                      i;
+
+  MsrData = 0;
+  OccupExeCacheSize = 0;
+
+  //
+  //Calculate Variable MTRR base 6~7
+  //
+  for (i = 0; i < 2; i++) {
+    LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader);
+    if (MsrData != 0) {
+      LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader);
+      OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000);
+    }
+  }
+
+  //
+  //Calculate Fixed MTRR base D0000~F8000
+  //
+  for (i = 0; i < 6; i++) {
+    LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader);
+    if (MsrData!= 0) {
+      OccupExeCacheSize = OccupExeCacheSize + 0x8000;
+    }
+  }
+
+  return (UINT32)OccupExeCacheSize;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
new file mode 100755
index 0000000000..c4f51b7db7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_CACHE_INIT_H_
+#define _CPU_CACHE_INIT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define AMD_MTRR_FIX4K_BASE     0x268
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_VARIABLE_BASE7 0x20E
+
+#define WP_IO 0x0505050505050505ull
+
+#define AGESA_CACHE_SIZE_REDUCED              1
+#define AGESA_CACHE_REGIONS_ACROSS_1MB        2
+#define AGESA_CACHE_REGIONS_ACROSS_4GB        3
+#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY  4
+#define AGESA_CACHE_START_ADDRESS_LESS_D0000  5
+#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB   6
+#define AGESA_DEALLOCATE_CACHE_REGIONS        7
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Cache Information
+typedef struct {
+  IN       UINT32  BspStackSize;              ///< Stack size of BSP
+  IN       UINT32  Core0StackSize;            ///< Stack size of primary cores
+  IN       UINT32  Core1StackSize;            ///< Stack size of all non primary cores
+  IN       UINT32  MemTrainingBufferSize;     ///< Memory training buffer size
+  IN       UINT32  SharedMemSize;             ///< Shared memory size
+  IN       UINT64  VariableMtrrMask;          ///< Mask to apply before variable MTRR writes
+} CACHE_INFO;
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+  IN AMD_CONFIG_PARAMS *StdHeader,
+  IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+  );
+
+#endif  // _CPU_CACHE_INIT_H_
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
new file mode 100755
index 0000000000..bdb26abce7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCoreLeveling.c
@@ -0,0 +1,283 @@
+/**
+ * @file
+ *
+ * AMD CPU Core Leveling Function.
+ *
+ * Contains code to Level the number of core in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "AMD.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuEarlyInit.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should core leveling be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               core leveling is supported.
+ * @retval       FALSE              core leveling cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsCoreLevelingEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  CORE_LEVELING_TYPE  CoreLevelMode;
+
+  CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
+  if (CoreLevelMode != CORE_LEVEL_NONE) {
+    return (TRUE);
+  } else {
+    return (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Performs core leveling for the system.
+ *
+ * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter.
+ * The possible modes are:
+ *    -1    CORE_LEVEL_LOWEST            Level to lowest common denominator
+ *    -2    CORE_LEVEL_TWO               Level to 2 cores
+ *    -3    CORE_LEVEL_POWER_OF_TWO      Level to 1,2,4 or 8
+ *    -4    CORE_LEVEL_NONE              Do no leveling
+ *
+ * @param[in]  EntryPoint        Timepoint designator.
+ * @param[in]  PlatformConfig    Contains the leveling mode parameter
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+STATIC AGESA_STATUS
+CoreLevelingAtEarly (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    NumberOfSockets;
+  UINT32    NumberOfModules;
+  UINT32    MinCoreCountOnNode;
+  UINT32    MaxCoreCountOnNode;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    LeveledCores;
+  UINT32    RequestedCores;
+  UINT32    TotalEnabledCoresOnNode;
+  AP_MAIL_INFO ApMailboxInfo;
+  CORE_LEVELING_TYPE  CoreLevelMode;
+  CPU_CORE_LEVELING_FAMILY_SERVICES  *FamilySpecificServices;
+
+  MaxCoreCountOnNode = 0;
+  MinCoreCountOnNode = 0xFFFFFFFF;
+  LeveledCores = 0;
+
+  ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax);
+
+  // Get OEM IO core level mode
+  CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
+
+  // Get socket count
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  GetApMailbox (&ApMailboxInfo.Info, StdHeader);
+  NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1;
+
+  // Collect cpu core info
+  // Get the highest and lowest core count in all nodes
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      for (Module = 0; Module < NumberOfModules; Module++) {
+        if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
+          TotalEnabledCoresOnNode = HighCore - LowCore + 1;
+          if (TotalEnabledCoresOnNode < MinCoreCountOnNode) {
+            MinCoreCountOnNode = TotalEnabledCoresOnNode;
+          }
+          if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) {
+            MaxCoreCountOnNode = TotalEnabledCoresOnNode;
+          }
+        }
+      }
+    }
+  }
+
+  // Get LeveledCores
+  switch (CoreLevelMode) {
+  case CORE_LEVEL_LOWEST:
+    if (MinCoreCountOnNode == MaxCoreCountOnNode) {
+      return (AGESA_SUCCESS);
+    }
+    LeveledCores = MinCoreCountOnNode;
+    break;
+  case CORE_LEVEL_TWO:
+    LeveledCores = 2 / NumberOfModules;
+    if (LeveledCores != 0) {
+      LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
+    } else {
+      return (AGESA_WARNING);
+    }
+    if ((LeveledCores * NumberOfModules) != 2) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      2, (LeveledCores * NumberOfModules), 0, 0, StdHeader
+      );
+    }
+    break;
+  case CORE_LEVEL_POWER_OF_TWO:
+    // Level to power of 2 (1, 2, 4, 8...)
+    LeveledCores = 1;
+    while (MinCoreCountOnNode >= (LeveledCores * 2)) {
+      LeveledCores = LeveledCores * 2;
+    }
+    break;
+  case CORE_LEVEL_ONE:
+    LeveledCores = 1;
+    break;
+  case CORE_LEVEL_THREE:
+  case CORE_LEVEL_FOUR:
+  case CORE_LEVEL_FIVE:
+  case CORE_LEVEL_SIX:
+  case CORE_LEVEL_SEVEN:
+  case CORE_LEVEL_EIGHT:
+  case CORE_LEVEL_NINE:
+  case CORE_LEVEL_TEN:
+  case CORE_LEVEL_ELEVEN:
+  case CORE_LEVEL_TWELVE:
+  case CORE_LEVEL_THIRTEEN:
+  case CORE_LEVEL_FOURTEEN:
+  case CORE_LEVEL_FIFTEEN:
+    RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3;
+    LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules;
+    LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
+    if ((LeveledCores * NumberOfModules) != RequestedCores) {
+      PutEventLog (
+      AGESA_WARNING,
+      CPU_WARNING_ADJUSTED_LEVELING_MODE,
+      RequestedCores, (LeveledCores * NumberOfModules), 0, 0, StdHeader
+      );
+    }
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+
+  // Set down core register
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, (CONST VOID **)&FamilySpecificServices, StdHeader);
+      if (FamilySpecificServices != NULL) {
+        for (Module = 0; Module < NumberOfModules; Module++) {
+          FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, StdHeader);
+        }
+      }
+    }
+  }
+
+  return (AGESA_SUCCESS);
+}
+
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
+{
+  CoreLeveling,
+  (CPU_FEAT_AFTER_PM_INIT),
+  IsCoreLevelingEnabled,
+  CoreLevelingAtEarly
+};
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L      F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
new file mode 100755
index 0000000000..9e7ea86ec0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuDmi.c
@@ -0,0 +1,694 @@
+/**
+ * @file
+ *
+ * AMD DMI Record Creation API, and related functions.
+ *
+ * Contains code that produce the DMI related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionDmi.h"
+#include "cpuLateInit.h"
+#include "cpuServices.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_DMI_CONFIGURATION    OptionDmiConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT16
+STATIC
+AdjustGranularity (
+  IN UINT32 *CacheSizePtr
+  );
+
+VOID
+STATIC
+IntToString (
+  IN OUT   CHAR8 *String,
+  IN       UINT8 *Integer,
+  IN       UINT8 SizeInByte
+);
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetDmiInfoStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  );
+AGESA_STATUS
+GetDmiInfoMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  );
+AGESA_STATUS
+ReleaseDmiBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+AGESA_STATUS
+ReleaseDmiBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CreateDmiRecords
+ *
+ *  Description:
+ *     This function creates DMI/SMBios records pertinent to the processor
+ *     SMBIOS type 4, type 7, and type 40.
+ *
+ *  Parameters:
+ *    @param[in, out]  *StdHeader
+ *    @param[in, out]  **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+
+AGESA_STATUS
+CreateDmiRecords (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader);
+  return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  GetDmiInfoStub
+ *
+ *  Description:
+ *     This is the default routine for use when the DMI option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *    @param[in, out]    **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+GetDmiInfoStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  GetDmiInfoMain
+ *
+ *  Description:
+ *     This is the common routine for getting Dmi type4 and type7 CPU related information.
+ *
+ *  Parameters:
+ *    @param[in, out]  *StdHeader
+ *    @param[in, out]  **DmiTable
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+GetDmiInfoMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   DMI_INFO              **DmiTable
+  )
+{
+  UINT8  Socket;
+  UINT8  Channel;
+  UINT8  Dimm;
+  UINT16 DimmIndex;
+  UINT16 NumberOfDimm;
+  UINT32 PciData;
+  UINT64 MsrData;
+  UINT64 MsrRegister;
+  PCI_ADDR PciAddress;
+  AGESA_STATUS Flag;
+  AGESA_STATUS CalledStatus;
+  AP_EXE_PARAMS ApParams;
+  MEM_DMI_INFO *MemInfo;
+  DMI_T17_MEMORY_TYPE MemType;
+  DMI_INFO *DmiBufferPtr;
+  ALLOCATE_HEAP_PARAMS AllocateHeapParams;
+  LOCATE_HEAP_PTR LocateHeapParams;
+
+  MsrData = 0;
+  Flag = TRUE;
+  DmiBufferPtr = *DmiTable;
+  if (DmiBufferPtr == NULL) {
+    //
+    // Allocate a buffer by heap function
+    //
+    AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE;
+    AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO);
+    AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
+
+    if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+
+    DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr;
+    *DmiTable = DmiBufferPtr;
+  }
+  // Fill with 0x00
+  LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader);
+
+  //
+  // Get CPU information
+  //
+
+  // Run GetType4Type7Info on all core0s.
+  ApParams.StdHeader = *StdHeader;
+  ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7;
+  ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr;
+  ApParams.RelatedBlockLength = sizeof (DMI_INFO);
+  CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader);
+  if (CalledStatus > Flag) {
+    Flag = CalledStatus;
+  }
+  CalledStatus = GetType4Type7Info (&ApParams);
+  if (CalledStatus > Flag) {
+    Flag = CalledStatus;
+  }
+
+  //------------------------------
+  // T Y P E 16 17 19 20
+  //------------------------------
+
+  LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    if (Flag < AGESA_ERROR) {
+      Flag = AGESA_ERROR;
+    }
+  } else {
+    NumberOfDimm = *((UINT16 *) (LocateHeapParams.BufferPtr));
+    MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2));
+    MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
+    // TYPE 16
+    DmiBufferPtr->T16.Location = 0x03;
+    DmiBufferPtr->T16.Use = 0x03;
+    PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90);
+    LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    if (PciData == 0) {
+      PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x190);
+      LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
+    }
+    if ((PciData & 0x00080000) != 0) {
+      DmiBufferPtr->T16.MemoryErrorCorrection = 0x04;
+    } else {
+      DmiBufferPtr->T16.MemoryErrorCorrection = 0x03;
+    }
+
+    LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader);
+    if (MsrData == 0) {
+      LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader);
+      DmiBufferPtr->T16.MaximumCapacity = (UINT32) (MsrData >> 10);
+    } else {
+      DmiBufferPtr->T16.MaximumCapacity = (UINT32) (MsrData >> 10);
+    }
+
+    DmiBufferPtr->T16.NumberOfMemoryDevices = NumberOfDimm;
+
+    // TYPE 17
+    for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) {
+      Socket = (MemInfo + DimmIndex)->Socket;
+      Channel = (MemInfo + DimmIndex)->Channel;
+      Dimm = (MemInfo + DimmIndex)->Dimm;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' ';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0';
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' ';
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0';
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1;
+      DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode;
+
+      IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2);
+
+      LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader);
+      DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0;
+
+      DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes;
+
+      //TYPE 20
+      DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = 0;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF;
+      DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF;
+    }
+
+    // TYPE 19
+    DmiBufferPtr->T19.StartingAddr = 0;
+
+    LibAmdMsrRead (TOP_MEM2, &MsrRegister, StdHeader);
+    if (MsrRegister == 0) {
+      LibAmdMsrRead (TOP_MEM, &MsrRegister, StdHeader);
+      DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
+    } else if (MsrRegister != 0) {
+      DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
+    }
+
+    DmiBufferPtr->T19.PartitionWidth = 0xFF;
+  }
+  return (Flag);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  GetType4Type7Info
+ *
+ *  Description:
+ *    This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables.
+ *
+ *  Parameters:
+ *    @param[in] ApExeParams   Handle to config for library and services.
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *  Processing:
+ *
+ */
+AGESA_STATUS
+GetType4Type7Info (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT8  CpuStepping;
+  UINT16 Index;
+  UINT32 SocketNum;
+  UINT32 CacheSize;
+  UINT32 IgnoredModule;
+  UINT32 IgnoredCore;
+  DMI_INFO *DmiBufferPtr;
+  AGESA_STATUS IgnoredSts;
+  AGESA_STATUS Flag;
+  BOOLEAN FamilyNotFound;
+  CPUID_DATA CpuId;
+  CPU_TYPE_INFO CpuInfo;
+  PROC_FAMILY_TABLE   *ProcData;
+  CPU_LOGICAL_ID LogicalID;
+
+  Flag = TRUE;
+  DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock;
+  GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);
+
+  ProcData = NULL;
+  FamilyNotFound = TRUE;
+  for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) {
+    ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]);
+    if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) {
+      FamilyNotFound = FALSE;
+      break;
+    }
+  }
+
+  if (FamilyNotFound) {
+    return AGESA_ERROR;
+  }
+
+  ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader);
+
+  // ------------------------------
+  // T Y P E 4
+  // ------------------------------
+
+  IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts);
+
+  // Type 4 Offset 0x05, Processor Type
+  DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR;
+
+  // Type 4 Offset 0x06, Processor Family
+  for (Index = 0; Index < ProcData->LenBrandList; Index++) {
+    if ((ProcData->DmiBrandList[Index].PackageType == 'x' || ProcData->DmiBrandList[Index].PackageType == CpuInfo.PackageType) &&
+        (ProcData->DmiBrandList[Index].PgOfBrandId == 'x' || ProcData->DmiBrandList[Index].PgOfBrandId == CpuInfo.BrandId.Pg) &&
+        (ProcData->DmiBrandList[Index].NumberOfCores == 'x' || ProcData->DmiBrandList[Index].NumberOfCores == CpuInfo.TotalCoreNumber) &&
+        (ProcData->DmiBrandList[Index].String1ofBrandId == 'x' || ProcData->DmiBrandList[Index].String1ofBrandId == CpuInfo.BrandId.String1)) {
+      DmiBufferPtr->T4[SocketNum].T4ProcFamily = ProcData->DmiBrandList[Index].ValueSetToDmiTable;
+      break;
+    }
+  }
+
+  if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) {
+    Flag = AGESA_ERROR;
+  }
+
+  // Type4 Offset 0x08, Processor ID
+  LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader);
+  DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg;
+  DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg;
+
+  // Type4 Offset 0x11, Voltage
+  DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader);
+
+  // Tyep4 Offset 0x12, External Clock
+  DmiBufferPtr->T4[SocketNum].T4ExternalClock = EXTERNAL_CLOCK;
+
+  // Type4 Offset 0x14, Max Speed
+  DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader);
+
+  // Type4 Offset 0x16, Current Speed
+  DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed;
+
+  // Type4 Offset 0x18, Status
+
+  // Type4 Offset 0x19, Processor Upgrade
+  DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade;
+
+  // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count
+  DmiBufferPtr->T4[SocketNum].T4CoreCount   = CpuInfo.TotalCoreNumber + 1;
+  DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1;
+  DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1;
+
+  // Type4 Offset 0x26, Processor Characteristics
+  DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS;
+
+  // Type4 Offset 0x28, Processor Family 2
+  DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily;
+
+  // Type4 ProcVersion
+  // BaseModel    ProcVersion
+  //    0~1         A
+  //    2~3         B
+  //    4~7         C
+  //    8~9         D
+  //    A~          E
+  switch (CpuInfo.BaseModel) {
+  case 0:
+  case 1:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x41;
+    break;
+  case 2:
+  case 3:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x42;
+    break;
+  case 4:
+  case 5:
+  case 6:
+  case 7:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x43;
+    break;
+  case 8:
+  case 9:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x44;
+    break;
+  case 0xA:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x45;
+    break;
+  default:
+    DmiBufferPtr->T4[SocketNum].T4ProcVersion[0] = 0x41;
+  }
+
+  if (CpuInfo.Stepping >= 0xA) {
+    CpuStepping = CpuInfo.Stepping + 0x37;
+  } else {
+    CpuStepping = CpuInfo.Stepping + 0x30;
+  }
+
+  DmiBufferPtr->T4[SocketNum].T4ProcVersion[1] = (CHAR8) CpuStepping;
+  DmiBufferPtr->T4[SocketNum].T4ProcVersion[2] = '\0';
+
+  //------------------------------
+  // T Y P E 7
+  //------------------------------
+
+  // Type7 Offset 0x05, Cache Configuration
+  DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1;
+  DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2;
+  DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3;
+
+  // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size
+  LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, &ApExeParams->StdHeader);
+
+  // Maximum L1 cache size
+  CacheSize = (UINT32) (((UINT8) (CpuId.ECX_Reg >> 24) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfo.EnabledCoreNumber + 1));
+  DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
+
+  // Installed L1 cache size
+  DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize;
+
+  // Maximum L2 cache size
+  LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, &ApExeParams->StdHeader);
+  CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfo.EnabledCoreNumber + 1));
+  DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
+
+  // Installed L2 cache size
+  DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize;
+
+  // Maximum L3 cache size
+  CacheSize = ((CpuId.EDX_Reg >> 18) & 0x3FFF) * 512;
+  DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
+
+  // Installed L3 cache size
+  DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize;
+
+  // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type
+  DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE;
+
+  // Type7 Offset 0x0F, Cache Speed
+  DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1;
+  DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1;
+  DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1;
+
+  // Type7 Offset 0x10, Error Correction Type
+  DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
+
+  // Type7 Offset 0x11, System Cache Type
+  DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE;
+  DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE;
+  DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE;
+
+  // Type7 Offset 0x12, Associativity
+  DmiBufferPtr->T7L1[SocketNum].T7Associativity = ASSOCIATIVE_2_WAY;
+  DmiBufferPtr->T7L2[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY;
+  if (((CpuId.EDX_Reg >> 12) & 0x0F) == ASSOCIATIVE_16_WAY) {
+    DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY;
+  } else {
+    DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_OTHER;
+  }
+  return (Flag);
+}
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  AdjustGranularity
+ *
+ *  Description:
+ *    If cache size is greater than or equal to 32M, then set granularity
+ *    to 64K. otherwise, set granularity to 1K
+ *
+ *  Parameters:
+ *    @param[in]    *CacheSizePtr
+ *
+ *    @retval       CacheSize
+ *
+ *  Processing:
+ *
+ */
+UINT16
+STATIC
+AdjustGranularity (
+  IN UINT32 *CacheSizePtr
+  )
+{
+  UINT16 CacheSize;
+
+  if (*CacheSizePtr >= 0x8000) {
+    CacheSize = (UINT16) (*CacheSizePtr / 64);
+    CacheSize |= 0x8000;
+  } else {
+    CacheSize = (UINT16) *CacheSizePtr;
+  }
+
+  return (CacheSize);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseDmiBufferStub
+ *
+ *  Description:
+ *     This is the default routine for use when the DMI option is NOT requested.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseDmiBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseDmiBuffer
+ *
+ *  Description:
+ *     Deallocate DMI buffer
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseDmiBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader);
+
+  return  AGESA_SUCCESS;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  IntToString
+ *
+ *  Description:
+ *    Translate UINT array to CHAR array.
+ *
+ *  Parameters:
+ *    @param[in, out]    *String       Pointer to CHAR array
+ *    @param[in]         *Integer      Pointer to UINT array
+ *    @param[in]         SizeInByte    The size of UINT array
+ *
+ *  Processing:
+ *
+ */
+VOID
+STATIC
+IntToString (
+  IN OUT   CHAR8 *String,
+  IN       UINT8 *Integer,
+  IN       UINT8 SizeInByte
+  )
+{
+  UINT8 Index;
+
+  for (Index = 0; Index < SizeInByte; Index++) {
+    *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F;
+    *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F;
+  }
+  for (Index = 0; Index < (SizeInByte * 2); Index++) {
+    if (*(String + Index) >= 0x0A) {
+      *(String + Index) += 0x37;
+    } else {
+      *(String + Index) += 0x30;
+    }
+  }
+  *(String + SizeInByte * 2) = 0x0;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
new file mode 100755
index 0000000000..03780ed500
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatureLeveling.c
@@ -0,0 +1,262 @@
+/**
+ * @file
+ *
+ * AMD CPU Feature Leveling Function.
+ *
+ * Contains code to Level the Feature in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 6626 $   @e \$Date: 2008-07-04 02:01:02 +0800 (Fri, 04 Jul 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuPostInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SaveFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+WriteFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+GetGlobalCpuFeatureListAddress (
+     OUT   UINT64            **Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  FeatureLeveling
+ *
+ *    CPU feature leveling. Set least common features set of all CPUs
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+FeatureLeveling (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 BscSocket;
+  UINT32 Ignored;
+  UINT32 BscCore;
+  UINT32 Socket;
+  UINT32 Core;
+  UINT32 NumberOfSockets;
+  UINT32 NumberOfCores;
+  BOOLEAN *FirstTime;
+  BOOLEAN *NeedLeveling;
+  AGESA_STATUS IgnoredSts;
+  CPU_FEATURES_LIST *globalCpuFeatureList;
+  AP_TASK  TaskPtr;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);
+  FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));
+  NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
+
+  *FirstTime = TRUE;
+  *NeedLeveling = FALSE;
+
+  LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      if (Socket !=  BscSocket) {
+        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
+      }
+    }
+  }
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+
+  if (*NeedLeveling) {
+    TaskPtr.FuncAddress.PfApTaskI  = WriteFeatures;
+    for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+      if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+        for (Core = 0; Core < NumberOfCores; Core++) {
+          if ((Socket != BscSocket) || (Core != BscCore)) {
+            ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
+          }
+        }
+      }
+    }
+    ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+  }
+}
+
+/*----------------------------------------------------------------------------------------
+ *                          L O C A L      F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  SaveFeatures
+ *
+ *    save least common features set of all CPUs
+ *
+ *    @param[in,out]  cpuFeatureListPtr  - Pointer to CPU Feature List.
+ *    @param[in,out]  StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+SaveFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  WriteFeatures
+ *
+ *    Write out least common features set of all CPUs
+ *
+ *    @param[in,out]  cpuFeatureListPtr  - Pointer to CPU Feature List.
+ *    @param[in,out]  StdHeader          - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ */
+VOID
+STATIC
+WriteFeatures (
+  IN OUT   VOID *cpuFeatureListPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  GetGlobalCpuFeatureListAddress
+ *
+ *   Determines the address in system DRAM that should be used for CPU feature leveling.
+ *
+ * @param[out] Address           Address to utilize
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ *
+ */
+VOID
+STATIC
+GetGlobalCpuFeatureListAddress (
+     OUT   UINT64            **Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 AddressValue;
+
+  AddressValue = (UINT32)GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
+
+  *Address = (UINT64 *)(AddressValue);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c
new file mode 100755
index 0000000000..e3a0ef99b5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.c
@@ -0,0 +1,149 @@
+/**
+ * @file
+ *
+ * Implement general feature dispatcher.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *            E X P O R T E D    F U N C T I O N S - External General Services API
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[];
+
+/**
+ * Determines if a specific feature is or will be enabled.
+ *
+ * This code traverses the feature list until a match is
+ * found, then invokes the 'IsEnabled' function of the
+ * feature.
+ *
+ * @param[in]       Feature        Indicates the desired feature.
+ * @param[in]       PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in]       StdHeader      Standard AMD configuration parameters.
+ *
+ * @retval         TRUE      Feature is or will be enabled
+ * @retval         FALSE     Feature is not enabled
+ */
+BOOLEAN
+IsFeatureEnabled (
+  IN       DISPATCHABLE_CPU_FEATURES Feature,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINTN i;
+
+  ASSERT (Feature < MaxCpuFeature);
+
+  for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
+    if (SupportedCpuFeatureList[i]->Feature == Feature) {
+      return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader));
+    }
+  }
+  return FALSE;
+}
+
+/**
+ * Dispatches all features needing to perform some initialization at
+ * this time point.
+ *
+ * This routine searches the feature table for features needing to
+ * run at this time point, and invokes them.
+ *
+ * @param[in]      EntryPoint     Timepoint designator
+ * @param[in]      PlatformConfig Contains the runtime modifiable feature input data.
+ * @param[in]      StdHeader      Standard AMD configuration parameters.
+ *
+ * @return         The most severe status of any called service.
+ */
+AGESA_STATUS
+DispatchCpuFeatures (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN i;
+  AGESA_STATUS AgesaStatus;
+  AGESA_STATUS CalledStatus;
+  AGESA_STATUS IgnoredStatus;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);
+
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
+      if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) {
+        if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) {
+          CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader);
+          if (CalledStatus > AgesaStatus) {
+            AgesaStatus = CalledStatus;
+          }
+        }
+      }
+    }
+  }
+  return AgesaStatus;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
new file mode 100755
index 0000000000..698eafdbc8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuFeatures.h
@@ -0,0 +1,255 @@
+/**
+ * @file
+ *
+ * Generic CPU feature dispatcher and related services.
+ *
+ * Provides a feature processing engine to handle feature in a
+ * more generic way.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FEATURES_H_
+#define _CPU_FEATURES_H_
+
+/**
+ * @page cpufeatimpl CPU Generic Feature Implementation Guide
+ *
+ * The CPU generic feature dispatcher provides services which can be used to implement a
+ * wide range of features in a manner that isolates calling code from knowledge about which
+ * families or features are supported in the current build.
+ *
+ * @par Determine if a New Feature is a Suitable Candidate
+ *
+ * A feature must meet the following requirements:
+ * <ul>
+ * <li> Any core in the system must be able to determine if the feature should be enabled or not.
+ *
+ *   <ul>
+ *   <li> MSRs cannot be read in multisocket systems in the 'IsEnabled' function.
+ *
+ *   <li> Cores cannot be launched in the 'IsEnabled' function.
+ *   </ul>
+ * </ul>
+ *
+ * @par Determine the Time Point at which the Feature Should be Enabled
+ *
+ * Factors to consider in making this determination:
+ *
+ * <ul>
+ * <li> Determine if there are any dependencies on other settings that require strict ordering.
+ *
+ * <li> Consider the state of the APs that you will need.
+ *
+ * <li> Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume.
+ * </ul>
+ *
+ * @par Implementing a new feature
+ *
+ * Perform the following steps to implement a new feature:
+ *
+ * <ul>
+ * <li> Create a unique equate for your time point, @b if you cannot use an existing time point.
+ *
+ * <li> Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature.
+ *
+ * <li> Add a new 'C' file to the Features folder for your feature.
+ *
+ *   <ul>
+ *   <li> The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize'
+ *
+ *   <li> The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure.
+ *   </ul>
+ *
+ * <li> Add a new 'H' file to the Features folder for your feature.
+ *
+ *   <ul>
+ *   <li> The 'H' file declares whatever family specific functions required by the feature.
+ *
+ *   <li> The 'H' file declares a structure containing all family specific functions.  For a reference
+ *        example, your feature API should have a set of conventions similar to cpu specific services,
+ *        @ref cpuimplfss.
+ *   </ul>
+ *
+ * <li> Create 'C' files in all applicable family folders.
+ *
+ *   <ul>
+ *   <li> Implement the required family specific functions.
+ *
+ *   <li> Instantiate a family specific services structure.
+ *   </ul>
+ *
+ * <li> Create \<feature name\>Install.h in the include folder.
+ *
+ *   <ul>
+ *   <li> Add logic to determine when your feature should be included in the build.
+ *
+ *   <li> If the feature should be included, define OPTION_\<feature name\> to the address of your
+ *        CPU_FEATURE_DESCRIPTOR instantiation.  If not, define OPTION_\<feature name\> to be blank.
+ *
+ *   <li> Create a family translation table pointing to all applicable instantiations of
+ *        family specific function structures.
+ *   </ul>
+ *
+ * <li> Modify OptionCpuFeaturesInstall.h in the include folder.
+ *
+ *   <ul>
+ *   <li> Include \<feature name\>Install.h.
+ *
+ *   <li> Add OPTION_\<feature name\> to the SupportedCpuFeatureList array.
+ *   </ul>
+ *
+ * <li> If a new time point was created, add a call to DispatchCpuFeatures at the desired location,
+ *      passing your new time point equate.
+ * </ul>
+ *
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FEAT_AFTER_PM_INIT          (0x0000000000000001ull)
+#define CPU_FEAT_AFTER_POST_MTRR_SYNC   (0x0000000000000002ull)
+#define CPU_FEAT_INIT_MID_END           (0x0000000000000004ull)
+#define CPU_FEAT_INIT_LATE_END          (0x0000000000000008ull)
+#define CPU_FEAT_S3_LATE_RESTORE_END    (0x0000000000000010ull)
+#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC (0x0000000000000020ull)
+#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000040ull)
+/**
+ * Enumerated list of supported features.
+ */
+typedef enum {
+  HardwareC1e,               ///< Hardware C1e
+  HtAssist,                  ///< Probe filter
+  MsgBasedC1e,               ///< Message-based C1e
+  CoreLeveling,              ///< Core Leveling
+  C6Cstate,                  ///< C6 C-state
+  CacheFlushOnHalt,          ///< Cache Flush On Halt
+  PreserveAroundMailbox,     ///< Save-Restore the registers used for AP mailbox, to preserve their normal function.
+  MaxCpuFeature              ///< Not a valid value, used for verifying input
+} DISPATCHABLE_CPU_FEATURES;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Feature specific call to check if it is supported by the system.
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Feature is supported.
+ * @retval       FALSE              Feature is not supported.
+ *
+ */
+typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  The feature's main entry point for enablement.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE;
+
+
+/**
+ * Generic feature descriptor
+ */
+typedef struct {
+  DISPATCHABLE_CPU_FEATURES Feature;     ///< Enumerated feature ID
+  UINT64                    EntryPoint;  ///< Timepoint designator
+  PF_CPU_FEATURE_IS_ENABLED IsEnabled;   ///< Pointer to the function that checks if the feature is supported
+  PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature
+} CPU_FEATURE_DESCRIPTOR;
+
+/**
+ * Table descriptor for the installed features.
+ */
+typedef struct {
+  UINT8       NumberOfFeats;      ///< Number of valid entries in the table.
+  CPU_FEATURE_DESCRIPTOR *FeatureList;       ///< Pointer to the first element in the array.
+} CPU_FEATURE_TABLE;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+BOOLEAN
+IsFeatureEnabled (
+  IN       DISPATCHABLE_CPU_FEATURES Feature,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+DispatchCpuFeatures (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#endif // _CPU_FEATURES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
new file mode 100755
index 0000000000..1dead2cabb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.c
@@ -0,0 +1,344 @@
+/**
+ * @file
+ *
+ * AMD CPU HT Assist Initialization functions.
+ *
+ * Contains code for doing probe filter initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 7284 $   @e \$Date: 2008-08-08 23:29:33 +0800 (Fri, 08 Aug 2008) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Topology.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuLateInit.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFeatures.h"
+#include "cpuHtAssist.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUHTASSIST_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE HtAssistFamilyServiceTable;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should HT Assist be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsHtAssistEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  UINT32           CpuCount;
+  UINT32           Socket;
+  AP_MAILBOXES     ApMailboxes;
+  HT_ASSIST_FAMILY_SERVICES *FamilyServices;
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->PlatformProfile.UseHtAssist) {
+    CpuCount = GetNumberOfProcessors (StdHeader);
+    ASSERT (CpuCount != 0);
+
+    if (CpuCount == 1) {
+      GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+      if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
+        IsEnabled = TRUE;
+      }
+    } else if (CpuCount > 1) {
+      IsEnabled = TRUE;
+    }
+    if (IsEnabled) {
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (IsProcessorPresent (Socket, StdHeader)) {
+          GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+          if ((FamilyServices == NULL) || !FamilyServices->IsHtAssistSupported (FamilyServices, Socket, StdHeader)) {
+            IsEnabled = FALSE;
+            break;
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the HT Assist feature.
+ *
+ * HT Assist initialization requires the following series of steps.
+ * -# Disable Cache on @b all cores.
+ * -# Initialize Probe Filter PCI regs
+ *    -# Save L3 Scrub Rate
+ *    -# On each node:
+ *       -# Turn off L3Scrubber and Disable L3 cache
+ *    -# On each node:
+ *       -# Enable probe filter
+ *    -# On each node:
+ *       -# Enable L3 cache and turn on Scrubber.
+ *    -# Restore L3 Scrub Rate
+ * -# Enable Cache on @b all cores.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       AGESA_SUCCESS      HT Assist feature is running optimally.
+ * @retval       AGESA_WARNING      HT Assist feature is not running optimally.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeHtAssistFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                     CpuCount;
+  UINT32                     Socket;
+  AGESA_STATUS               AgesaStatus;
+  AP_MAILBOXES               ApMailboxes;
+  AP_EXE_PARAMS              ApParams;
+  UINT32                     Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE];
+  HT_ASSIST_FAMILY_SERVICES  *FamilyServices[MAX_SOCKETS_SUPPORTED];
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  // There are many family service call outs.  Initialize the family service array while
+  // cache is still enabled.
+  for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
+    if (IsProcessorPresent (Socket, StdHeader)) {
+      GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices[Socket], StdHeader);
+    } else {
+      FamilyServices[Socket] = NULL;
+    }
+  }
+
+  if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) {
+    // Check for optimal settings
+    GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+    CpuCount = GetNumberOfProcessors (StdHeader);
+    if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) ||
+        ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) {
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (FamilyServices[Socket] != NULL) {
+          if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) {
+            // Non-optimal settings.  Log an event.
+            AgesaStatus = AGESA_WARNING;
+            PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader);
+            break;
+          }
+        }
+      }
+    }
+  } else {
+    // Disable the scrubbers.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
+      }
+    }
+
+    // Wait for 40us
+    WaitMicroseconds ((UINT32) 40, StdHeader);
+
+    // Run DisableAllCaches on AP cores.
+    ApParams.StdHeader = *StdHeader;
+    ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE;
+    ApParams.RelatedDataBlock = NULL;
+    ApParams.RelatedBlockLength = 0;
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+
+    // Run DisableAllCaches on core 0.
+    DisableAllCaches (&ApParams);
+
+    // Family hook before initialization.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Activate probe filter.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Family hook after initialization.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader);
+      }
+    }
+
+    // Run EnableAllCaches on core 0.
+    EnableAllCaches (&ApParams);
+
+    // Run EnableAllCaches on every core.
+    ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE;
+    RunLateApTaskOnAllAPs (&ApParams, StdHeader);
+
+    // Restore the scrubbers.
+    for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+      if (FamilyServices[Socket] != NULL) {
+        FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
+      }
+    }
+  }
+
+  return AgesaStatus;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Disable all the caches on current core.
+ *
+ * @param[in] ApExeParams   Handle to config for library and services.
+ *
+ * @retval    AGESA_SUCCESS  Always succeeds.
+ *
+ */
+AGESA_STATUS
+DisableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT32   CR0Data;
+  HT_ASSIST_FAMILY_SERVICES  *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader);
+
+  FamilyServices->HookDisableCache (FamilyServices, &ApExeParams->StdHeader);
+
+  // Disable cache through CR0.
+  LibAmdReadCpuReg (0, &CR0Data);
+  CR0Data |= (0x60000000);
+  LibAmdWriteCpuReg (0, CR0Data);
+
+  // Execute wbinvd
+  LibAmdWriteBackInvalidateCache ();
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Enable all the caches on current core.
+ *
+ * @param[in] ApExeParams    Handle to config for library and services.
+ *
+ * @retval    AGESA_SUCCESS  Always succeeds.
+ *
+ */
+AGESA_STATUS
+EnableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  )
+{
+  UINT32   CR0Data;
+  HT_ASSIST_FAMILY_SERVICES  *FamilyServices;
+
+  // Enable cache through CR0.
+  LibAmdReadCpuReg (0, &CR0Data);
+  CR0Data &= ~(0x60000000);
+  LibAmdWriteCpuReg (0, CR0Data);
+
+  GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, (CONST VOID **)&FamilyServices, &ApExeParams->StdHeader);
+
+  FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist =
+{
+  HtAssist,
+  (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END),
+  IsHtAssistEnabled,
+  InitializeHtAssistFeature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
new file mode 100755
index 0000000000..0ce6b17574
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHtAssist.h
@@ -0,0 +1,278 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU HT Assist Function declarations.
+ *
+ * Contains code that declares the AGESA CPU Probe filter related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_HT_ASSIST_H_
+#define _CPU_HT_ASSIST_H_
+
+#include "Filecode.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _HT_ASSIST_FAMILY_SERVICES HT_ASSIST_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define AP_LATE_TASK_DISABLE_CACHE (0x00000000 | PROC_CPU_FEATURE_CPUHTASSIST_FILECODE)
+#define AP_LATE_TASK_ENABLE_CACHE  (0x00010000 | PROC_CPU_FEATURE_CPUHTASSIST_FILECODE)
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if HT Assist is supported.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is supported.
+ * @retval       FALSE              HT Assist is not supported.
+ *
+ */
+typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific hook before HT Assist is initialized.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_BEFORE_INIT (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_BEFORE_INIT *PF_HT_ASSIST_BEFORE_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_DISABLE_CACHE (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_DISABLE_CACHE *PF_HT_ASSIST_DISABLE_CACHE;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef VOID F_HT_ASSIST_ENABLE_CACHE (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_ENABLE_CACHE *PF_HT_ASSIST_ENABLE_CACHE;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to enable.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_INIT (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to disable cache.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_AFTER_INIT (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_AFTER_INIT *PF_HT_ASSIST_AFTER_INIT;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to save the L3 scrubber.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_GET_L3_SCRUB_CTRL (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_GET_L3_SCRUB_CTRL *PF_HT_ASSIST_GET_L3_SCRUB_CTRL;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to restore the L3 scrubber.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Contains L3 scrubber settings to restore.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+typedef VOID F_HT_ASSIST_SET_L3_SCRUB_CTRL (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_SET_L3_SCRUB_CTRL *PF_HT_ASSIST_SET_L3_SCRUB_CTRL;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to restore the L3 scrubber.
+ *
+ * @param[in]    HtAssistServices    HT Assist family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       TRUE                The system may be running with non-optimal settings.
+ * @return       FALSE               The system may is running optimally.
+ *
+ */
+typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
+  IN       HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
+
+
+/**
+ * Provide the interface to the HT Assist Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _HT_ASSIST_FAMILY_SERVICES {
+  UINT16          Revision;                             ///< Interface version
+  // Public Methods.
+  PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported;        ///< Method: Check if HT Assist is supported.
+  PF_HT_ASSIST_INIT HtAssistInit;                       ///< Method: Enable HT Assist.
+  PF_HT_ASSIST_GET_L3_SCRUB_CTRL GetL3ScrubCtrl;        ///< Method: Save/disable the L3 scrubber.
+  PF_HT_ASSIST_SET_L3_SCRUB_CTRL SetL3ScrubCtrl;        ///< Method: Restore the L3 scrubber.
+  PF_HT_ASSIST_BEFORE_INIT HookBeforeInit;              ///< Method: Hook before enabling HT Assist.
+  PF_HT_ASSIST_AFTER_INIT HookAfterInit;                ///< Method: Hook after enabling HT Assist.
+  PF_HT_ASSIST_DISABLE_CACHE HookDisableCache;          ///< Method: Core hook just before disabling cache.
+  PF_HT_ASSIST_ENABLE_CACHE HookEnableCache;            ///< Method: Core hook just after enabling cache.
+  PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig;        ///< Method: Check if HT Assist is running optimally.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+DisableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+AGESA_STATUS
+EnableAllCaches (
+  IN       AP_EXE_PARAMS *ApExeParams
+  );
+
+#endif  // _CPU_HT_ASSIST_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
new file mode 100755
index 0000000000..49fb9b00a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.c
@@ -0,0 +1,166 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU HW C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "Topology.h"
+#include "cpuFeatures.h"
+#include "cpuHwC1e.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should hardware C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ * @retval       FALSE              HW C1e cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsHwC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  BOOLEAN          IsEnabled;
+  AP_MAILBOXES     ApMailboxes;
+  HW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+  IsEnabled = FALSE;
+  if (PlatformConfig->C1eMode == C1eModeHardware) {
+    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
+    ASSERT (PlatformConfig->C1ePlatformData != 0);
+    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
+      if (GetNumberOfProcessors (StdHeader) == 1) {
+        GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+        if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
+          GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+          if (FamilyServices != NULL) {
+            IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader);
+          }
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       The most severe status of any family specific service.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeHwC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AGESA_STATUS CalledStatus;
+  AGESA_STATUS AgesaStatus;
+  HW_C1E_FAMILY_SERVICES *FamilyServices;
+
+  AgesaStatus = AGESA_SUCCESS;
+
+  if (IsWarmReset (StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+    CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
+    if (CalledStatus > AgesaStatus) {
+      AgesaStatus = CalledStatus;
+    }
+  }
+  return AgesaStatus;
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e =
+{
+  HardwareC1e,
+  CPU_FEAT_AFTER_PM_INIT,
+  IsHwC1eFeatureEnabled,
+  InitializeHwC1eFeature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
new file mode 100755
index 0000000000..53226f7ff1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuHwC1e.h
@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU HW C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_HW_C1E_H_
+#define _CPU_HW_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _HW_C1E_FAMILY_SERVICES HW_C1E_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if hardware C1e is supported.
+ *
+ * @param[in]    HwC1eServices      Hardware C1e services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ * @retval       FALSE              HW C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable hardware C1e.
+ *
+ * @param[in]    HwC1eServices      Hardware C1e services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_HW_C1E_INIT (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_HW_C1E_INIT *PF_HW_C1E_INIT;
+
+/**
+ * Provide the interface to the hardware C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _HW_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported;                              ///< Method: Family specific call to check if hardware C1e is supported.
+  PF_HW_C1E_INIT InitializeHwC1e;                                       ///< Method: Family specific call to enable hardware C1e.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_HW_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
new file mode 100755
index 0000000000..1be14e2db8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.c
@@ -0,0 +1,236 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Message-based C1e feature support code.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "OptionMultiSocket.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuMsgBasedC1e.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+EnableMsgC1eOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should message-based C1e be enabled
+ *
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Message-based C1e is supported.
+ * @retval       FALSE              Message-based C1e cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+IsMsgBasedC1eFeatureEnabled (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINTN                         Link;
+  UINTN                         LinkCount;
+  UINT32                        Socket;
+  UINT32                        Module;
+  BOOLEAN                       IsEnabled;
+  PCI_ADDR                      PciAddress;
+  AGESA_STATUS                  AgesaStatus;
+  HT_HOST_FEATS                 HtHostFeats;
+  CPU_SPECIFIC_SERVICES         *CpuServices;
+  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
+
+  ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
+
+  IsEnabled = FALSE;
+  if (PlatformConfig->C1eMode == C1eModeMsgBased) {
+    ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
+    ASSERT (PlatformConfig->C1ePlatformData != 0);
+    if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
+      IsEnabled = TRUE;
+      for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
+        if (IsProcessorPresent (Socket, StdHeader)) {
+          GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, (CONST VOID **)&FamilyServices, StdHeader);
+          if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {
+            IsEnabled = FALSE;
+            break;
+          } else {
+            // If the CPU revision supports message-based C1e, check whether the feature should
+            // be disabled based on the speed of ncHT links (HT1).
+            GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);
+            for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+              if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
+                HtHostFeats.HtHostValue = 0;
+                for (LinkCount = 0; LinkCount < 8; LinkCount++) {
+                  if (FindHtHostCapability (LinkCount, &PciAddress, StdHeader)) {
+                    CpuServices->GetHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader);
+                    if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {
+                      IsEnabled = FALSE;
+                      break;
+                    }
+                  }
+                }
+              }
+              // Exit for (Module = 0; Module < GetPlatformNumberOfModules; Module++)
+              if (!IsEnabled) {
+                break;
+              }
+            }
+          }
+        }
+        // Exit for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++)
+        if (!IsEnabled) {
+          break;
+        }
+      }
+    }
+  }
+  return IsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Message-based C1e
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+InitializeMsgBasedC1eFeature (
+  IN       UINT64                 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  AP_TASK      TaskPtr;
+  AMD_CPU_EARLY_PARAMS CpuEarlyParams;
+
+  if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) {
+    CpuEarlyParams.PlatformConfig = *PlatformConfig;
+
+    TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = &EntryPoint;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
+    OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  'Local' core 0 task to enable message-based C1e on it's socket.
+ *
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ * @param[in]    CpuEarlyParams     Service parameters.
+ *
+ */
+VOID
+STATIC
+EnableMsgC1eOnSocket (
+  IN       VOID *EntryPoint,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+  )
+{
+  MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
+
+  GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+  FamilyServices->InitializeMsgBasedC1e (FamilyServices,
+                                         *((UINT64 *) EntryPoint),
+                                         &CpuEarlyParams->PlatformConfig,
+                                         StdHeader);
+}
+
+CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e =
+{
+  MsgBasedC1e,
+  (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
+  IsMsgBasedC1eFeatureEnabled,
+  InitializeMsgBasedC1eFeature
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
new file mode 100755
index 0000000000..4896622986
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuMsgBasedC1e.h
@@ -0,0 +1,127 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Message-based C1e Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU C1e related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_MSG_BASED_C1E_H_
+#define _CPU_MSG_BASED_C1E_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _MSG_BASED_C1E_FAMILY_SERVICES MSG_BASED_C1E_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if message-based C1e is supported.
+ *
+ * @param[in]    MsgBasedC1eServices Contains the runtime modifiable feature input data.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               Message-based C1e is supported.
+ * @retval       FALSE              Message-based C1e is not supported.
+ *
+ */
+typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to enable hardware C1e.
+ *
+ * @param[in]    MsgBasedC1eServices Hardware C1e services.
+ * @param[in]    EntryPoint          Timepoint designator.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       Family specific error value.
+ *
+ */
+typedef AGESA_STATUS F_MSG_BASED_C1E_INIT (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT;
+
+/**
+ * Provide the interface to the hardware C1e Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _MSG_BASED_C1E_FAMILY_SERVICES {
+  UINT16          Revision;                                             ///< Interface version
+  // Public Methods.
+  PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported;                 ///< Method: Family specific call to check if hardware C1e is supported.
+  PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e;                          ///< Method: Family specific call to enable hardware C1e.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_MSG_BASED_C1E_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
new file mode 100755
index 0000000000..766a623102
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateGather.c
@@ -0,0 +1,382 @@
+/**
+ * @file
+ *
+ * AMD CPU Pstate Data Gather Function.
+ *
+ * Contains code to collect all the Pstate related information from MSRs, and PCI registers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuPostInit.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_POST_CONFIGURATION    OptionPstatePostConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+PStateGather (
+  IN OUT   VOID *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+AGESA_STATUS
+PStateGatherStub (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+AGESA_STATUS
+PStateGatherMain (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PStateGatherData
+ *
+ *  Description:
+ *    This function will gather PState information from the MSRs and fill up the
+ *    pStateBuf. This buffer will be used by the PState Leveling, and PState Table
+ *    generation code later.
+ *
+ *    Note:  This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval      AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherData (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader);
+  return (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr);
+  // Note: Split config struct into PEI/DXE halves. This one is PEI.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGatherStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherStub (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGatherMain
+ *
+ *  Description:
+ *     This is the common routine for BSP gathering the Pstate data.
+ *
+ *  Parameters:
+ *    @param[in]        *StdHeader
+ *    @param[in, out]   *PStateStrucPtr
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateGatherMain (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  PopulatedSockets;
+  UINT32                  NumberOfSockets;
+  UINT32                  Socket;
+  AGESA_STATUS            IgnoredSts;
+  PSTATE_LEVELING         *PStateBufferPtr;
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  UINT32                  MaxState;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredSts));
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+
+  PopulatedSockets = 1;
+  PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
+
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);
+
+  PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE);
+
+  MaxState = 0;
+  FamilySpecificServices->GetPstateMaxState (FamilySpecificServices, &MaxState, StdHeader);
+
+  TaskPtr.FuncAddress.PfApTaskI = PStateGather;
+  //
+  // Calculate max buffer size in dwords that need to pass to ap task.
+  //
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES)));
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  //
+  //Get P-States and fill the PStateBufferPtr for BSP
+  //
+  ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
+
+  //
+  //Calculate next node buffer address
+  //
+  PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
+  PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
+  PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
+  //
+  //Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
+  //
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (Socket != BscSocket) {
+      if (IsProcessorPresent (Socket, StdHeader)) {
+        PopulatedSockets++;
+        LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader);
+        TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+        ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
+        PStateBufferPtr->SocketNumber = (UINT8) Socket;
+        //
+        //Calculate next node buffer address
+        //
+        PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+        PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
+        PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+      }
+    }
+  }
+  PStateStrucPtr->TotalSocketInSystem = PopulatedSockets;
+
+  return AGESA_SUCCESS;
+}
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateGather
+ *
+ *  Description:
+ *     This is the common routine run on each BSC for gathering Pstate data.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateBuffer
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+PStateGather (
+  IN OUT   VOID                *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  UINT32                 k;
+  UINT32                 IddVal;
+  UINT32                 IddDiv;
+  UINT32                 NodeNum;
+  UINT32                 CoreNum;
+  UINT32                 TempVar_c;
+  UINT32                 TotalEnabledPStates;
+  PCI_ADDR               PciAddress;
+  PSTATE_LEVELING        *PStateBufferPtr;
+  BOOLEAN                PStateEnabled;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  UINT32                 Socket;
+  AGESA_STATUS           IgnoredSts;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  ASSERT (FamilySpecificServices != NULL);
+
+  PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
+  TotalEnabledPStates = 0;
+  PStateEnabled = FALSE;
+
+  //
+  /// Sockets number:  code looking at PStateBufferPtr->TotalCoresInNode
+  ///        needs to know it is Processor (or socket) core count and NOT a Node Core count.
+  GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
+  PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum;
+
+  //
+  // Assume current CoreNum always zero.(BSC)
+  //
+  GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader);
+
+  PStateBufferPtr->CreateAcpiTables = 1; /// @todo need remove
+
+  //
+  // We need to know the max pstate state in this socket.
+  //
+  FamilySpecificServices->GetPstateMaxState (FamilySpecificServices, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c;
+
+  for (k = 0; k <= TempVar_c; k++) {
+    // Check if PState is enabled
+    FamilySpecificServices->GetPstateRegisterInfo (FamilySpecificServices,
+                                                   k,
+                                                   &PStateEnabled,
+                                                   &IddVal,
+                                                   &IddDiv,
+                                                   StdHeader);
+
+    LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader);
+
+    if (PStateEnabled) {
+
+      FamilySpecificServices->GetPstateFrequency (
+        FamilySpecificServices,
+        (UINT8) k,
+        &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq),
+        StdHeader);
+
+      FamilySpecificServices->GetPstatePower (
+        FamilySpecificServices,
+        (UINT8) k,
+        &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power),
+        StdHeader);
+
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal;
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv;
+
+      PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable  = 1;
+      TotalEnabledPStates++;
+    }
+  } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+  // Don't create ACPI Tables if there is one or less than one PState is enabled
+  if (TotalEnabledPStates <= 1) {
+    PStateBufferPtr[0].CreateAcpiTables = 0;
+  }
+
+  //--------------------Check Again--------------------------------
+
+  IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts);
+  GetPciAddress (StdHeader, Socket, NodeNum, &PciAddress, &IgnoredSts);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+  TempVar_c = 0;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].HtcCapable =
+    (UINT8) ((TempVar_c & 0x00000400) >> 10);    // Bit  10
+
+  TempVar_c = 0;
+  PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
+  PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit =
+    (UINT8) ((TempVar_c & 0x70000000) >> 28);   // Bits 30:28
+
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
new file mode 100755
index 0000000000..169a94f170
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateLeveling.c
@@ -0,0 +1,1088 @@
+/**
+ * @file
+ *
+ * AMD CPU Pstate Leveling Function.
+ *
+ * Contains code to level the Pstates in a multi-socket system
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuPostInit.h"
+#include "Ids.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_POST_CONFIGURATION    OptionPstatePostConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PStateLevelingStub (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+VOID
+CorePstateRegModify (
+  IN       VOID               *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PutAllCoreInPState0 (
+  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+AGESA_STATUS
+StartPstateMsrModify (
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+VOID
+STATIC
+PutCoreInPState0 (
+  IN       VOID   *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PStateLeveling
+ *
+ *  Description:
+ *    This function will populate the PStateBuffer, after doing the PState Leveling
+ *    Note: This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLeveling (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader);
+  return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader));
+  // Note: Split config struct into PEI/DXE halves. This one is PEI.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateLevelingStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLevelingStub (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  PStateLevelingMain
+ *
+ *  Description:
+ *     This is the common routine for creating the ACPI information tables.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateStrucPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  UINT32                   i;
+  UINT32                   k;
+  UINT32                   m;
+  UINT32                   TotalIterations;
+  UINT32                   LogicalSocketCount;
+  UINT32                   TempVar_a;
+  UINT32                   TempVar_b;
+  UINT32                   TempVar_c;
+  UINT32                   TempVar_d;
+  UINT32                   TempVar_e;
+  UINT32                   TempVar_f;
+  PCI_ADDR                 PciAddress;
+
+  UINT32                   TempFreqArray[20];
+  UINT32                   TempPowerArray[20];
+  UINT32                   TempIddValueArray[20];
+  UINT32                   TempIddDivArray[20];
+  UINT32                   TempSocketPiArray[20];
+
+  BOOLEAN                  TempFlag1;
+  BOOLEAN                  TempFlag2;
+  BOOLEAN                  TempFlag3;
+  BOOLEAN                  TempFlag4;
+  BOOLEAN                  AllCoresHaveHtcCapEquToZeroFlag;
+  BOOLEAN                  AllCoreHaveMaxOnePStateFlag;
+  BOOLEAN                  PstateMaxValEquToPstateHtcLimitFlag;
+  BOOLEAN                  AtLeastOneCoreHasPstateHtcLimitEquToOneFlag;
+  BOOLEAN                  PstateMaxValMinusHtcPstateLimitLessThan2Flag;
+  PSTATE_LEVELING          *PStateBufferPtr;
+  PSTATE_LEVELING          *PStateBufferPtrTmp = NULL;
+  UINT32                   MaxPstateInNode;
+  AGESA_STATUS             Status;
+
+  TempFlag1 = FALSE;
+  TempFlag2 = FALSE;
+  TempFlag3 = FALSE;
+  TempFlag4 = FALSE;
+  AllCoresHaveHtcCapEquToZeroFlag = FALSE;
+  AllCoreHaveMaxOnePStateFlag = FALSE;
+  PstateMaxValEquToPstateHtcLimitFlag = FALSE;
+  AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE;
+  PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE;
+  PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
+  Status = AGESA_SUCCESS;
+
+  if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) {
+    PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
+    PStateBufferPtr[0].InitStruct = 1;
+    return AGESA_UNSUPPORTED;
+  }
+
+  LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem;
+
+  // This section of code will execute only for "core 0" i.e. BSP
+  // Read P-States of all the cores.
+  if (PStateBufferPtr[0].InitStruct == 0) {
+    // Check if core frequency and power are same across all sockets.
+    TempFlag1 = FALSE;
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) {
+        TempFlag1 = TRUE;
+        break;
+      }
+      MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+      for (k = 0; k <= MaxPstateInNode; k++) {
+        if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq !=
+             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) ||
+            (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power !=
+             PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) {
+          TempFlag1 = TRUE;
+          break; // Come out of the inner FOR loop
+        }
+      }
+      if (TempFlag1) {
+        break; // Come out of the outer FOR loop
+      }
+    }
+
+    if (!TempFlag1) {
+      // No need to do pStateLeveling, or writing to pState MSR registers
+      // if all CPUs have Identical PStates
+      PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
+      PStateBufferPtr[0].InitStruct = 1;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    } else {
+      PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE;
+    }
+
+    // 1_b) & 1_c)
+    TempFlag1 = FALSE;
+    TempFlag2 = FALSE;
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 0) {
+        TempFlag1 = TRUE;
+      } else {
+        TempFlag2 = TRUE;
+      }
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) {
+        TempFlag3 = TRUE;
+      } else {
+        TempFlag4 = TRUE;
+      }
+
+      if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
+           PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) {
+        PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
+      }
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue ==
+          PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+        PstateMaxValEquToPstateHtcLimitFlag = TRUE;
+      }
+
+      if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
+        AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
+      }
+    }
+
+    // Do general setup of flags, that we may use later
+    // Implementation of (1_b)
+    if (TempFlag1 && TempFlag2) {
+      //
+      //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with
+      //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b).
+      //
+      PStateBufferPtr[0].InitStruct = 1;
+      PStateBufferPtr[0].CreateAcpiTables = 0;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    } else if (TempFlag1 && !TempFlag2) {
+      //
+      //all processors have only 1 enabled P-state
+      //
+      AllCoreHaveMaxOnePStateFlag = TRUE;
+      PStateBufferPtr[0].OnlyOneEnabledPState = TRUE;
+    }
+
+    // Processors with F3xE8[HTC_CAPABLE] = 1 can not be
+    // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0.
+    if (TempFlag3 && TempFlag4) {
+      PStateBufferPtr[0].InitStruct = 1;
+      PStateBufferPtr[0].CreateAcpiTables = 0;
+      PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+      return AGESA_UNSUPPORTED;
+    }
+
+    if (TempFlag3) {
+      //
+      //If code run to here means that all processors do not have HTC_CAPABLE.
+      //
+      AllCoresHaveHtcCapEquToZeroFlag = TRUE;
+    }
+
+    //--------------------------------------------------------------------------------
+    // S T E P - 2
+    //--------------------------------------------------------------------------------
+    // Now run the PState Leveling Algorithm which will create mixed CPU P-State
+    // Tables.
+    // Follow the algorithm in the latest BKDG
+    // -------------------------------------------------------------------------------
+    // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the
+    // coherent fabric, and match P0 power for all CPU cores to the highest P0 power
+    // value in the coherent fabric.
+    // 2_a) If all processors have only 1 enabled P-State BIOS must write the
+    //      appropriate CpuFid value resulting from the matched CPU COF to all
+    //      copies of MSRC001_0070[CpuFid], and exit the sequence (No further
+    //      steps are executed)
+    //--------------------------------------------------------------------------------
+    // Identify the lowest P0 Frequency and maximum P0 Power
+    TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].CoreFreq;
+    TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].Power;
+    TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].IddValue;
+    TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].IddDiv;
+
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq) {
+        TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq;
+      }
+
+      if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power) {
+        TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power;
+        TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue;
+        TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv;
+      }
+    }
+
+    // Set P0 Frequency and Power for all CPUs
+    for (i = 0; i < LogicalSocketCount; i++) {
+      CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq = TempVar_d;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power = TempVar_e;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue = TempVar_a;
+      PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv = TempVar_b;
+    }
+
+    // 2_a)
+    if (!AllCoreHaveMaxOnePStateFlag) {
+      //--------------------------------------------------------------------------
+      // STEP - 3
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for P-states used by HTC. Skip to step 4
+      // is any processor reports F3xE8[HTC_Capable] = 0;
+      // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for
+      //      processors with F3x64[HtcPstateLimit] = 000b.
+      // 3_b) Identify the lowest CPU COF for all processors in the P-state
+      //      pointed to by [The Hardware Thermal Control (HTC) Register]
+      //      F3x64[HtcPstateLimit]
+      // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control
+      //      (HTC) Register] F3x64[HtcPstateLimit] for all processors to the
+      //      previously identified lowest CPU COF value.
+      // 3_d) Identify the highest power for all processors in the P-state
+      //      pointed to by [The Hardware Thermal Control (HTC) Register]
+      //      F3x64[HtcPstateLimit].
+      // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC)
+      //      Register] F3x64[HtcPstateLimit] to the previously identified
+      //      highest power value.
+      if (!AllCoresHaveHtcCapEquToZeroFlag) {
+        // 3_a)
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) {
+            // To Be Done (Set Htc and Stc PstateLimit values)
+            // for this CPU (using PCI address space)
+            for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) {
+              if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) {
+                // Set F3x64[HtcPstateLimit] = 001b
+                PciAddress.Address.Function = FUNC_3;
+                PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
+                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+                // Bits 30:28
+                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
+                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+
+                // Set F3x68[StcPstateLimit] = 001b
+                PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG;
+                LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+                // Bits 28:30
+                TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
+                LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+              }
+            }
+            // Set LocalBuffer
+            PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1;
+            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) {
+              PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
+            }
+
+            if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) {
+              PstateMaxValEquToPstateHtcLimitFlag = TRUE;
+            }
+          }
+
+          if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
+            AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
+          }
+        }
+
+        // 3_b) and 3_d)
+        TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit;
+        TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
+        TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
+        TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
+        TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          for (k = 0; k < 1; k++) {
+            TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+            if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
+              TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
+            }
+
+            if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
+              TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
+              TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
+              TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
+            }
+          }
+        }
+
+        // 3_c) and 3_e)
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
+        }
+      } // if(AllCoresHaveHtcCapEquToZeroFlag)
+
+
+      //--------------------------------------------------------------------------
+      // STEP - 4
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for the lowest performance P-state:
+      // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor,
+      //      set PstateEn = 0 for all the P-states greater than
+      //      F3x64[HtcPstateLimit] for all processors.
+      // 4_b) Identify the lowest CPU COF for all processors in the P-state
+      //      pointed to by F3xDC[PstateMaxVal].
+      // 4_c) Modify the CPU COF for all processors in the P-state pointed to by
+      //      F3xDC[PstateMaxVal] to the previously identified lowest CPU COF
+      //      value.
+      // 4_d) Identify the highest power for all processors in the P-state
+      //      pointed to by F3xDC[PstateMaxVal].
+      // 4_e) Modify the power for all processors in the P-state pointed to by
+      //      F3xDC[PstateMaxVal] to the previously identified highest power
+      //      value.
+
+      // 4_a)
+      if (PstateMaxValEquToPstateHtcLimitFlag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1;
+          for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) {
+            PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+          }
+          //--------------------------------------------------------------------------
+          // STEP - 5
+          //--------------------------------------------------------------------------
+          // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance
+          //      P-state with PstateEn set for each processor (Step 4 can disable
+          //      P-states pointed to by F3xDC[PstateMaxVal])
+
+          // Use this value of HtcPstateLimit to program the
+          // F3xDC[pStateMaxValue]
+          TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+          TempVar_e <<= 8;
+          // Bits 10:8
+
+          for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) {
+            if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) {
+              PciAddress.Address.Function = FUNC_3;
+              PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+              LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+              TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e;
+              LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
+            }
+          }//End of step 5
+        }
+      }// End of 4_a)
+
+      // 4_b) and 4_d)
+      TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue;
+      TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
+      TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
+      TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
+      TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
+
+      for (i = 0; i < LogicalSocketCount; i++) {
+        CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+        TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+        if (TempVar_d >
+            PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
+          TempVar_d =
+          PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
+        }
+
+        if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
+          TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
+          TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
+          TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
+        }
+      }
+
+      // 4_c) and 4_e)
+      for (i = 0; i < LogicalSocketCount; i++) {
+        CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+        TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
+        PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
+      }
+
+
+      //--------------------------------------------------------------------------
+      // STEP - 6
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for upper intermediate performance
+      // P-state(s):
+      // Upper intermediate PStates = PStates between (Not including) P0 and
+      // F3x64[HtcPstateLimit]
+      // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0
+      //      for enabled upper intermediate P-states for all processors with
+      //      F3x64[HtcPstateLimit] > 001b and skip the remaining actions for
+      //      this numbered step.
+      // 6_b) Define each of the available upper intermediate P-states; for each
+      //      processor concurrently evaluate the following loop; when any
+      //      processor falls out of the loop (runs out of available upper
+      //      intermediate Pstates) all other processors have their remaining
+      //      upper intermediate P-states invalidated (PstateEn = 0);
+      //      for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--)
+      //         - Identify the lowest CPU COF for P(i).
+      //         - Identify the highest power for P(i).
+      //         - Modify P(i) CPU COF for all processors to the previously
+      //           identified lowest CPU COF value.
+      //         - Modify P(i) power for all processors to the previously
+      //           identified highest power value.
+
+      // 6_a)
+      if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          for (k = 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) {
+            if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) {
+              // Make a function call to clear the
+              // structure values
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+            }
+          }
+        }
+      }
+      // 6_b)
+      else {
+        // Identify Lowest Frequency and Highest Power
+        TotalIterations = 0;
+        TempFlag1 = TRUE;
+
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1;
+        }
+
+        do {
+          //For first socket, try to find a candidate
+          if (TempSocketPiArray[0] != 0) {
+            while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
+              TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
+              if (TempSocketPiArray[0] == 0) {
+                TempFlag1 = FALSE;
+                break;
+              }
+            }
+          } else {
+            TempFlag1 = FALSE;
+          }
+          if (TempFlag1) {
+            TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
+            TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
+            TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
+            TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
+
+            //Try to find next candidate
+            for (i = 1; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempSocketPiArray[i] != 0) {
+                while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
+                  TempSocketPiArray[i]--;
+                  if (TempSocketPiArray[i] == 0) {
+                    TempFlag1 = FALSE;
+                    break;
+                  }
+                }//end while
+              } else {
+                TempFlag1 = FALSE;
+              }
+
+            } //end for LogicalSocketCount
+          }
+
+          if (TempFlag1) {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              //
+              //Compare
+              //
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
+                TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
+              }
+
+              if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
+                TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
+                TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
+                TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
+              }
+            }
+            // Modify (Pi) CPU COF and Power for all the CPUs
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power    = TempPowerArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv   = TempIddDivArray[TotalIterations];
+              TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
+            }
+          } else {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              for (m = TempSocketPiArray[i]; m > 0; m--) {
+                PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
+              }
+            }
+          }
+
+          TotalIterations++;
+        } while (TempFlag1);
+
+      } // else
+
+      //--------------------------------------------------------------------------
+      // STEP - 7
+      //--------------------------------------------------------------------------
+      // Match the CPU COF and power for lower intermediate performance P - state(s)
+      // Lower Intermediate Pstates = Pstates between (not including)
+      // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal]
+      // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any
+      //      processor, set PstateEn = 0 for enabled lower intermediate P - states
+      //      for all processors with (F3xDC[PstateMaxVal] -
+      //      F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this
+      //      numbered step.
+      // 7_b) Define each of the available lower intermediate P-states; for each
+      //      processor concurrently evaluate the following loop; when any
+      //      processor falls out of the loop (runs out of available lower
+      //      intermediate Pstates) all other processors have their remaining
+      //      lower intermediate P-states invalidated (PstateEn = 0);
+      //      for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--)
+      //         - Identify the lowest CPU COF for P-states between
+      //           (not including) F3x64[HtcPstateLimit] and P(i).
+      //         - Identify the highest power for P-states between
+      //           (not including) F3x64[HtcPstateLimit] and P(i).
+      //         - Modify P(i) CPU COF for all processors to the previously
+      //           identified lowest CPU COF value.
+      //         - Modify P(i) power for all processors to the previously
+      //           identified highest power value.
+
+
+      // 7_a)
+      if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) {
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+
+          for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
+              k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
+              k--) {
+            if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
+                 PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) {
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
+            }
+          }
+        }
+      }
+
+      // 7_b)
+      else {
+        // Identify Lowest Frequency and Highest Power
+
+        TotalIterations = 0;
+        TempFlag1 = TRUE;
+
+        for (i = 0; i < LogicalSocketCount; i++) {
+          CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+          TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
+        }
+
+        do {
+          //For first socket, try to find a candidate
+          if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
+            while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
+              TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
+              if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
+                TempFlag1 = FALSE;
+                break;
+              }
+            }
+          } else {
+            TempFlag1 = FALSE;
+          }
+          if (TempFlag1) {
+            TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
+            TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
+            TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
+            TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
+
+            //Try to find next candidate
+            for (i = 1; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+                while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
+                  TempSocketPiArray[i]--;
+                  if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
+                    TempFlag1 = FALSE;
+                    break;
+                  }
+                }//end while
+              } else {
+                TempFlag1 = FALSE;
+              }
+            } //end for LogicalSocketCount
+          }
+
+          if (TempFlag1) {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              //
+              //Compare
+              //
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
+                TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
+              }
+              if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
+                TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
+                TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
+                TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
+              }
+            }
+            // Modify (Pi) CPU COF and Power for all the CPUs
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power    = TempPowerArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
+              PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv   = TempIddDivArray[TotalIterations];
+              TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
+            }
+          } else {
+            for (i = 0; i < LogicalSocketCount; i++) {
+              CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
+              for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) {
+                PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
+              }
+            }
+          }
+          TotalIterations++;
+        } while (TempFlag1);
+      } // else
+    } // if(!AllCoreHaveMaxOnePStateFlag)
+
+    PStateBufferPtr[0].InitStruct = 1;
+  } // CurrentCore
+
+
+  // Update the pState MSRs
+  // This can be done only by individual core
+  StartPstateMsrModify (PStateStrucPtr, StdHeader);
+
+  //----------------------------------------------------------------------------------
+  // STEP - 8
+  //----------------------------------------------------------------------------------
+  // Place all cores into a valid COF and VID configuration corresponding to an
+  // enabled P-state:
+  // 8_a) Select an enabled P-state != to the P-state pointed to by
+  //      MSRC001_0063[CurPstate] for each core.
+  // 8_b) Transition all cores to the selected P-states by writing the Control value
+  //      from the_PSS object corresponding to the selected P-state to
+  //      MSRC001_0062[PstateCmd].
+  // 8_c) Wait for all cores to report the Status value from the _PSS object
+  //      corresponding to the selected P-state in MSRC001_0063[CurPstate].
+  //
+  PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PutAllCoreInPState0
+ *
+ *  Description:
+ *    This function will put core pstate to p0.
+ *
+ *  Parameters:
+ *    @param[in,out]    *PStateBufferPtr
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+PutAllCoreInPState0 (
+  IN OUT   PSTATE_LEVELING    *PStateBufferPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0;
+  TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  PutCoreInPState0 (PStateBufferPtr, StdHeader);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CorePstateRegModify
+ *
+ *  Description:
+ *    This function will setting the Pstate MSR to each APs base on Pstate Buffer.
+ *    Note: This function should be called for every core in the system.
+ *
+ *  Parameters:
+ *    @param[in,out]    *CpuAmdPState
+ *    @param[in]        *StdHeader
+ *
+ *    @retval          VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+CorePstateRegModify (
+  IN       VOID               *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  FamilySpecificServices = NULL;
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->SetPStateLevelReg  (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader);
+
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will set msr on all cores of all nodes.
+ *
+ * @param[in]     CpuAmdPState  @todo describe
+ * @param[in]     StdHeader     Header for library and services.
+ *
+ * @retval        AGESA_SUCCESS  Always succeeds
+ *
+ */
+AGESA_STATUS
+StartPstateMsrModify (
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  BscSocket;
+  UINT32                  Ignored;
+  UINT32                  BscCore;
+  UINT32                  Core;
+  UINT32                  Socket;
+  UINT32                  NumberOfSockets;
+  UINT32                  NumberOfCores;
+  AGESA_STATUS            IgnoredSts;
+
+  TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify;
+  TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1);
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
+  TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
+
+  IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
+  NumberOfSockets = GetPlatformNumberOfSockets ();
+
+  CorePstateRegModify (CpuAmdPState, StdHeader);
+
+  for (Socket = 0; Socket < NumberOfSockets; Socket++) {
+    if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
+      for (Core = 0; Core < NumberOfCores; Core++) {
+        if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
+          ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
+        }
+      }
+    }
+  }
+
+  return AGESA_SUCCESS;
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CpuGetPStateLevelStructure
+ *
+ *  Description:
+ *    Based on the LogicalSocketNumber, this function will return a pointer
+ *      point to the accurate offset of the PSTATE_LEVELING structure.
+ *
+ *  Parameters:
+ *    @param[in,out]          *PStateBufferPtr
+ *    @param[in]              *CpuAmdPState
+ *    @param[in]              LogicalSocketNumber
+ *    @param[in]              *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CpuGetPStateLevelStructure (
+     OUT   PSTATE_LEVELING     **PStateBufferPtr,
+  IN       S_CPU_AMD_PSTATE    *CpuAmdPState,
+  IN       UINT32              LogicalSocketNumber,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  PSTATE_LEVELING         *PStateBufferPtrTmp;
+  UINT32                  i;
+
+  if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc;
+
+  for (i = 1; i <= LogicalSocketNumber; i++) {
+    PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes));
+  }
+
+  *PStateBufferPtr = PStateBufferPtrTmp;
+
+  return AGESA_SUCCESS;
+}
+
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  PutCoreInPState0
+ *
+ *  Description:
+ *    This function will take the CPU core into P0
+ *
+ *  Parameters:
+ *    @param[in]         *PStateBuffer
+ *    @param[in]         *StdHeader
+ *
+ *    @retval         VOID
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+VOID
+STATIC
+PutCoreInPState0 (
+  IN       VOID   *PStateBuffer,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_SPECIFIC_SERVICES   *FamilySpecificServices;
+  PSTATE_LEVELING         *PStateBufferPtr;
+
+  PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
+
+  if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) ||
+     (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) {
+    return;
+  }
+
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+
+  FamilySpecificServices->TransitionPstate  (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
new file mode 100755
index 0000000000..ed4eb02144
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.c
@@ -0,0 +1,821 @@
+/**
+ * @file
+ *
+ * AMD PSTATE, ACPI table related API functions.
+ *
+ * Contains code that generates the _PSS, _PCT, and other ACPI tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionPstate.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "heapManager.h"
+#include "Ids.h"
+#include "Filecode.h"
+#include "GeneralServices.h"
+#include "cpuPstateTables.h"
+#include "cpuFeatures.h"
+#include "cpuC6State.h"
+#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_PSTATE_LATE_CONFIGURATION    OptionPstateLateConfiguration;  // global user config record
+extern CPU_FAMILY_SUPPORT_TABLE            PstateFamilyServiceTable;
+extern CPU_FAMILY_SUPPORT_TABLE            C6FamilyServiceTable;
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuSsdtHdrStruct =
+{
+  {'S','S','D','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'P','O','W','E','R','N','O','W'},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PStateLevelingMain (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+AGESA_STATUS
+CreateAcpiTablesMain (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+AGESA_STATUS
+CreateAcpiTablesStub (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  );
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CalAcpiTablesSize
+ *
+ *  Description:
+ *    This function will calculate the size of ACPI PState tables
+ *
+ *  Parameters:
+ *    @param[in]     *AmdPstatePtr
+ *    @param[in]     *PlatformConfig
+ *    @param[in]     *StdHeader
+ *
+ *    @retval      UINT32
+ *
+ *---------------------------------------------------------------------------------------
+ */
+STATIC UINT32
+CalAcpiTablesSize (
+  IN       S_CPU_AMD_PSTATE       *AmdPstatePtr,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32               ScopeSize;
+  UINT32               CoreCount;
+  UINT32               SocketCount;
+  UINT32               MaxCoreNumberInCurrentSocket;
+  UINT32               MaxSocketNumberInSystem;
+  UINT32               MaxPstateNumberInCurrentCore;
+  UINT32               CstObjSize;
+  PSTATE_LEVELING      *PStateLevelingBufferStructPtr;
+  C6_FAMILY_SERVICES   *C6FamilyServices;
+
+  ScopeSize = sizeof (ACPI_TABLE_HEADER);
+  CstObjSize = 0;
+  C6FamilyServices = NULL;
+
+  PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
+  MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem;
+
+  if (IsFeatureEnabled (C6Cstate, PlatformConfig, StdHeader)) {
+    GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&C6FamilyServices, StdHeader);
+    CstObjSize = C6FamilyServices->GetAcpiCstObj ();
+  }
+
+  for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) {
+    MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode;
+    for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) {
+      MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1;
+      ScopeSize += (PCT_STRUCT_SIZE +
+                    PSS_HEADER_STRUCT_SIZE +
+                    (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) +
+                    XPSS_HEADER_STRUCT_SIZE +
+                    (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) +
+                    PSD_HEADER_STRUCT_SIZE +
+                    PSD_BODY_STRUCT_SIZE +
+                    PPC_HEADER_BODY_STRUCT_SIZE) + (SCOPE_STRUCT_SIZE - 1) +
+                    CstObjSize;
+
+    }
+    ScopeSize += MaxCoreNumberInCurrentSocket;
+    PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+  }
+
+  AmdPstatePtr->SizeOfBytes = ScopeSize;
+
+  return ScopeSize;
+}
+
+/**
+ *---------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTables
+ *
+ *  Description:
+ *    This function will populate the ACPI PState tables
+ *    This function should be called only from BSP
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval      AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+CreateAcpiTables (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader);
+  return ((*(OptionPstateLateConfiguration.PstateFeature)) (StdHeader, PlatformConfig, SsdtPtr));
+  // Note: Split config struct into PEI/DXE halves. This one is DXE.
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTablesStub
+ *
+ *  Description:
+ *     This is the default routine for use when the PState option is NOT requested.
+ *      The option install process will create and fill the transfer vector with
+ *      the address of the proper routine (Main or Stub). The link optimizer will
+ *      strip out of the .DLL the routine that is not used.
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CreateAcpiTablesStub (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/**--------------------------------------------------------------------------------------
+ *
+ *  CreateAcpiTablesMain
+ *
+ *  Description:
+ *     This is the common routine for creating the ACPI information tables.
+ *
+ *  Parameters:
+ *    @param[in]       StdHeader          Handle to config for library and services
+ *    @param[in]       PlatformConfig     Contains the power cap parameter
+ *    @param[in,out]   SsdtPtr            ACPI SSDT table pointer
+ *
+ *    @retval         AGESA_STATUS
+ *
+ *---------------------------------------------------------------------------------------
+ **/
+AGESA_STATUS
+CreateAcpiTablesMain (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SsdtPtr
+  )
+{
+  UINT32                 i;
+  UINT32                 j;
+  UINT32                 k;
+  UINT32                 TempVar8_a;
+  UINT32                 PStateCount;
+  UINT32                 CoreCount;
+  UINT32                 CoreCount1;
+  UINT32                 SocketCount;
+  UINT32                 ScopeSize;
+  UINT32                 TempVar_a;
+  UINT32                 TempVar_b;
+  UINT32                 TempVar_c;
+  UINT32                 TempVar_d;
+  PCI_ADDR               PciAddress;
+  UINT32                 TransAndBusMastLatency;
+  UINT32                 MaxCorePerNode;
+  UINT8                  PStateMaxValueOnCurrentCore;
+  UINT8                  *IntermediatePtr;
+  PSTATE_LEVELING        *PStateLevelingBufferStructPtr;
+  AMD_CONFIG_PARAMS      *AmdConfigParamsStructPtr;
+  SCOPE                  *ScopeAcpiTablesStructPtr;
+  SCOPE                  *ScopeAcpiTablesStructPtrTemp;
+  PCT_HEADER_BODY        *pPctAcpiTables;
+  PSS_HEADER             *pPssHeaderAcpiTables;
+  PSS_BODY               *pPssBodyAcpiTables;
+  XPSS_HEADER            *pXpssHeaderAcpiTables;
+  XPSS_BODY              *pXpssBodyAcpiTables;
+  PSD_HEADER             *pPsdHeaderAcpiTables;
+  PSD_BODY               *pPsdBodyAcpiTables;
+  PPC_HEADER_BODY        *pPpcHeaderBodyAcpiTables;
+  AGESA_BUFFER_PARAMS    AgesaBuffer;
+  LOCATE_HEAP_PTR        LocateHeapParams;
+  S_CPU_AMD_PSTATE       *AmdPstatePtr;
+  BOOLEAN                PstateCapEnable;
+  UINT32                 PstateCapInputMilliWatts;
+  UINT8                  PstateCapLevelSupport;
+  BOOLEAN                PstateCapLevelSupportDetermined;
+  UINT8                  LocalApicId;
+  AGESA_STATUS           AgesaStatus;
+  AGESA_STATUS           IgnoredStatus;
+  CPU_SPECIFIC_SERVICES  *FamilySpecificServices;
+  PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
+  BOOLEAN                IsPsdDependent;
+  C6_FAMILY_SERVICES     *C6FamilyServices;
+  //
+  //Initialize local variables
+  //
+  AmdConfigParamsStructPtr = StdHeader;
+  PstateCapEnable = FALSE;
+  PstateCapInputMilliWatts = PlatformConfig->PowerCeiling;
+  PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP;
+  PstateCapLevelSupportDetermined = TRUE;
+  LocalApicId = 0;
+  AgesaStatus = AGESA_SUCCESS;
+  TempVar_c = 0;
+  ScopeAcpiTablesStructPtrTemp = NULL;
+  TransAndBusMastLatency = 0;
+  PStateCount = 0;
+  IsPsdDependent = !(PlatformConfig->ForcePstateIndependent);
+  FamilyServices = NULL;
+  C6FamilyServices = NULL;
+
+  ASSERT (IsBsp (StdHeader, &IgnoredStatus));
+
+  //
+  //Locate P-state gathered data heap.
+  //
+  LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
+
+  AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader);
+  if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
+    return AGESA_ERROR;
+  }
+  AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader);
+
+  AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr;
+  PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
+
+  //
+  // Check if we need to create ACPI tables
+  //
+  if (PStateLevelingBufferStructPtr[0].CreateAcpiTables == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  //
+  //Allocate rough buffer for AcpiTable, if AcpiPstateBufferPtr is NULL
+  //
+  if (*SsdtPtr == NULL) {
+    AgesaBuffer.StdHeader = *StdHeader;
+    //
+    //Do not know the actual size.. pre-calculate it.
+    //
+    AgesaBuffer.BufferLength = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader);
+    AgesaBuffer.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader);
+    *SsdtPtr = AgesaBuffer.BufferPointer;
+  }
+
+  //SSDT header
+  LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+
+  IntermediatePtr = (UINT8 *) *SsdtPtr;
+  ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)];
+
+  SocketCount = AmdPstatePtr->TotalSocketInSystem;
+
+  // Initialize data variables
+  ScopeSize = 0;
+  CoreCount = 0;
+  for (i = 0; i < SocketCount; i++) {
+
+    MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode;
+
+    for (j = 0; j < MaxCorePerNode; j++) {
+
+      //
+      //Check Pstate Capability enable
+      //
+      if (PstateCapInputMilliWatts != 0) {
+        PstateCapEnable = TRUE;
+        PstateCapLevelSupportDetermined = FALSE;
+      }
+
+      PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue;
+
+      CoreCount++;
+      // Set Name Scope for CPU0, 1, 2, ..... n
+      // CPU0 to CPUn will name  as  C000 to Cnnn
+      // -----------------------------------------
+      ScopeAcpiTablesStructPtr->ScopeOpcode      = SCOPE_OPCODE;
+      // This value will be filled at the end of this function
+      // Since at this time, we don't know how many  Pstates we
+      // would have
+      ScopeAcpiTablesStructPtr->ScopeLength      = 0;
+      ScopeAcpiTablesStructPtr->ScopeValue1      = SCOPE_VALUE1;
+      ScopeAcpiTablesStructPtr->ScopeValue2      = SCOPE_VALUE2;
+      ScopeAcpiTablesStructPtr->ScopeNamePt1a__  = SCOPE_NAME__;
+      if (PlatformConfig->ProcessorScopeInSb) {
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_P  = SCOPE_NAME_S;
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_R  = SCOPE_NAME_B;
+      } else {
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_P  = SCOPE_NAME_P;
+        ScopeAcpiTablesStructPtr->ScopeNamePt1a_R  = SCOPE_NAME_R;
+      }
+      ScopeAcpiTablesStructPtr->ScopeNamePt1b__  = SCOPE_NAME__;
+
+      ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z'))
+      ASSERT (((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z')) || \
+              ((PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9')) || \
+              (PlatformConfig->ProcessorScopeName1 == '_'))
+
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_C  = PlatformConfig->ProcessorScopeName0;
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_P  = PlatformConfig->ProcessorScopeName1;
+
+      TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F;
+      ScopeAcpiTablesStructPtr->ScopeNamePt2a_U  = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
+
+      TempVar8_a = (CoreCount - 1) & 0x0F;
+      if (TempVar8_a < 0xA) {
+        ScopeAcpiTablesStructPtr->ScopeNamePt2a_0  = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
+      } else {
+        ScopeAcpiTablesStructPtr->ScopeNamePt2a_0  = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA);
+      }
+
+      //
+      // Increment and typecast the pointer
+      //
+      ScopeAcpiTablesStructPtr++;
+      pPctAcpiTables = (PCT_HEADER_BODY *) ScopeAcpiTablesStructPtr;
+      ScopeAcpiTablesStructPtr--;
+      ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr;
+      ScopeAcpiTablesStructPtrTemp++;
+
+      if (OptionPstateLateConfiguration.CfgPstatePct) {
+        //
+        // Set _PCT Table
+        // --------------
+        pPctAcpiTables->NameOpcode              = NAME_OPCODE;
+        pPctAcpiTables->PctName_a__             = PCT_NAME__;
+        pPctAcpiTables->PctName_a_P             = PCT_NAME_P;
+        pPctAcpiTables->PctName_a_C             = PCT_NAME_C;
+        pPctAcpiTables->PctName_a_T             = PCT_NAME_T;
+        pPctAcpiTables->Value1                  = PCT_VALUE1;
+        pPctAcpiTables->Value2                  = PCT_VALUE2;
+        pPctAcpiTables->Value3                  = PCT_VALUE3;
+        pPctAcpiTables->GenericRegDescription1  = GENERIC_REG_DESCRIPTION;
+        pPctAcpiTables->Length1                 = PCT_LENGTH;
+        pPctAcpiTables->AddressSpaceId1         = PCT_ADDRESS_SPACE_ID;
+        pPctAcpiTables->RegisterBitWidth1       = PCT_REGISTER_BIT_WIDTH;
+        pPctAcpiTables->RegisterBitOffset1      = PCT_REGISTER_BIT_OFFSET;
+        pPctAcpiTables->Reserved1               = PCT_RESERVED;
+        pPctAcpiTables->ControlRegAddressLo     = PCT_CONTROL_REG_LO;
+        pPctAcpiTables->ControlRegAddressHi     = PCT_CONTROL_REG_HI;
+        pPctAcpiTables->Value4                  = PCT_VALUE4;
+        pPctAcpiTables->Value5                  = PCT_VALUE5;
+        pPctAcpiTables->GenericRegDescription2  = GENERIC_REG_DESCRIPTION;
+        pPctAcpiTables->Length2                 = PCT_LENGTH;
+        pPctAcpiTables->AddressSpaceId2         = PCT_ADDRESS_SPACE_ID;
+        pPctAcpiTables->RegisterBitWidth2       = PCT_REGISTER_BIT_WIDTH;
+        pPctAcpiTables->RegisterBitOffset2      = PCT_REGISTER_BIT_OFFSET;
+        pPctAcpiTables->Reserved2               = PCT_RESERVED;
+        pPctAcpiTables->StatusRegAddressLo      = PCT_STATUS_REG_LO;
+        pPctAcpiTables->StatusRegAddressHi      = PCT_STATUS_REG_HI;
+        pPctAcpiTables->Value6                  = PCT_VALUE6;
+
+        // Set _PSS Table - START
+        //------------------------
+
+        // Increment and then typecast the pointer
+        pPctAcpiTables++;
+        TempVar_c += PCT_STRUCT_SIZE;
+
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPctAcpiTables;
+      } // end of OptionPstateLateConfiguration.CfgPstatePct
+
+      pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstatePss) {
+        //
+        // Set _PSS Header
+        // Note: Set the pssLength and numOfItemsInPss later
+        //---------------------------------------------------
+        pPssHeaderAcpiTables->NameOpcode      = NAME_OPCODE;
+        pPssHeaderAcpiTables->PssName_a__     = PSS_NAME__;
+        pPssHeaderAcpiTables->PssName_a_P     = PSS_NAME_P;
+        pPssHeaderAcpiTables->PssName_a_S     = PSS_NAME_S;
+        pPssHeaderAcpiTables->PssName_b_S     = PSS_NAME_S;
+        pPssHeaderAcpiTables->PkgOpcode       = PACKAGE_OPCODE;
+
+        pPssHeaderAcpiTables++;
+      }// end of PSS Header if OptionPstateLateConfiguration.CfgPstatePss
+
+      pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstatePss) {
+        // Restore the pPssHeaderAcpiTables
+        pPssHeaderAcpiTables--;
+
+        // Set _PSS Body
+        //---------------
+        PStateCount = 0;
+
+        //
+        //Calculate pci address for socket only
+        //
+        GetPciAddress (StdHeader, (UINT32) PStateLevelingBufferStructPtr->SocketNumber, 0, &PciAddress, &IgnoredStatus);
+        TransAndBusMastLatency = 0;
+        GetCpuServicesOfSocket ((UINT32) PStateLevelingBufferStructPtr->SocketNumber, &FamilySpecificServices, StdHeader);
+        ASSERT (FamilySpecificServices != NULL);
+        FamilySpecificServices->GetPstateLatency (FamilySpecificServices,
+                                                  PStateLevelingBufferStructPtr,
+                                                  &PciAddress,
+                                                  &TransAndBusMastLatency,
+                                                  StdHeader);
+
+        for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+          if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+            pPssBodyAcpiTables->PkgOpcode           = PACKAGE_OPCODE;
+            pPssBodyAcpiTables->PkgLength           = PSS_PKG_LENGTH;
+            pPssBodyAcpiTables->NumOfElements       = PSS_NUM_OF_ELEMENTS;
+            pPssBodyAcpiTables->DwordPrefixOpcode1  = DWORD_PREFIX_OPCODE;
+
+            pPssBodyAcpiTables->Frequency           =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
+
+            pPssBodyAcpiTables->DwordPrefixOpcode2  = DWORD_PREFIX_OPCODE;
+
+            pPssBodyAcpiTables->Power               =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].Power;
+
+            if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) {
+              PstateCapLevelSupport = (UINT8) k;
+              PstateCapLevelSupportDetermined = TRUE;
+            }
+
+            pPssBodyAcpiTables->DwordPrefixOpcode3  = DWORD_PREFIX_OPCODE;
+
+            pPssBodyAcpiTables->TransitionLatency   = TransAndBusMastLatency;
+            pPssBodyAcpiTables->DwordPrefixOpcode4  = DWORD_PREFIX_OPCODE;
+            pPssBodyAcpiTables->BusMasterLatency    = TransAndBusMastLatency;
+            pPssBodyAcpiTables->DwordPrefixOpcode5  = DWORD_PREFIX_OPCODE;
+            pPssBodyAcpiTables->Control             = k;
+            pPssBodyAcpiTables->DwordPrefixOpcode6  = DWORD_PREFIX_OPCODE;
+            pPssBodyAcpiTables->Status              = k;
+
+            pPssBodyAcpiTables++;
+            PStateCount++;
+          }
+
+        } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+        if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) {
+          PstateCapLevelSupport = PStateMaxValueOnCurrentCore;
+        }
+
+        // Set _PSS Header again
+        // Now Set pssLength and numOfItemsInPss
+        //---------------------------------------
+        TempVar_a = (PStateCount * PSS_BODY_STRUCT_SIZE) + 3;
+        if (TempVar_a > 63) {
+          TempVar_b = TempVar_a;
+          TempVar_d = ((TempVar_b << 4) & 0x0000FF00);
+          TempVar_d = TempVar_d | ((TempVar_b & 0x0000000F) | 0x00000040);
+          TempVar_a = (UINT16) TempVar_d;
+        }
+
+        pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a;
+        pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PStateCount;
+        TempVar_c += (PSS_HEADER_STRUCT_SIZE + (PStateCount * PSS_BODY_STRUCT_SIZE));
+
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPssBodyAcpiTables;
+      } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss
+
+      //
+      // Set XPSS Table - START
+      //------------------------
+      // Typecast the pointer
+      pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstateXpss) {
+        // Set XPSS Header
+        // Note: Set the pssLength and numOfItemsInPss later
+        //---------------------------------------------------
+        pXpssHeaderAcpiTables->NameOpcode       = NAME_OPCODE;
+        pXpssHeaderAcpiTables->XpssName_a_X     = PSS_NAME_X;
+        pXpssHeaderAcpiTables->XpssName_a_P     = PSS_NAME_P;
+        pXpssHeaderAcpiTables->XpssName_a_S     = PSS_NAME_S;
+        pXpssHeaderAcpiTables->XpssName_b_S     = PSS_NAME_S;
+        pXpssHeaderAcpiTables->PkgOpcode        = PACKAGE_OPCODE;
+
+        // Increment and then typecast the pointer
+        pXpssHeaderAcpiTables++;
+      }//end of XPSS header if OptionPstateLateConfiguration.CfgPstateXpss
+
+      pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables;
+
+      if (OptionPstateLateConfiguration.CfgPstateXpss) {
+        // Restore the pXpssHeaderAcpiTables
+        pXpssHeaderAcpiTables--;
+
+        // Set XPSS Body
+        //---------------
+        for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
+          if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
+            pXpssBodyAcpiTables->PkgOpcode          = PACKAGE_OPCODE;
+            pXpssBodyAcpiTables->PkgLength          = XPSS_PKG_LENGTH;
+            pXpssBodyAcpiTables->NumOfElements      = XPSS_NUM_OF_ELEMENTS;
+            pXpssBodyAcpiTables->XpssValueTbd       = 04;
+            pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE;
+
+            pXpssBodyAcpiTables->Frequency          =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
+
+            pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE;
+
+            pXpssBodyAcpiTables->Power              =
+            PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].Power;
+
+            pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE;
+
+            pXpssBodyAcpiTables->TransitionLatency  = TransAndBusMastLatency;
+            pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE;
+            pXpssBodyAcpiTables->BusMasterLatency   = TransAndBusMastLatency;
+            pXpssBodyAcpiTables->ControlBuffer      = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->ControlLo          = k;
+            pXpssBodyAcpiTables->ControlHi          = 0;
+            pXpssBodyAcpiTables->StatusBuffer       = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->StatusLo           = k;
+            pXpssBodyAcpiTables->StatusHi           = 0;
+            pXpssBodyAcpiTables->ControlMaskBuffer  = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->ControlMaskLo      = 0;
+            pXpssBodyAcpiTables->ControlMaskHi      = 0;
+            pXpssBodyAcpiTables->StatusMaskBuffer   = XPSS_ACPI_BUFFER;
+            pXpssBodyAcpiTables->StatusMaskLo       = 0;
+            pXpssBodyAcpiTables->StatusMaskHi       = 0;
+
+            pXpssBodyAcpiTables++;
+          }
+        } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
+
+        // Set XPSS Header again
+        // Now Set pssLength and numOfItemsInPss
+        //---------------------------------------
+        TempVar_a = (PStateCount * XPSS_BODY_STRUCT_SIZE) + 3;
+        if (TempVar_a > 63) {
+          TempVar_b = TempVar_a;
+          TempVar_d = ((TempVar_b << 4) & 0x0000FF00);
+          TempVar_d = TempVar_d | ((TempVar_b & 0x0000000F) | 0x00000040);
+          TempVar_a = (UINT16) TempVar_d;
+        }
+
+        pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a;
+        pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PStateCount;
+        TempVar_c += (XPSS_HEADER_STRUCT_SIZE + (PStateCount * XPSS_BODY_STRUCT_SIZE));
+
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pXpssBodyAcpiTables;
+      } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss
+
+      //
+      // Set _PSD Table - START
+      //------------------------
+      // Typecast the pointer
+      pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables;
+
+      //
+      // Get Total Cores Per Node
+      /// @todo Maybe this should ask for single core Sockets not single core nodes?
+      if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBufferStructPtr->SocketNumber, &CoreCount1, AmdConfigParamsStructPtr)) {
+        if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd)) {
+          //
+          // Set _PSD Header
+          //-----------------
+          pPsdHeaderAcpiTables->NameOpcode    = NAME_OPCODE;
+          pPsdHeaderAcpiTables->PkgOpcode     = PACKAGE_OPCODE;
+          pPsdHeaderAcpiTables->PsdLength     = PSD_HEADER_LENGTH;
+          pPsdHeaderAcpiTables->Value1        = PSD_VALUE1;
+
+          // Set _PSD Header
+          pPsdHeaderAcpiTables->PsdName_a__   = PSD_NAME__;
+          pPsdHeaderAcpiTables->PsdName_a_P   = PSD_NAME_P;
+          pPsdHeaderAcpiTables->PsdName_a_S   = PSD_NAME_S;
+          pPsdHeaderAcpiTables->PsdName_a_D   = PSD_NAME_D;
+
+          // Typecast the pointer
+          pPsdHeaderAcpiTables++;
+          TempVar_c += PSD_HEADER_STRUCT_SIZE;
+        }  // end of PSD Header if (CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd)
+     }
+      pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables;
+
+      if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd)) {
+        pPsdHeaderAcpiTables--;
+        //
+        // Set _PSD Body
+        //----------------
+        pPsdBodyAcpiTables->PkgOpcode           = PACKAGE_OPCODE;
+        pPsdBodyAcpiTables->PkgLength           = PSD_PKG_LENGTH;
+        pPsdBodyAcpiTables->NumOfEntries        = NUM_OF_ENTRIES;
+        pPsdBodyAcpiTables->BytePrefixOpcode1   = BYTE_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->PsdNumOfEntries     = PSD_NUM_OF_ENTRIES;
+        pPsdBodyAcpiTables->BytePrefixOpcode2   = BYTE_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->PsdRevision         = PSD_REVISION;
+        pPsdBodyAcpiTables->DwordPrefixOpcode1  = DWORD_PREFIX_OPCODE;
+        //
+        //Get ApicId from AMD CPU general service.
+        //Basically, DependencyDomain should be LocalApicId for each core PSD independent.
+        //
+        GetApicId (StdHeader, (UINT32) PStateLevelingBufferStructPtr->SocketNumber, j, &LocalApicId, &AgesaStatus);
+
+        GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader);
+        if (FamilyServices != NULL) {
+          IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader);
+        }
+
+        if (IsPsdDependent) {
+          pPsdBodyAcpiTables->DependencyDomain    = PSD_DEPENDENCY_DOMAIN;
+          pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_SW_ALL;
+          pPsdBodyAcpiTables->NumOfProcessors     = CoreCount1;
+        } else {
+          pPsdBodyAcpiTables->DependencyDomain    = LocalApicId;
+          pPsdBodyAcpiTables->CoordinationType    = PSD_COORDINATION_TYPE_SW_ANY;
+          pPsdBodyAcpiTables->NumOfProcessors     = PSD_NUM_OF_PROCESSORS;
+        }
+
+        pPsdBodyAcpiTables->DwordPrefixOpcode2  = DWORD_PREFIX_OPCODE;
+        pPsdBodyAcpiTables->DwordPrefixOpcode3  = DWORD_PREFIX_OPCODE;
+
+        pPsdBodyAcpiTables++;
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPsdBodyAcpiTables;
+        TempVar_c += PSD_BODY_STRUCT_SIZE;
+      }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd)
+
+      //
+      // Set _PPC Table - START
+      //------------------------
+
+      // Typecast the pointer
+
+      pPpcHeaderBodyAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables;
+
+      // Set _PPC Header and Body
+      //--------------------------
+      if (OptionPstateLateConfiguration.CfgPstatePpc) {
+        pPpcHeaderBodyAcpiTables->NameOpcode            = NAME_OPCODE;
+        pPpcHeaderBodyAcpiTables->PpcName_a__           = PPC_NAME__;
+        pPpcHeaderBodyAcpiTables->PpcName_a_P           = PPC_NAME_P;
+        pPpcHeaderBodyAcpiTables->PpcName_b_P           = PPC_NAME_P;
+        pPpcHeaderBodyAcpiTables->PpcName_a_C           = PPC_NAME_C;
+        pPpcHeaderBodyAcpiTables->Value1                = PPC_VALUE1;
+
+        pPpcHeaderBodyAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport;
+        TempVar_c += PPC_HEADER_BODY_STRUCT_SIZE;
+        // Increment and typecast the pointer
+        pPpcHeaderBodyAcpiTables++;
+        ScopeAcpiTablesStructPtrTemp = (SCOPE *) pPpcHeaderBodyAcpiTables;
+      }// end of OptionPstateLateConfiguration.CfgPstatePpc
+
+      // If C6 is enabled, generate the corresponding ACPI object for it
+      if (IsFeatureEnabled (C6Cstate, PlatformConfig, StdHeader)) {
+        GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, (CONST VOID **)&C6FamilyServices, StdHeader);
+        C6FamilyServices->CreateAcpiCstObj ((VOID *) &ScopeAcpiTablesStructPtrTemp, StdHeader);
+        TempVar_c += C6FamilyServices->GetAcpiCstObj ();
+      }
+
+      //
+      // Now update the SCOPE Length field
+      //
+      {
+        TempVar_c += (SCOPE_STRUCT_SIZE - 1);
+        ScopeSize += TempVar_c;
+
+        TempVar_d = ((TempVar_c << 4) & 0x0000FF00);
+        TempVar_d |= ((TempVar_c & 0x0000000F) | 0x00000040);
+        TempVar_a = TempVar_d;
+        ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a;
+        TempVar_c = 0;
+      }
+
+      // Increment and typecast the pointer
+      ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp;
+
+    } // for (j = 0; j < MPPSTATE_MAX_CORES_PER_NODE; j++)
+
+    //
+    //Calculate next node buffer address
+    //
+    PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
+
+  } // for (i = 0; i < NodeCount; i++)
+
+  //Update SSDT header Checksum
+  ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER));
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
new file mode 100755
index 0000000000..af55edfd67
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuPstateTables.h
@@ -0,0 +1,120 @@
+/**
+ * @file
+ *
+ * AMD AGESA CPU Pstate Table Functions declarations.
+ *
+ * Contains code that declares the AGESA CPU _PSS related APIs
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Feature
+ * @e \$Revision: 13766 $   @e \$Date: 2009-05-14 07:22:59 +0800 (Thu, 14 May 2009) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+#ifndef _CPU_PSTATE_TABLES_H_
+#define _CPU_PSTATE_TABLES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+// Forward declaration.
+typedef struct _PSTATE_CPU_FAMILY_SERVICES PSTATE_CPU_FAMILY_SERVICES;
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                    T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Family specific call to check if Pstate PSD is dependent.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in,out] PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               PSD is dependent.
+ * @retval       FALSE              PSD is independent.
+ *
+ */
+typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN OUT   PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT;
+
+/**
+ *  Family specific call to set core TscFreqSel.
+ *
+ * @param[in]     PstateCpuFamilyServices  Pstate CPU services.
+ * @param[in]     StdHeader          Config Handle for library, services.
+ *
+ */
+typedef VOID F_PSTATE_SET_TSC_FREQ_SEL (
+  IN       PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL;
+
+/**
+ * Provide the interface to the PSD dependent Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _PSTATE_CPU_FAMILY_SERVICES {
+  UINT16          Revision;                                         ///< Interface version
+  // Public Methods.
+  PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent;                  ///< Method: Family specific call to check if PSD is dependent.
+  PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel;                      ///< Method: Family specific call to set core TscFreqSel.
+};
+
+
+/*----------------------------------------------------------------------------------------
+ *                          F U N C T I O N S     P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _CPU_PSTATE_TABLES_H_
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
new file mode 100755
index 0000000000..1447c450e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSlit.c
@@ -0,0 +1,370 @@
+/**
+ * @file
+ *
+ * AMD SLIT, ACPI table related API functions.
+ *
+ * Contains code that generates the SLIT table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SLIT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionSlit.h"
+#include "heapManager.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "Topology.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration;  // global user config record
+
+STATIC ACPI_TABLE_HEADER  ROMDATA CpuSlitHdrStruct =
+{
+  {'S','L','I','T'},
+  0,
+  1,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'F','1','0',' ',' ',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1
+};
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+AcpiSlitHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     E X P O R T E D     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiSlitStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+AGESA_STATUS
+GetAcpiSlitMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+   );
+AGESA_STATUS
+ReleaseSlitBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+AGESA_STATUS
+ReleaseSlitBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete SLIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiSlit (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader);
+  return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the SLIT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiSlitStub (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function generates a complete SLIT table into a memory buffer.
+ * After completion, this table must be set by the system BIOS into its
+ * internal ACPI namespace, and linked into the RSDT/XSDT
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in]       PlatformConfig   Config handle for platform specific information
+ *    @param[in, out]  SlitPtr          Point to Slit Struct including buffer address and length
+ *
+ *    @retval          UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiSlitMain (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+   )
+{
+  UINT8 MaxHops;
+  UINT8 SocketNum;
+  UINT8 i;
+  UINT8 j;
+  UINT8 *BufferPtr;
+  UINT8 *SocketTopologyDataPtr;
+  UINT8 *SocketTopologyPtr;
+  ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr;
+  AGESA_STATUS Flag;
+  ALLOCATE_HEAP_PARAMS AllocStruct;
+
+  MaxHops = 0;
+  SocketTopologyPtr = NULL;
+  Flag = AGESA_ERROR;
+
+  // find out the pointer to the BufferHandle which contains
+  // Node Topology information
+  AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr);
+  if (SocketTopologyPtr == 0) {
+    return (Flag);
+  }
+
+  SocketNum = *SocketTopologyPtr;
+
+  // create a buffer by calling IBV callout routine
+  AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER);
+  AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE;
+  AllocStruct.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) {
+    return (Flag);
+  }
+  *SlitPtr = AllocStruct.BufferPtr;
+
+  //SLIT header
+  LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
+  CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr;
+  CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize;
+  BufferPtr = *SlitPtr;
+
+  Flag = AGESA_SUCCESS;
+  // SLIT body
+  // check if is PfMode (Prober Filer Mode)
+  if (!IsFeatureEnabled (HtAssist, PlatformConfig, StdHeader)) {
+    // probe filter is disabled
+
+    // get MaxHops
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        if (*SocketTopologyDataPtr > MaxHops) {
+          MaxHops = *SocketTopologyDataPtr;
+        }
+        SocketTopologyDataPtr++;
+      }
+    }
+
+    // the Max hop entries have a value of 13
+    // and all other entries have 10.
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        if (*SocketTopologyDataPtr++ == MaxHops) {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13;
+        } else {
+          *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+            AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10;
+        }
+      }
+    }
+  } else {
+    // probe filter is enabled
+
+    // formula : num_hops * 6 + 10
+    SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
+    for (i = 0; i < SocketNum; i++) {
+      for (j = 0; j < SocketNum; j++) {
+        *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
+          AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) =
+          ((*SocketTopologyDataPtr++) * 6) + 10;
+      }
+    }
+  }
+
+  BufferPtr += sizeof (ACPI_TABLE_HEADER);
+  *((UINT64 *) BufferPtr) = (UINT64) SocketNum;
+
+  //Update SLIT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader);
+
+  return (Flag);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Find out the pointer to the BufferHandle which contains
+ * Node Topology information
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in] SocketTopologyPtr      Point to the address of Socket Topology
+ *
+ */
+VOID
+STATIC
+AcpiSlitHBufferFind (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT8 **SocketTopologyPtr
+  )
+{
+  LOCATE_HEAP_PTR LocateBuffer;
+
+  LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) {
+    *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr;
+  }
+
+  return;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseSlitBufferStub
+ *
+ *  Description:
+ *      This is the default routine for use when the SLIT option is NOT requested.
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseSlitBufferStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *  ReleaseSlitBuffer
+ *
+ *  Description:
+ *     Deallocate SLIT buffer
+ *
+ *  Parameters:
+ *    @param[in, out]    *StdHeader
+ *
+ *    @retval         AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+ReleaseSlitBuffer (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader);
+
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
new file mode 100755
index 0000000000..bf136043d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuSrat.c
@@ -0,0 +1,614 @@
+/**
+ * @file
+ *
+ * AMD SRAT, ACPI table related API functions.
+ *
+ * Contains code that Create the APCI SRAT Table after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ***************************************************************************/
+
+
+/*----------------------------------------------------------------------------
+ * This file provides functions, that will generate SRAT tables
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuServices.h"
+#include "OptionSrat.h"
+#include "cpuRegisters.h"
+#include "cpuLateInit.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                          EXPORTED FUNCTIONS
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiSratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+AGESA_STATUS
+GetAcpiSratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration;  // global user config record
+
+#define NodeID 0x60
+#define FOURGB 0x010000
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *  All of the DATA should be defined in _CODE segment.
+ *  Use ROMDATA to specify that it belongs to _CODE.
+ *----------------------------------------------------------------------------
+ */
+STATIC CPU_SRAT_HEADER  ROMDATA CpuSratHdrStruct =
+{
+  {'S','R','A','T'},
+  0,
+  2,
+  0,
+  {'A','M','D',' ',' ',' '},
+  {'F','1','0',' ',' ',' ',' ',' '},
+  1,
+  {'A','M','D',' '},
+  1,
+  1,
+  {0, 0, 0, 0, 0, 0, 0, 0}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8
+STATIC
+*MakeApicEntry (
+  IN UINT8 ApicId,
+  IN UINT8 Domain,
+  IN UINT8 *BufferLocPtr
+  );
+
+UINT8
+STATIC
+*FillMemoryForCurrentNode (
+  IN      UINT8 *PDomain,
+  IN OUT  UINT8 *PDomainForBase640K,
+  IN      UINT8 Node,
+  IN OUT  UINT8 *BufferLocPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader
+  );
+
+UINT8
+STATIC
+*MakeMemEntry (
+  IN UINT8  PDomain,
+  IN UINT8  Node,
+  IN UINT32 Base,
+  IN UINT32 Size,
+  IN UINT8  *BufferLocPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Static Resource Affinity Table
+ * i.e. SRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+CreateAcpiSrat (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader);
+  return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the SRAT option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out] StdHeader      Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiSratStub (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will generate a complete Static Resource Affinity Table
+ * i.e. SRAT into a memory buffer. After completion, this table must be set
+ * by the system BIOS into its internal ACPI name space.
+ *
+ *    @param[in, out] StdHeader         Standard Head Pointer
+ *    @param[in, out] SratPtr           Point to Srat Struct including buffer address and length
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiSratMain (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  )
+{
+  UINT8     *BufferPtr;
+  UINT8     NodeNum;
+  UINT8     NodeCount;
+  UINT8     PDomain;
+  UINT8     PDomainForBase640K;
+  UINT32    Socket;
+  UINT32    Module;
+  UINT32    LowCore;
+  UINT32    HighCore;
+  UINT32    CoreNum;
+  UINT32    RegVal;
+  UINT32    tempVar_32;
+  AMD_APIC_PARAMS ApicParams;
+  PCI_ADDR  PciAddress;
+  CPU_SRAT_HEADER  *CpuSratHeaderStructPtr;
+  AGESA_BUFFER_PARAMS AllocParams;
+
+  // Get Node count
+  PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID);
+  LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader);
+  NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1);
+
+  // The worst-case buffer size to request is for the SRAT table header, one
+  // entree for special region (base 640k block), two memory
+  // regions per node, and APIC entries for each core in the system.
+  tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY))
+               + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY))
+               + (MAX_NUMBER_CORES * sizeof (CPU_SRAT_APIC_ENTRY))));
+
+  if (*SratPtr == NULL) {
+    //
+    // Allocate a buffer by callback function
+    //
+    AllocParams.StdHeader = *StdHeader;
+    AllocParams.BufferLength = tempVar_32;
+    AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AllocParams) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader);
+
+    *SratPtr = AllocParams.BufferPointer;
+  }
+
+  CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr;
+  BufferPtr = (UINT8 *) *SratPtr;
+
+  // Copy acpiSRATHeader -> data buffer
+  LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader);
+
+  BufferPtr += sizeof (CPU_SRAT_HEADER);
+
+  // Place all memory and IO affinity entries
+  NodeNum = 0;
+  PDomain = 0;
+  PDomainForBase640K = 0xFF;
+  ApicParams.StdHeader = *StdHeader;
+  while (NodeNum < NodeCount) {
+    GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader);
+    GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
+    BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader);
+    for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) {
+      ApicParams.Socket = (UINT8) Socket;
+      ApicParams.Core = (UINT8) CoreNum;
+      AmdGetApicId (&ApicParams);
+      if (ApicParams.IsPresent) {
+        BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr);
+      }
+    }
+
+    NodeNum++;
+    PDomain = NodeNum;
+  }
+
+  // Store size in table (current buffer offset - buffer start offset)
+  CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr);
+
+  //Update SSDT header Checksum
+  ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader);
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------
+ *                            L O C A L    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will build Memory entry for current node.
+ * Note that we only create a memory affinity entry if we find one
+ * that matches the current node.  This makes an easier to read table
+ * though it is not necessary.
+ *
+ *    @param[in]      PDomain            Proximity Domain
+ *    @param[in, out] PDomainForBase640K The PDomain for Base 640K
+ *    @param[in]      Node               The number of Node
+ *    @param[in, out] BufferLocPtr       Point to the address of buffer
+ *    @param[in, out] StdHeader          Standard Head Pointer
+ *
+ *    @retval         UINT8 *(New buffer location ptr)
+ */
+UINT8
+STATIC
+*FillMemoryForCurrentNode (
+  IN      UINT8 *PDomain,
+  IN OUT  UINT8 *PDomainForBase640K,
+  IN      UINT8 Node,
+  IN OUT  UINT8 *BufferLocPtr,
+  IN OUT  AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    ValueLimit;
+  UINT32    ValueTOM;
+  BOOLEAN   isModified;
+  UINT8     Domain;
+  UINT32    RegVal;
+  UINT32    DramLeng;
+  UINT32    DramBase;
+  UINT32    DramLimit;
+  UINT32    OffsetRegs;
+  PCI_ADDR  PciAddress;
+  UINT64    MsrValue;
+  UINT32    TopOfMemoryAbove4Gb;
+
+  Domain = *PDomain;
+
+  PciAddress.Address.Segment = 0;
+  PciAddress.Address.Bus = 0;
+  PciAddress.Address.Device = LOW_NODE_DEVICEID;
+  PciAddress.Address.Function = FUNC_1;
+
+  for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) {
+    isModified = FALSE;        // FALSE means normal update procedure
+    // Get DRAM Base Address
+    PciAddress.Address.Register = OffsetRegs;
+    LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader);
+    if ((DramBase & 3) != 3) {
+      // 0:1 set if memory range enabled
+      // Not set, so we don't have an enabled range
+      continue;   // Proceed to next Base register
+    }
+
+    // Get DRAM Limit
+    PciAddress.Address.Register = OffsetRegs + 4;
+    LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader);
+    if (DramLimit == 0xFFFFFFFF) {
+      // Node not installed(all FF's)?
+      continue;   // Proceed to next Base register
+    }
+
+    if ((DramLimit & 0xFF) != Node) {
+      // Check if Destination Node ID is current node
+      continue;   // Proceed to next Base register
+    }
+
+    //    We only add an entry now if detected range belongs to current node/PDomain
+    PciAddress.Address.Register = OffsetRegs + 0x104;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
+
+    DramLimit = (((RegVal & 0xFF) << 16) | (DramLimit >> 16));  // Get DRAM Limit addr [47:24]
+    DramLimit++;                     // Add 1 for potential length
+    DramLimit <<= 8;
+
+    // Get DRAM Base Address
+    PciAddress.Address.Register = OffsetRegs + 0x100;
+    LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
+    DramBase = ((((RegVal & 0xFF) << 24) | (DramBase >> 8)) & 0xFFFFFF00);   // Get DRAM Base Base value [47:24]
+    DramLeng = DramLimit - DramBase;    // Subtract base from limit to get length
+
+    //    Leave hole for conventional memory (Less than 640K).  It must be on CPU 0.
+    if (DramBase == 0) {
+      if (*PDomainForBase640K == 0xFF) {
+        // It is the first time that the range start at 0.
+        // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K
+        BufferLocPtr = MakeMemEntry (
+                         Domain,
+                         Node,
+                         0,              // Base = 0
+                         0xA0000 >> 16,  // Put it into format used in DRAM regs..
+                         BufferLocPtr
+                         );
+        DramBase += 0x10;       // Add 1MB, so range = 1MB to Top of Region
+        DramLeng -= 0x10;       // Also subtract 1MB from the length
+        *PDomainForBase640K = Domain;        // Save Domain number for memory Less than 640K
+      } else {
+        // If No, there are more than one memory range less than 640K, it should that
+        // node interleaving is enabled. All nodes have the same memory ranges
+        // and all cores in these nodes belong to the same domain.
+        *PDomain = *PDomainForBase640K;
+        return (BufferLocPtr);
+      }
+    }
+    LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader);
+    ValueTOM   = (UINT32) MsrValue >> 16;    // Save it in 39:24 format
+    ValueLimit = DramBase + DramLeng;        // We need to know how large region is
+
+    LibAmdMsrRead (SYS_CFG, &MsrValue, StdHeader);
+    if ((MsrValue & BIT21) != 0) {
+      LibAmdMsrRead (TOP_MEM2, &MsrValue, StdHeader);
+      TopOfMemoryAbove4Gb = (UINT32) (MsrValue >> 16);    // Save it in 47:16 format
+    } else {
+      TopOfMemoryAbove4Gb = 0xFFFFFFFF;
+    }
+
+    //  SPECIAL CASES:
+    //
+    //  Several conditions require that we process the values of the memory range differently.
+    //  Here are descriptions of the corner cases.
+    //
+    //  1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole).  For this case,
+    //     the range must be truncated to end at TOM.
+    //  *******************************            *******************************
+    //  *                    *        *      ->    *                             *
+    //  *******************************            *******************************
+    //  2                    TOM      4            2                             TOM
+    //
+    //  2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB.  This is handled by changing the
+    //     start base to 4GB.
+    //          ****************                        **********
+    //          *     *        *      ->                *        *
+    //          ****************                        **********
+    //  TOM     3.8   4        6            TOM   3.8   4        6
+    //
+    //  3. Memory range starts below TOM, ends above 4GB.  For this case, the range must be truncated
+    //     to end at TOM.  Note that this scenario creates two ranges, as the second comparison below
+    //     will find that it ends above 4GB since base and limit have been restored after first truncation,
+    //     and a second range will be written based at 4GB ending at original end address.
+    //  *******************************            ****************          **********
+    //  *              *     *        *      ->    *              *          *        *
+    //  *******************************            ****************          **********
+    //  2              TOM   4        6            2              TOM        4        6
+    //
+    //  4. Memory range starts above TOM, ends below or equal to 4GB.  This invalid range should simply
+    //     be ignored.
+    //          *******
+    //          *     *      ->    < NULL >
+    //          *******
+    //  TOM     3.8   4
+    //
+    //  5. Memory range starts below TOM2, and ends beyond TOM2.  This range must be truncated to TOM2.
+    //  ************************         *******************************
+    //  *              *       *   ->    *                             *
+    //  ************************         *******************************
+    //  768          TOM2   1024         768                        TOM2
+    //
+    //  6. Memory range starts above TOM2.  This invalid range should simply be ignored.
+    //          ********************
+    //          *                  *    ->    < NULL >
+    //          ********************
+    //  TOM2    1024            1280
+
+    if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM))
+        || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) {
+      //   TRUNCATE LOW!!! Shrink entry below TOM...
+      //   Base = DramBase, Size = TOM - DramBase
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) {
+      //   TRUNCATE HIGH!!! Shrink entry above 4GB...
+      //   Size = Base + Size - 4GB, Base = 4GB
+      BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) {
+      //   IGNORE!!!  Entry located entirely within memory hole
+      isModified = TRUE;
+    }
+
+    if ((DramBase < TopOfMemoryAbove4Gb) && (ValueLimit > TopOfMemoryAbove4Gb)) {
+      //   Truncate to TOM2
+      //   Base = DramBase, Size = TOM2 - DramBase
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (TopOfMemoryAbove4Gb - DramBase), BufferLocPtr);
+      isModified = TRUE;
+    }
+
+    if (DramBase >= TopOfMemoryAbove4Gb) {
+      //   IGNORE!!!  Entry located entirely above TOM2
+      isModified = TRUE;
+    }
+
+    //    If special range(isModified), we are done.
+    //    If not, finally write the memory entry.
+    if (isModified == FALSE) {
+      // Finally write the memory entry.
+      BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr);
+    }
+
+  } // for ( OffsetRegs = DRAMBase0; ... )
+
+  return (BufferLocPtr);
+} // FillMemoryForCurrentNode()
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This function will add APIC entry.
+ *
+ *    @param[in]      ApicId            APIC ID number
+ *    @param[in]      Domain            Domain number
+ *    @param[in]      BufferLocPtr      Point to the address of buffer
+ *
+ *    @retval         UINT8 *(New buffer location ptr)
+ */
+UINT8
+STATIC
+*MakeApicEntry (
+  IN      UINT8 ApicId,
+  IN      UINT8 Domain,
+  IN      UINT8 *BufferLocPtr
+  )
+{
+  CPU_SRAT_APIC_ENTRY *psSratApicEntry;
+  UINT8 ReservedBytes;
+
+  psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr;
+
+  psSratApicEntry->Type = AE_APIC;
+  psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY);
+  psSratApicEntry->Domain = Domain;
+  psSratApicEntry->ApicId = ApicId;
+  psSratApicEntry->Flags = ENABLED;
+  psSratApicEntry->LSApicEid = 0;
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) {
+    psSratApicEntry->Reserved[ReservedBytes] = 0;
+  }
+  return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY));
+} // MakeApicEntry
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This function will add Memory entry.
+ *
+ *  Parameters:
+ *    @param[in]  PDomain               Proximity Domain
+ *    @param[in]  Node                  The number of Node
+ *    @param[in]  Base                  Memory Base
+ *    @param[in]  Size                  Memory Size
+ *    @param[in]  BufferLocPtr          Point to the address of buffer
+ *
+ *    @retval       UINT8 * (new buffer location ptr)
+ */
+UINT8
+STATIC
+*MakeMemEntry (
+  IN  UINT8   PDomain,
+  IN  UINT8   Node,
+  IN  UINT32  Base,
+  IN  UINT32  Size,
+  IN  UINT8   *BufferLocPtr
+  )
+{
+  CPU_SRAT_MEMORY_ENTRY *psSratMemEntry;
+  UINT8 ReservedBytes;
+
+  psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr;
+
+  psSratMemEntry->Type = AE_MEMORY;                       // [0] = Memory Entry
+  psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40
+  psSratMemEntry->Domain = PDomain;                            // [2] = Proximity Domain
+
+  // [6-7] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) {
+    psSratMemEntry->Reserved1[ReservedBytes] = 0;
+  }
+
+  // [8-11] = Keep 31:0 of address only -> Base Addr Low
+  psSratMemEntry->BaseAddrLow  = Base << 16;
+
+  // [12-15] = Keep 39:32 of address only -> Base Addr High
+  psSratMemEntry->BaseAddrHigh = Base >> 16;
+
+  // [16-19] = Keep 31:0 of address only -> Length Low
+  psSratMemEntry->LengthAddrLow  = Size << 16;
+
+  // [20-23] = Keep 39:32 of address only -> Length High
+  psSratMemEntry->LengthAddrHigh = Size >> 16;
+
+  // [24-27] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) {
+    psSratMemEntry->Reserved2[ReservedBytes] = 0;
+  }
+
+  // [28-31] = Flags
+  psSratMemEntry->Flags = ENABLED;
+
+  // [32-40] = Reserved
+  for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) {
+    psSratMemEntry->Reserved3[ReservedBytes] = 0;
+  }
+  return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
+} // MakeMemEntry()
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
new file mode 100755
index 0000000000..fb8930269e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuWhea.c
@@ -0,0 +1,276 @@
+/**
+ * @file
+ *
+ * AMD WHEA Table Creation API, and related functions.
+ *
+ * Contains code that produce the ACPI WHEA related information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionWhea.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "Ids.h"
+#include "Filecode.h"
+#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration;  // global user config record
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+CreateHestBank (
+  IN       AMD_HEST_BANK *HestBankPtr,
+  IN       UINT8 BankNum,
+  IN       AMD_WHEA_INIT_DATA *WheaInitDataPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GetAcpiWheaStub (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+AGESA_STATUS
+GetAcpiWheaMain (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create the ACPI table of WHEA and return the pointer to the table.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         AGESA_STATUS
+ */
+AGESA_STATUS
+CreateAcpiWhea (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader);
+  return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * This is the default routine for use when the WHEA option is NOT requested.
+ *
+ * The option install process will create and fill the transfer vector with
+ * the address of the proper routine (Main or Stub). The link optimizer will
+ * strip out of the .DLL the routine that is not used.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         AGESA_STATUS
+ */
+
+AGESA_STATUS
+GetAcpiWheaStub (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  return  AGESA_UNSUPPORTED;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create the ACPI tale of WHEA and return the pointer to the table.
+ *
+ *    @param[in, out]  StdHeader        Standard Head Pointer
+ *    @param[in, out]  WheaMcePtr       Point to Whea Hest Mce table
+ *    @param[in, out]  WheaCmcPtr       Point to Whea Hest Cmc table
+ *
+ *    @retval         UINT32  AGESA_STATUS
+ */
+AGESA_STATUS
+GetAcpiWheaMain (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  )
+{
+  UINT8  BankNum;
+  UINT8  Entries;
+  UINT16 HestMceTableSize;
+  UINT16 HestCmcTableSize;
+  UINT64 MsrData;
+  AMD_HEST_MCE_TABLE *HestMceTablePtr;
+  AMD_HEST_CMC_TABLE *HestCmcTablePtr;
+  AMD_HEST_BANK *HestBankPtr;
+  AMD_WHEA_INIT_DATA *WheaInitDataPtr;
+  AGESA_BUFFER_PARAMS AllocParams;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  FamilySpecificServices = NULL;
+
+  // step 1: calculate Hest table size
+  LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
+  BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count);
+  if (BankNum == 0) {
+    return AGESA_ERROR;
+  }
+
+  HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + BankNum * sizeof (AMD_HEST_BANK);
+  HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + BankNum * sizeof (AMD_HEST_BANK);
+
+  HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr;
+  HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr;
+
+  // step 2: allocate a buffer by callback function
+  if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) {
+    AllocParams.StdHeader = *StdHeader;
+    AllocParams.BufferLength = (UINT32) (HestMceTableSize + HestCmcTableSize);
+    AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE;
+
+    AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader);
+    if (AgesaAllocateBuffer (0, &AllocParams) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader);
+
+    HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPointer;
+    HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (BankNum * sizeof (AMD_HEST_BANK)));
+  }
+
+  // step 3: fill in Hest MCE table
+  GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetWheaInitData (FamilySpecificServices, (CONST VOID **)&WheaInitDataPtr, &Entries, StdHeader);
+
+  ASSERT (BankNum <= WheaInitDataPtr->HestBankNum);
+
+  HestMceTablePtr->TblLength = HestMceTableSize;
+  HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD;
+  HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD;
+  HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD;
+  HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD;
+  HestMceTablePtr->NumHWBanks = BankNum;
+
+  HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1);
+  CreateHestBank (HestBankPtr, BankNum, WheaInitDataPtr);
+
+  // step 4: fill in Hest CMC table
+  HestCmcTablePtr->NumHWBanks = BankNum;
+  HestCmcTablePtr->TblLength = HestCmcTableSize;
+
+  HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1);
+  CreateHestBank (HestBankPtr, BankNum, WheaInitDataPtr);
+
+  // step 5: fill in the incoming structure
+  *WheaMcePtr = HestMceTablePtr;
+  *WheaCmcPtr = HestCmcTablePtr;
+
+  return (AGESA_SUCCESS);
+}
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * It will create Bank structure for Hest table
+ *
+ *    @param[in]  HestBankPtr           Pointer to the Hest Back structure
+ *    @param[in]  BankNum               The number of Bank
+ *    @param[in]  WheaInitDataPtr     Pointer to the AMD_WHEA_INIT_DATA structure
+ *
+ */
+VOID
+STATIC
+CreateHestBank (
+  IN       AMD_HEST_BANK *HestBankPtr,
+  IN       UINT8 BankNum,
+  IN       AMD_WHEA_INIT_DATA *WheaInitDataPtr
+  )
+{
+  UINT8 BankIndex;
+  for (BankIndex = 0; BankIndex < BankNum; BankIndex++) {
+    HestBankPtr->BankNum = BankIndex;
+    HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit;
+    HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat;
+    HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn;
+    HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr;
+    HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD;
+    HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD;
+    HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr;
+    HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr;
+    HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr;
+    HestBankPtr++;
+  }
+}
+
author	efdesign98 <efdesign98@gmail.com>	2011-07-13 16:43:39 -0700
committer	Patrick Georgi <patrick@georgi-clan.de>	2011-07-15 14:17:00 +0200
commit	229f7cb6d660ad4063c9f65e3fabfff80583f281 (patch)
tree	eaa627ceb717250c38f1bc6ca79868b331d12e23 /src/vendorcode/amd/agesa/f10/Proc/CPU/Feature
parent	25f23f17bcb2bac9fb5af0f5d6d1d8c1c9ea16ff (diff)
download	coreboot-229f7cb6d660ad4063c9f65e3fabfff80583f281.tar.xz