Add the AMD Family10 Agesa code

This change officially adds the Agesa code for the AMD Family 10
cpus.  This code supports the G34 and C32 sockets.

Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

79 files changed, 15975 insertions, 0 deletions

diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
new file mode 100755
index 0000000000..d0f1e4a0d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.c
@@ -0,0 +1,159 @@
+/**
+ * @file
+ *
+ * Coherent Family 10h Routines.
+ *
+ * Coherent feature Northbridge implementation specific to Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbCoherentFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return whether the current configuration exceeds the capability.
+ *
+ * @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}.
+ *
+ * Get Node capability and update the minimum supported system capability.
+ *
+ * @param[in]     Node     the Node
+ * @param[in]     State    sysMpCap (updated) and NodesDiscovered
+ * @param[in]     Nb       this northbridge
+ *
+ * @retval        TRUE     system is not capable of current config.
+ * @retval        FALSE    system is capable of current config.
+ */
+BOOLEAN
+Fam10IsExceededCapable (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  UINT8 MaxNodes;
+  PCI_ADDR Reg;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+
+  LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle);
+
+  if (Temp != 0) {
+    MaxNodes = (UINT8) (1 << (~Temp & 0x3));  // That is, 1, 2, 4, or 8
+  } else {
+    MaxNodes = 8;
+  }
+  if (State->SysMpCap > MaxNodes) {
+    State->SysMpCap = MaxNodes;
+  }
+  // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true
+  //
+  return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered));
+}
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ *
+ * @HtNbMethod{::F_STOP_LINK}.
+ *
+ * Use is for fatal incompatible configurations, or for user interface
+ * request to power off a link (IgnoreLink, SkipRegang).
+ * Set ConnDly to make the power effective at the warm reset.
+ * Set XMT and RCV off.
+ *
+ * @param[in] Node   the node to stop a link on.
+ * @param[in] Link   the link to stop.
+ * @param[in] State  access to special routine for writing link control register
+ * @param[in] Nb     this northbridge.
+ */
+VOID
+Fam10StopLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  // Set ConnDly
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_GLOBAL_EXT_CONTROL_0x16C);
+  Temp = 1;
+  LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
+  // Set TransOff and EndOfChain
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+  Temp = 3;
+  State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h
new file mode 100755
index 0000000000..c903ce3bd1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbCoherentFam10.h
@@ -0,0 +1,66 @@
+/**
+ * @file
+ *
+ * Coherent Family 10h specific Routines.
+ *
+ * Coherent feature Northbridge implementation specific to Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return whether the current configuration exceeds the capability.
+ *
+ */
+BOOLEAN
+Fam10IsExceededCapable (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ */
+VOID
+Fam10StopLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c
new file mode 100755
index 0000000000..1e593ec6ab
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbFam10.c
@@ -0,0 +1,295 @@
+/**
+ * @file
+ *
+ * Initializers for Family 10h northbridge support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "CommonReturns.h"
+#include "htNbCoherent.h"
+#include "htNbCoherentFam10.h"
+#include "htNbNonCoherent.h"
+#include "htNbNonCoherentFam10.h"
+#include "htNbOptimization.h"
+#include "htNbOptimizationFam10.h"
+#include "htNbSystemFam10.h"
+#include "htNbUtilities.h"
+#include "htNbUtilitiesFam10.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/**
+ * Map Northbridge links to package links for Family 10h, Rev D, multi-module.
+ *
+ * Unfortunately, there is no way to do this except to type the BKDG text into this data structure.
+ * Note that there is one entry per package external sublink and each connected internal link.
+ */
+CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] =
+{
+  {0, 0, 0},        ///< Module zero, link 0: package link 0
+  {4, 0, 4},        ///< Module zero, link 4: package link 4
+  {0, 1, 1},        ///< Module one,  link 0: package link 1
+  {4, 1, 5},        ///< Module one,  link 4: package link 5
+  {3, 0, 2},        ///< Module zero, link 3: package link 2
+  {7, 0, 6},        ///< Module zero, link 7: package link 6
+  {2, 0, 3},        ///< Module zero, link 2: package link 3
+  {1, 1, 7},        ///< Module one,  link 1: package link 7
+  {1, 0, HT_LIST_MATCH_INTERNAL_LINK_0},        ///< Internal Link
+  {5, 0, HT_LIST_MATCH_INTERNAL_LINK_1},        ///< Internal Link
+  {6, 0, HT_LIST_MATCH_INTERNAL_LINK_2},        ///< Internal Link
+  {2, 1, HT_LIST_MATCH_INTERNAL_LINK_0},        ///< Internal Link
+  {6, 1, HT_LIST_MATCH_INTERNAL_LINK_1},        ///< Internal Link
+  {5, 1, HT_LIST_MATCH_INTERNAL_LINK_2},        ///< Internal Link
+  {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End
+};
+
+/**
+ * A default Ignore Link list for rev D to power off the 3rd internal sublink.
+ */
+STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = {
+  {HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF},
+  {HT_LIST_TERMINAL}
+};
+
+/**
+ * Initial construction data for Family 10h North Bridge, default, full features.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbDefault =
+{
+  8,
+  WriteRoutingTable,
+  WriteNodeID,
+  ReadDefaultLink,
+  EnableRoutingTables,
+  DisableRoutingTables,
+  VerifyLinkIsCoherent,
+  ReadToken,
+  WriteToken,
+  WriteFullRoutingTable,
+  IsIllegalTypeMix,
+  Fam10IsExceededCapable,
+  Fam10StopLink,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  HandleSpecialNodeCase,
+  ReadSouthbridgeLink,
+  VerifyLinkIsNonCoherent,
+  Fam10SetConfigAddrMap,
+  Fam10NorthBridgeFreqMask,
+  GatherLinkFeatures,
+  SetLinkRegang,
+  SetLinkFrequency,
+  SetLinkUnitIdClumping,
+  Fam10WriteTrafficDistribution,
+  Fam10WriteLinkPairDistribution,
+  Fam10BufferOptimizations,
+  Fam10GetNumCoresOnNode,
+  SetTotalNodesAndCores,
+  GetNodeCount,
+  LimitNodes,
+  ReadTrueLinkFailStatus,
+  Fam10GetNextLink,
+  GetPackageLink,
+  MakeLinkBase,
+  Fam10GetModuleInfo,
+  Fam10PostMailbox,
+  Fam10RetrieveMailbox,
+  Fam10GetSocket,
+  0x00000001,
+  0x00000200,
+  18,
+  TRUE,
+  TRUE,
+  ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY)),
+  NULL,
+  0,
+  NULL,
+  MakeKey,
+  NULL
+};
+
+/**
+ * Initial construction data for Family 10h North Bridge, default, full features.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault =
+{
+  8,
+  WriteRoutingTable,
+  WriteNodeID,
+  ReadDefaultLink,
+  EnableRoutingTables,
+  DisableRoutingTables,
+  VerifyLinkIsCoherent,
+  ReadToken,
+  WriteToken,
+  WriteFullRoutingTable,
+  IsIllegalTypeMix,
+  Fam10IsExceededCapable,
+  Fam10StopLink,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  HandleSpecialNodeCase,
+  ReadSouthbridgeLink,
+  VerifyLinkIsNonCoherent,
+  Fam10SetConfigAddrMap,
+  Fam10RevDNorthBridgeFreqMask,
+  GatherLinkFeatures,
+  SetLinkRegang,
+  SetLinkFrequency,
+  SetLinkUnitIdClumping,
+  Fam10WriteTrafficDistribution,
+  Fam10WriteLinkPairDistribution,
+  Fam10RevDBufferOptimizations,
+  Fam10RevDGetNumCoresOnNode,
+  SetTotalNodesAndCores,
+  GetNodeCount,
+  LimitNodes,
+  ReadTrueLinkFailStatus,
+  Fam10GetNextLink,
+  GetPackageLink,
+  MakeLinkBase,
+  Fam10GetModuleInfo,
+  Fam10PostMailbox,
+  Fam10RetrieveMailbox,
+  Fam10RevDGetSocket,
+  0x00000001,
+  0x00000200,
+  18,
+  TRUE,
+  TRUE,
+  AMD_FAMILY_10_HY,
+  (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
+  0,
+  (IGNORE_LINK *)&Fam10RevDIgnoreLinkList,
+  MakeKey,
+  NULL
+};
+
+/**
+ * Initial construction data for Family 10h North Bridge, for non-coherent only builds.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly =
+{
+  8,
+  (PF_WRITE_ROUTING_TABLE)CommonVoid,
+  (PF_WRITE_NODEID)CommonVoid,
+  (PF_READ_DEFAULT_LINK)CommonReturnZero8,
+  (PF_ENABLE_ROUTING_TABLES)CommonVoid,
+  (PF_DISABLE_ROUTING_TABLES)CommonVoid,
+  (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
+  (PF_READ_TOKEN)CommonReturnZero8,
+  (PF_WRITE_TOKEN)CommonVoid,
+  (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
+  (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
+  (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
+  (PF_STOP_LINK)CommonVoid,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
+  ReadSouthbridgeLink,
+  VerifyLinkIsNonCoherent,
+  Fam10SetConfigAddrMap,
+  Fam10NorthBridgeFreqMask,
+  GatherLinkFeatures,
+  SetLinkRegang,
+  SetLinkFrequency,
+  SetLinkUnitIdClumping,
+  (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
+  Fam10BufferOptimizations,
+  Fam10GetNumCoresOnNode,
+  SetTotalNodesAndCores,
+  GetNodeCount,
+  LimitNodes,
+  ReadTrueLinkFailStatus,
+  Fam10GetNextLink,
+  GetPackageLink,
+  MakeLinkBase,
+  Fam10GetModuleInfo,
+  Fam10PostMailbox,
+  Fam10RetrieveMailbox,
+  Fam10GetSocket,
+  0x00000001,
+  0x00000200,
+  18,
+  TRUE,
+  TRUE,
+  ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY)),
+  NULL,
+  0,
+  NULL,
+  MakeKey,
+  NULL
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
new file mode 100755
index 0000000000..dbe48f051f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.c
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * Northbridge non-coherent support for Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbNonCoherentFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
+ *
+ * @param[in]     ConfigMapIndex the map entry to set
+ * @param[in]     SecBus         The secondary bus number to use
+ * @param[in]     SubBus         The subordinate bus number to use
+ * @param[in]     TargetNode     The Node  that shall be the recipient of the traffic
+ * @param[in]     TargetLink     The Link that shall be the recipient of the traffic
+ * @param[in]     State          our global state
+ * @param[in]     Nb             this northbridge
+ */
+VOID
+Fam10SetConfigAddrMap (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT8 CurNode;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
+
+  ASSERT (SecBus <= SubBus);
+  ASSERT (TargetNode <= State->NodesDiscovered);
+  ASSERT (TargetLink < Nb->MaxLinks);
+  Temp = SecBus;
+  Reg.Address.Register += HTHOST_ISOC_REG;
+  LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
+
+  Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
+    ((UINT32)TargetNode << 4) + (UINT32)3;
+  for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
+    Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
+                                   MakePciBusFromNode (CurNode),
+                                   MakePciDeviceFromNode (CurNode),
+                                   CPU_ADDR_FUNC_01,
+                                   REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
+    LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h
new file mode 100755
index 0000000000..29b84d67c4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbNonCoherentFam10.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * Northbridge non-coherent support for Family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ */
+VOID
+Fam10SetConfigAddrMap (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
new file mode 100755
index 0000000000..4a5c515228
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.c
@@ -0,0 +1,214 @@
+/**
+ * @file
+ *
+ * Link optimization support specific to family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htNbOptimizationFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node           Result could (later) be for a specific Node
+ * @param[in]     Interface      Access to non-HT support functions.
+ * @param[in]     Nb             this northbridge
+ *
+ * @return Frequency mask
+ */
+UINT32
+Fam10NorthBridgeFreqMask (
+  IN       UINT8        Node,
+  IN       HT_INTERFACE *Interface,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  UINT32 NbCoreFreq;
+  UINT32 Supported;
+
+  ASSERT (Node < MAX_NODES);
+  ASSERT (Interface != NULL);
+  // The interface to power management will return a system based result.
+  // So we only need to call it once, not on every link.  Save the answer,
+  // and check to see if we can use a saved answer on subsequent calls.
+  //
+  if (Nb->CoreFrequency == 0) {
+    NbCoreFreq = Interface->GetMinNbCoreFreq (Nb->ConfigHandle);
+    NbCoreFreq = (NbCoreFreq / 100);
+    ASSERT (NbCoreFreq != 0);
+    Nb->CoreFrequency = NbCoreFreq;
+  } else {
+    NbCoreFreq = Nb->CoreFrequency;
+  }
+
+  //
+  // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
+  // HT can not go faster than the minimum speed of the northbridge.
+  //
+  if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
+    //  Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1.
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
+  } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
+    // Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1, noting that
+    // next power of two is two greater than non-extended frequencies
+    // (because of the register break).
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
+  } else if (NbCoreFreq > 32) {
+    Supported = HT_FREQUENCY_LIMIT_MAX;
+  } else if (NbCoreFreq == 4) {
+    // unlikely cases, but include as a defensive measure, also avoid trick above
+    Supported = HT_FREQUENCY_LIMIT_400M;
+  } else if (NbCoreFreq == 2) {
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  } else {
+    ASSERT (FALSE);
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  }
+
+  return (Supported);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node           Result could (later) be for a specific Node
+ * @param[in]     Interface      Access to non-HT support functions.
+ * @param[in]     Nb             this northbridge
+ *
+ * @return Frequency mask
+ */
+UINT32
+Fam10RevDNorthBridgeFreqMask (
+  IN       UINT8        Node,
+  IN       HT_INTERFACE *Interface,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  UINT32 NbCoreFreq;
+  UINT32 Supported;
+
+  ASSERT (Node < MAX_NODES);
+  ASSERT (Interface != NULL);
+  // The interface to power management will return a system based result.
+  // So we only need to call it once, not on every link.  Save the answer,
+  // and check to see if we can use a saved answer on subsequent calls.
+  //
+  if (Nb->CoreFrequency == 0) {
+    NbCoreFreq = Interface->GetMinNbCoreFreq (Nb->ConfigHandle);
+    NbCoreFreq = (NbCoreFreq / 100);
+    ASSERT (NbCoreFreq != 0);
+    Nb->CoreFrequency = NbCoreFreq;
+  } else {
+    NbCoreFreq = Nb->CoreFrequency;
+  }
+
+  // For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3.
+  // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3,
+  //  to avoid complicated recovery if the final speed is HT1.)
+  if (NbCoreFreq > 10) {
+    NbCoreFreq = NbCoreFreq * 2;
+  }
+  //
+  // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
+  // HT can not go faster than the minimum speed of the northbridge.
+  //
+  if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
+    //  Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1.
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
+  } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
+    // Convert frequency to bit and all less significant bits,
+    // by setting next power of 2 and subtracting 1, noting that
+    // next power of two is two greater than non-extended frequencies
+    // (because of the register break).
+    //
+    Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
+  } else if (NbCoreFreq > 32) {
+    Supported = HT_FREQUENCY_LIMIT_MAX;
+  } else if (NbCoreFreq == 4) {
+    // unlikely cases, but include as a defensive measure, also avoid trick above
+    Supported = HT_FREQUENCY_LIMIT_400M;
+  } else if (NbCoreFreq == 2) {
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  } else {
+    ASSERT (FALSE);
+    Supported = HT_FREQUENCY_LIMIT_200M;
+  }
+
+  return (Supported);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.h
new file mode 100755
index 0000000000..e98b9d311e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbOptimizationFam10.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Link optimization support specific to family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ */
+UINT32
+Fam10NorthBridgeFreqMask (
+  IN       UINT8            Node,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  );
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ */
+UINT32
+Fam10RevDNorthBridgeFreqMask (
+  IN       UINT8            Node,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
new file mode 100755
index 0000000000..d275f060ee
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.c
@@ -0,0 +1,398 @@
+/**
+ * @file
+ *
+ * System Tuning Family 10h specific routines
+ *
+ * Support for Traffic Distribution and buffer tunings which
+ * can not be done in a register table.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbSystemFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Register Fields for an individual link pair.
+ */
+typedef struct {
+  UINT32 Enable:1;            ///< Enable distribution on this pair.
+  UINT32 Asymmetric:1;        ///< Links are different widths.
+  UINT32 MasterSelect:3;      ///< The master link.
+  UINT32 AlternateSelect:3;   ///< The alternate link.
+} PAIR_SELECT_FIELDS;
+
+/**
+ * Register access union for ::PAIR_SELECT_FIELDS.
+ */
+typedef union {
+  UINT32 Value;               ///< access as a 32 bit value or register.
+  PAIR_SELECT_FIELDS Fields;  ///< access individual fields.
+} PAIR_SELECT;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION}
+ *
+ * @param[in]     Links01   coherent Links from Node 0 to 1
+ * @param[in]     Links10   coherent Links from Node 1 to 0
+ * @param[in]     Nb        this northbridge
+ */
+VOID
+Fam10WriteTrafficDistribution (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR TrafficDistReg;
+
+  TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
+                                            MakePciBusFromNode (0),
+                                            MakePciDeviceFromNode (0),
+                                            CPU_HTNB_FUNC_00,
+                                            REG_HT_TRAFFIC_DIST_0X164);
+
+  // Node 0
+  // DstLnk
+  LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle);
+  // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
+  Temp = 0x0107;
+  LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
+
+  TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1),
+                                            MakePciBusFromNode (1),
+                                            MakePciDeviceFromNode (1),
+                                            CPU_HTNB_FUNC_00,
+                                            REG_HT_TRAFFIC_DIST_0X164);
+
+  // Node 1
+  // DstLnk
+  LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle);
+  // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
+  Temp = 0x0007;
+  LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION}
+ *
+ * Set the links as a pair using the link pair index provided.  Set asymmetric attribute as
+ * provided. If the Master Link is not currently used as the route, fixup the routes for all
+ * nodes which specify the alternate link.
+ *
+ * @param[in]    Node           Set the pair on this node
+ * @param[in]    ConnectedNode  The Node to which this link pair directly connects.
+ * @param[in]    Pair           Using this pair set in the register
+ * @param[in]    Asymmetric     True if different widths
+ * @param[in]    MasterLink     Set this as the master link and in the route
+ * @param[in]    AlternateLink  Set this as the alternate link
+ * @param[in]    Nb             this northbridge
+ *
+ */
+VOID
+Fam10WriteLinkPairDistribution (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 CurrentRoute;
+  UINT32 MasterRoute;
+  UINT32 AlternateRoute;
+  PAIR_SELECT Selection;
+  UINT32 RouteIndex;
+
+  ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES));
+  ASSERT (Pair < MAX_LINK_PAIRS);
+  ASSERT (MasterLink < Nb->MaxLinks);
+  ASSERT (AlternateLink < Nb->MaxLinks);
+
+  // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of
+  // Alternate link with Master link.  If routing used the master link, no update is necessary.
+  MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1));
+  AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_ROUTE0_0X40);
+  for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) {
+    Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4);
+    LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
+    if ((CurrentRoute & AlternateRoute) != 0) {
+      // Since Master and Alternate are redundant, the route must use one or the other but not both.
+      ASSERT ((CurrentRoute & MasterRoute) == 0);
+      // Set the master route for Request, Response or Broadcast only if the alternate was used for that case.
+      // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response.
+      CurrentRoute = ((CurrentRoute & ~AlternateRoute) |
+                      ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute));
+      LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
+    }
+  }
+
+  // Set the Link Pair and Enable it
+  Selection.Fields.Enable = 1;
+  Selection.Fields.Asymmetric = Asymmetric;
+  Selection.Fields.MasterSelect = MasterLink;
+  Selection.Fields.AlternateSelect = AlternateLink;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_PAIR_DIST_0X1E0);
+  LibAmdPciWriteBits (
+    Reg,
+    ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1),
+    (PAIR_SELECT_OFFSET * Pair),
+    &Selection.Value,
+    Nb->ConfigHandle
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Family 10h specific tunings.
+ *
+ * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State  global state
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+Fam10BufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR currentPtr;
+  PCI_ADDR GangedReg;
+  UINT8 i;
+
+  ASSERT (Node < MAX_NODES);
+
+  //
+  // Link to XCS Token Count Tuning
+  //
+  // For each active Link that we reganged (so this unfortunately can't go into the PCI reg
+  // table), we have to switch the Link to XCS Token Counts to the ganged state.
+  // We do this here for the non - uma case, which is to write the values that would have
+  // been power on defaults if the Link was ganged at cold reset.
+  //
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+    if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
+      // If the Link is greater than 4, this is a subLink 1, so it is not reganged.
+      if ((*State->PortList)[i].Link < 4) {
+        currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                              MakePciBusFromNode (Node),
+                                              MakePciDeviceFromNode (Node),
+                                              CPU_NB_FUNC_03,
+                                              REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link)
+          );
+        if ((*State->PortList)[i].SelRegang) {
+          // Handle all the regang Token count adjustments
+
+          // SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2
+          Temp = 0xAA;
+          LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle);
+          // SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0
+          Temp = 0;
+          LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle);
+          // [FreeTok] = 3
+          Temp = 3;
+          LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
+
+        } else {
+          // Read the regang bit in hardware
+          GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID),
+                                               MakePciBusFromNode ((*State->PortList)[i].NodeID),
+                                               MakePciDeviceFromNode ((*State->PortList)[i].NodeID),
+                                               CPU_HTNB_FUNC_00,
+                                               REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
+          LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle);
+          if (Temp == 1) {
+            // handle a minor adjustment for strapped ganged Links.  If SelRegang is false we
+            // didn't do the regang, so if the bit is on then it's hardware strapped.
+            //
+
+            // [FreeTok] = 3
+            Temp = 3;
+            LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Family 10h specific tunings.
+ *
+ * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State  global state
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+Fam10RevDBufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+  UINT8 i;
+  FINAL_LINK_STATE FinalLinkState;
+  UINT32 Widthin;
+  UINT32 Widthout;
+
+  ASSERT (Node < MAX_NODES);
+
+  //
+  // Internal link fixup.
+  // When powering off internal link 2, a performance optimization may be possible where its buffers
+  // can be made available to the external paired sublink.  If the conditions are met, do the fix up here.
+  //
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+    if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
+      // Is this a sublink 0 paired with internal link 2?
+      if (((*State->PortList)[i].Link < 4) &&
+          (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) {
+        FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State);
+        // Are we ignoring the internal link 2 with Power Off?
+        if (FinalLinkState == POWERED_OFF) {
+          // Read the regang bit in hardware.
+          Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                         MakePciBusFromNode (Node),
+                                         MakePciDeviceFromNode (Node),
+                                         CPU_HTNB_FUNC_00,
+                                         REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
+          LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+          // If it's already ganged, skip to the width fix up.
+          if (Temp == 0) {
+            // Clear EndOfChain / XmitOff on internal sublink
+            Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb);
+            Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+            Temp = 0;
+            State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
+
+            // Gang the link
+            Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb);
+          }
+
+          // Set InLnSt = PHY_OFF in register table.
+          // Set sublink 0 widths to 8 bits
+          if ((*State->PortList)[i].SelWidthOut > 8) {
+            (*State->PortList)[i].SelWidthOut = 8;
+          }
+          if ((*State->PortList)[i].SelWidthIn > 8) {
+            (*State->PortList)[i].SelWidthIn = 8;
+          }
+          Widthout = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
+          Widthin = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
+          Temp = (Widthin & 7) | ((Widthout & 7) << 4);
+          Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb);
+          Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+          State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
+        }
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h
new file mode 100755
index 0000000000..4994df0593
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbSystemFam10.h
@@ -0,0 +1,90 @@
+/**
+ * @file
+ *
+ * System Tuning Family 10h specific routines
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ */
+VOID
+Fam10WriteTrafficDistribution (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  );
+
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ */
+VOID
+Fam10WriteLinkPairDistribution (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  );
+
+/**
+ * Family 10h specific tunings.
+ *
+ */
+VOID
+Fam10BufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Family 10h Rev D specific tunings.
+ *
+ */
+VOID
+Fam10RevDBufferOptimizations (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
new file mode 100755
index 0000000000..8f7cacf4fd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.c
@@ -0,0 +1,441 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * These routines are needed for support of more than one feature area.
+ * Collect them in this file so build options don't remove them.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbUtilitiesFam10.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+UINT8
+Fam10GetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Result;
+  UINT32 Leveling;
+  UINT32 Cores;
+  UINT8 i;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Read CmpCap
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+
+  LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
+
+  // Support Downcoring
+  Result = Cores;
+  Cores++;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_DOWNCORE_3X190);
+  LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle);
+  for (i = 0; i < Cores; i++) {
+    if ((Leveling & ((UINT32) 1 << i)) != 0) {
+      Result--;
+    }
+  }
+  return (UINT8) (Result + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}.
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+UINT8
+Fam10RevDGetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Result;
+  UINT32 Leveling;
+  UINT32 Cores;
+  UINT32 Cores2;
+  UINT8 i;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Read CmpCap
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+
+  LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle);
+  Cores = Cores + (Cores2 << 2);
+
+  // Support Downcoring
+  Result = Cores;
+  Cores++;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_DOWNCORE_3X190);
+  LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle);
+  for (i = 0; i < Cores; i++) {
+    if ((Leveling & ((UINT32) 1 << i)) != 0) {
+      Result--;
+    }
+  }
+  return (UINT8) (Result + 1);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ * @HtNbMethod{::F_GET_NEXT_LINK}
+ *
+ * Family 10h specific implementation use the Internal Link field in
+ * the northbridge to prioritize internal links in the order.
+ *
+ * @param[in]     Node The node on which to iterate links.
+ * @param[in,out] Link IN: the current iteration context, OUT: the next link.
+ * @param[in]     Nb   This Northbridge, access to config pointer.
+ *
+ * @retval LinkIteratorExternal    The current Link is an external link.
+ * @retval LinkIteratorInternal    The current Link is an internal link.
+ * @retval LinkIteratorEnd         There is no next link (Link is back to BEGIN).
+ *
+ */
+LINK_ITERATOR_STATUS
+Fam10GetNextLink (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32   InternalLinks;
+  UINT32   ExternalLinks;
+  UINT32   HigherLinks;
+  BOOLEAN  IsInternalLink;
+  LINK_ITERATOR_STATUS Status;
+
+  ASSERT ((Node < MAX_NODES));
+  ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN));
+  InternalLinks = 0;
+  ExternalLinks = 0;
+
+  // Read IntLnkRoute from the Link Initialization Status register.
+  // (Note that this register field is not reserved prior to rev D, but should be zero.)
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_INITIALIZATION_0X1A0);
+
+  LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle);
+  // The external links are all possible links which are not Internal
+  ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks);
+  // Can't have no possible links!
+  ASSERT ((ExternalLinks != 0) || (InternalLinks != 0));
+
+
+  if (*Link == LINK_ITERATOR_BEGIN) {
+    // If the request is for the first link (BEGIN), get it
+    if (InternalLinks != 0) {
+      *Link = LibAmdBitScanForward (InternalLinks);
+      Status = LinkIteratorInternal;
+    } else {
+      *Link = LibAmdBitScanForward (ExternalLinks);
+      Status = LinkIteratorExternal;
+    }
+  } else {
+    // If the iterator is not at the beginning, search for the next Link starting from the
+    // current link.
+    HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1);
+    IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0);
+    if (IsInternalLink && (HigherLinks != 0)) {
+      // We are still on internal links and there are more to do.
+      *Link = LibAmdBitScanForward (HigherLinks);
+      Status = LinkIteratorInternal;
+    } else {
+      if (IsInternalLink) {
+        // We are transitioning now from internal to external, so get the first external link
+        HigherLinks = ExternalLinks;
+      } else {
+        // We are already iterating over external links, so get the next one
+        HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1);
+      }
+      if (HigherLinks != 0) {
+        *Link = LibAmdBitScanForward (HigherLinks);
+        Status = LinkIteratorExternal;
+      } else {
+        // The end of all links
+        *Link = LINK_ITERATOR_BEGIN;
+        Status = LinkIteratorEnd;
+      }
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ * @HtNbMethod{::F_GET_MODULE_INFO}
+ *
+ * Provide the Processor module type, single or multi, and the node's module id.
+ *
+ * @param[in]     Node                the Node
+ * @param[out]    ModuleType          0 for Single, 1 for Multi
+ * @param[out]    Module              The module number of this node (0 if Single)
+ * @param[in]     Nb                  this northbridge
+ *
+ */
+VOID
+Fam10GetModuleInfo (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 MultNodeCpu;
+  UINT32 IntNodeNum;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CAPABILITY_3XE8);
+  LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle);
+
+  *ModuleType = (UINT8) MultNodeCpu;
+  *Module = (UINT8) IntNodeNum;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbMethod{::F_GET_SOCKET}
+ *
+ * The hardware socket naming method is not available for Family 10h prior to rev D.
+ *
+ * @param[in]   Node    The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb      Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+UINT8
+Fam10GetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  ASSERT ((Node < MAX_NODES));
+  ASSERT (TempNode < MAX_NODES);
+  ASSERT (Nb != NULL);
+  return (Node);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbMethod{::F_GET_SOCKET}
+ *
+ * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr.
+ *
+ * @param[in]   Node    The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb      Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+UINT8
+Fam10RevDGetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Socket;
+  PCI_ADDR Reg;
+
+  ASSERT ((TempNode < MAX_NODES));
+  ASSERT ((Node < MAX_NODES));
+  // Read SbiAddr
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode),
+                                 MakePciBusFromNode (TempNode),
+                                 MakePciDeviceFromNode (TempNode),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_SBI_CONTROL_3X1E4);
+  LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle);
+  return ((UINT8) Socket);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ * @HtNbMethod{::F_POST_MAILBOX}
+ *
+ * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
+ * and module info.
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailboxes   The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+VOID
+Fam10PostMailbox (
+  IN       UINT8 Node,
+  IN       AP_MAILBOXES ApMailboxes,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_MCA_LINK_THRESHOLD_3X168);
+  LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle);
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_MCA_L3_THRESHOLD_3X170);
+  LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Retrieve info from a node's mailbox.
+ *
+ * @HtNbMethod{::F_RETRIEVE_MAILBOX}
+ *
+ * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
+ * and module info.
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     Nb            this northbridge
+ *
+ * @return        The ap mailbox info
+ *
+ */
+AP_MAIL_INFO
+Fam10RetrieveMailbox (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  AP_MAIL_INFO ApMailInfo;
+
+  ASSERT (Node < MAX_NODES);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_MCA_LINK_THRESHOLD_3X168);
+  LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle);
+  return ApMailInfo;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h
new file mode 100755
index 0000000000..f78fccd52e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Fam10/htNbUtilitiesFam10.h
@@ -0,0 +1,128 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ */
+UINT8
+Fam10GetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ */
+UINT8
+Fam10RevDGetNumCoresOnNode (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ */
+LINK_ITERATOR_STATUS
+Fam10GetNextLink (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ */
+VOID
+Fam10GetModuleInfo (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ */
+UINT8
+Fam10GetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ */
+UINT8
+Fam10RevDGetSocket (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ */
+VOID
+Fam10PostMailbox (
+  IN       UINT8 Node,
+  IN       AP_MAILBOXES ApMailboxes,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Retrieve info from a node's mailbox.
+ *
+ */
+AP_MAIL_INFO
+Fam10RetrieveMailbox (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
new file mode 100755
index 0000000000..56ed891e8c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.c
@@ -0,0 +1,779 @@
+/**
+ * @file
+ *
+ * Coherent Discovery Routines.
+ *
+ * Contains routines for discovery, along with Temporary routing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htFeatDynamicDiscovery.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define LOGICAL_PROCESSOR_NONE 0xFF
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Status result from exploring for a new node on a link.
+ */
+typedef enum {
+  ExploreNodeStatusNew,    ///< A new node was discovered
+  ExploreNodeStatusGood,   ///< A new link to an already known node was discovered
+  ExploreNodeStatusStop,   ///< Discovery must halt now.
+  ExploreNodeStatusIgnore, ///< A new node was ignored on purpose.
+  ExploreNodeStatusMax     ///< Use for bounds check and limit only
+} EXPLORE_NODE_STATUS;
+
+/**
+ * Save all the information needed about a node at its discovery.
+ *
+ * When we can access the node at a known temporary route, read everything needed
+ * to do node to socket mapping, post to ap mailbox at later times.
+ */
+typedef struct {
+  UINT8       LogicalProcessor;     ///< Independent of Node,Socket group nodes into logical
+                                    ///< processors based on discovery.
+  UINT8       CurrentNode;          ///< The node from which discovery occurred.
+  UINT8       CurrentLink;          ///< The link on that node which we explored.
+  UINT8       PackageLink;          ///< The package level link corresponding to CurrentLink.
+  UINT8       CurrentModuleType;    ///< The current node's module type, Single or Multiple.
+  UINT8       CurrentModule;        ///< This current node's module id.
+  UINT8       HardwareSocket;       ///< Save the hardware socket strap (for hardware socket method).
+  UINT8       NewModuleType;        ///< The new node's module type, Single or Multiple.
+  UINT8       NewModule;            ///< The new node's module id.
+} NEW_NODE_SAVED_INFO_ITEM;
+
+/**
+ * A "no info" initializer for saved new node info.
+ */
+STATIC CONST NEW_NODE_SAVED_INFO_ITEM ROMDATA NoInfoSavedYet =
+{
+  LOGICAL_PROCESSOR_NONE, 0, 0, 0, 0, 0, 0, 0
+};
+
+/**
+ * A list of all the new node info, indexed by each new node's nodeid.
+ */
+typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***              GENERIC HYPERTRANSPORT DISCOVERY CODE                  ***
+ ***************************************************************************/
+
+/*-----------------------------------------------------------------------------------*/
+/**
+ * Ensure a request / response route from target Node to bsp.
+ *
+ * Since target Node is always a predecessor of actual target Node, each Node gets a
+ * route to actual target on the Link that goes to target.  The routing produced by
+ * this routine is adequate for config access during discovery, but NOT for coherency.
+ *
+ * @param[in] TargetNode     the path to actual target goes through target
+ * @param[in] ActualTarget   the ultimate target being routed to
+ * @param[in] State           our global state, port config info
+ *
+ */
+VOID
+STATIC
+routeFromBSP (
+  IN       UINT8        TargetNode,
+  IN       UINT8        ActualTarget,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT8 PredecessorNode;
+  UINT8 PredecessorLink;
+  UINT8 CurrentPair;
+
+  if (TargetNode == 0) {
+    return;  //  BSP has no predecessor, stop
+  }
+
+  // Search for the Link that connects TargetNode to its predecessor
+  CurrentPair = 0;
+  while ((*State->PortList)[CurrentPair*2 + 1].NodeID != TargetNode) {
+    CurrentPair++;
+    ASSERT (CurrentPair < State->TotalLinks);
+  }
+
+  PredecessorNode = (*State->PortList)[ (CurrentPair * 2)].NodeID;
+  PredecessorLink = (*State->PortList)[ (CurrentPair * 2)].Link;
+
+  // Recursively call self to ensure the route from the BSP to the Predecessor
+  // Node is established
+  routeFromBSP (PredecessorNode, ActualTarget, State);
+
+  State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Test Compatibility of a new node, and handle failure.
+ *
+ * Make the compatibility test call for the northbridge.
+ * If the new node is incompatible, force 1P.  Notify the event.
+ * Additionally, invoke the northbridge stop link method, to
+ * implement isolation of the BSP from any incompatible node.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ * @retval TRUE            Check is Ok
+ * @retval FALSE           Check failed and is handled
+ */
+BOOLEAN
+STATIC
+CheckCompatible (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 NodeToKill;
+  BOOLEAN Result;
+
+  Result = TRUE;
+
+  // Check the northbridge of the Node we just found, to make sure it is compatible
+  // before doing anything else to it.
+  //
+  if (State->Nb->IsIllegalTypeMix ((CurrentNode + 1), State->Nb)) {
+    IDS_ERROR_TRAP;
+
+    // Notify BIOS of event
+    NotifyFatalCohProcessorTypeMix (
+      CurrentNode,
+      CurrentLink,
+      State->NodesDiscovered,
+      State
+      );
+
+    // If Node is not compatible, force boot to 1P
+    // If they are not compatible stop cHT init and:
+    //     1. Disable all cHT Links on the BSP
+    //     2. Configure the BSP routing tables as a UP.
+    //     3. Notify main BIOS.
+    //
+    State->NodesDiscovered = 0;
+    State->TotalLinks = 0;
+    // Abandon our coherent Link data structure.  At this point there may
+    // be coherent Links on the BSP that are not yet in the portList, and
+    // we have to turn them off anyway.  So depend on the hardware to tell us.
+    //
+    for (CurrentLink = 0; CurrentLink < State->Nb->MaxLinks; CurrentLink++) {
+      // Stop all Links which are connected, coherent, and ready
+      if (State->Nb->VerifyLinkIsCoherent (0, CurrentLink, State->Nb)) {
+        State->Nb->StopLink (0, CurrentLink, State, State->Nb);
+      }
+    }
+
+    for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
+      State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
+    }
+
+    State->HtInterface->CleanMapsAfterError (State);
+
+    // End Coherent Discovery
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check the system MP capability with a new node and handle any failure.
+ *
+ * Invoke the northbridge MP capability check.  If it fails, notify the event and force
+ * 1P.  Should not need to stop links on the BSP.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ * @retval TRUE            Check is Ok
+ * @retval FALSE           Check Failed and is handled
+ */
+BOOLEAN
+STATIC
+CheckCapable (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 NodeToKill;
+  BOOLEAN Result;
+
+  Result = TRUE;
+
+  // Check the capability of northbridges against the currently known configuration
+  if (State->Nb->IsExceededCapable ((CurrentNode + 1), State, State->Nb)) {
+    IDS_ERROR_TRAP;
+    // Notify BIOS of event
+    NotifyFatalCohMpCapMismatch (
+      CurrentNode,
+      CurrentLink,
+      State->SysMpCap,
+      State->NodesDiscovered,
+      State
+      );
+
+    State->NodesDiscovered = 0;
+    State->TotalLinks = 0;
+
+    for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
+      State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
+    }
+
+    State->HtInterface->CleanMapsAfterError (State);
+
+    // End Coherent Discovery
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make all the tests needed to determine if a link should be added to the system data structure.
+ *
+ * The link should be added to the system data structure if it is:
+ * - not being Ignored on this boot
+ * - not having a hard failure
+ * - coherent and connected
+ * - not already in the system data structure
+ * - not subject to some special handling case.
+ * .
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ * @retval FALSE          This link should not be added.
+ * @retval TRUE           This link should explored and added to the system.
+ */
+BOOLEAN
+STATIC
+IsLinkToAdd (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       STATE_DATA  *State
+  )
+{
+  BOOLEAN Linkfound;
+  UINTN Port;
+  FINAL_LINK_STATE FinalLinkState;
+  BOOLEAN Result;
+
+  Result = FALSE;
+
+  FinalLinkState = State->HtInterface->GetIgnoreLink (CurrentNode, CurrentLink, State->Nb->DefaultIgnoreLinkList, State);
+  if ((FinalLinkState != MATCHED) && (FinalLinkState != POWERED_OFF)) {
+    if (!State->Nb->ReadTrueLinkFailStatus (CurrentNode, CurrentLink, State, State->Nb)) {
+      // Make sure that the Link is connected, coherent, and ready
+      if (State->Nb->VerifyLinkIsCoherent (CurrentNode, CurrentLink, State->Nb)) {
+        // Test to see if the CurrentLink has already been explored
+        Linkfound = FALSE;
+        for (Port = 0; Port < State->TotalLinks; Port++) {
+          if ((((*State->PortList)[ (Port * 2 + 1)].NodeID == CurrentNode) &&
+               ((*State->PortList)[ (Port * 2 + 1)].Link == CurrentLink)) ||
+              (((*State->PortList)[ (Port * 2)].NodeID == CurrentNode) &&
+               ((*State->PortList)[ (Port * 2)].Link == CurrentLink))) {
+            Linkfound = TRUE;
+            break;
+          }
+        }
+        if (!Linkfound) {
+          if (!State->Nb->HandleSpecialLinkCase (CurrentNode, CurrentLink, State, State->Nb)) {
+            Result = TRUE;
+          }
+        }
+      }
+    }
+  } else {
+    if (FinalLinkState == POWERED_OFF) {
+      State->Nb->StopLink (CurrentNode, CurrentLink, State, State->Nb);
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Explore for a new node over a link, handling whatever is found.
+ *
+ * Open a temporary route over a link on the current node.
+ * Make checks for compatibility and capability in the proper sequence.
+ * If the node found is new, set a token to it, so it will be recognized in the
+ * future, and notify an event for finding a new node.
+ * If the node is already found (token is set), just return status.
+ *
+ * @param[in]     CurrentNode         The node we are exploring from
+ * @param[in]     CurrentLink         The Link on that node to explore.
+ * @param[in]     LogicalProcessor    The processor to update in the maps.
+ * @param[in,out] NewNodeSavedInfo    The saved info for nodes in that processor.
+ * @param[in]     State               Access to Northbridge interface.
+ *
+ * @retval ExploreNodeStatusNew    A new node was found
+ * @retval ExploreNodeStatusGood   This is a good link to an already known node
+ * @retval ExploreNodeStatusStop   Stop Coherent Discovery
+ */
+EXPLORE_NODE_STATUS
+STATIC
+ExploreNode (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       UINT8       LogicalProcessor,
+  IN OUT   NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 Token;
+  EXPLORE_NODE_STATUS Status;
+
+  // Modify CurrentNode's routing table to use CurrentLink to send
+  // traffic to CurrentNode + 1
+  //
+  State->Nb->WriteRoutingTable (CurrentNode, (CurrentNode + 1), CurrentLink, State->Nb);
+  if (!State->Nb->HandleSpecialNodeCase ((CurrentNode + 1), CurrentLink, State, State->Nb)) {
+    if (CheckCompatible (CurrentNode, CurrentLink, State)) {
+      // Read Token from Current + 1
+      Token = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
+      ASSERT (Token <= State->NodesDiscovered);
+      if (Token == 0) {
+        State->NodesDiscovered++;
+        ASSERT (State->NodesDiscovered < MAX_NODES);
+        if (CheckCapable (CurrentNode, CurrentLink, State)) {
+          Token = State->NodesDiscovered;
+          State->Nb->WriteToken ((CurrentNode + 1), Token, State->Nb);
+          // Fill in Saved New Node info for the discovered node.
+          // We do this so we don't have to keep a temporary route open to it.
+          // So we save everything that might be needed to set the socket and node
+          // maps for either the software or hardware method.
+          //
+          (*NewNodeSavedInfo)[Token].LogicalProcessor = LogicalProcessor;
+          (*NewNodeSavedInfo)[Token].CurrentNode = CurrentNode;
+          (*NewNodeSavedInfo)[Token].CurrentLink = CurrentLink;
+          (*NewNodeSavedInfo)[Token].PackageLink = State->Nb->GetPackageLink (CurrentNode, CurrentLink, State->Nb);
+          (*NewNodeSavedInfo)[Token].HardwareSocket = State->Nb->GetSocket (Token, (CurrentNode + 1), State->Nb);
+          State->Nb->GetModuleInfo (
+            CurrentNode,
+            &((*NewNodeSavedInfo)[Token].CurrentModuleType),
+            &((*NewNodeSavedInfo)[Token].CurrentModule),
+            State->Nb
+            );
+          State->Nb->GetModuleInfo (
+            (CurrentNode + 1),
+            &((*NewNodeSavedInfo)[Token].NewModuleType),
+            &((*NewNodeSavedInfo)[Token].NewModule),
+            State->Nb
+            );
+
+          // Notify BIOS with info
+          NotifyInfoCohNodeDiscovered (
+            CurrentNode,
+            CurrentLink,
+            Token,
+            (CurrentNode + 1),
+            State
+            );
+          Status = ExploreNodeStatusNew;
+        } else {
+          // Failed Capable
+          Status = ExploreNodeStatusStop;
+        }
+      } else {
+        // Not a new node, token already set
+        Status = ExploreNodeStatusGood;
+      }
+    } else {
+      // Failed Compatible
+      Status = ExploreNodeStatusStop;
+    }
+  } else {
+    // Ignore this node
+    Status = ExploreNodeStatusIgnore;
+  }
+
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process all the saved new node info for the current processor.
+ *
+ * When all nodes in the processor have been discovered, we can process all the saved
+ * info about the nodes.  We add each node to the socket and node maps.
+ *
+ * @param[in]    LogicalProcessor    The processor to update in the maps.
+ * @param[in]    NewNodeSavedInfo    The saved info for nodes in that processor.
+ * @param[in]    State               Our system representation.
+ */
+VOID
+STATIC
+ProcessSavedNodeInfo (
+  IN       UINT8                    LogicalProcessor,
+  IN       NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 NewNode;
+  UINT8 HardwareSocket;
+
+  // Can't have more processors than nodes, just more (or equal) nodes than processors.
+  ASSERT (LogicalProcessor <= (State->NodesDiscovered));
+  HardwareSocket = 0xFF;
+  // Find the Hardware Socket value to use (if we are using the hardware socket naming method).
+  // The new nodes are the ones in this processor, so find the one that is module 0.
+  for (NewNode = 0; NewNode < (State->NodesDiscovered + 1); NewNode++) {
+    if (((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) &&
+        ((*NewNodeSavedInfo)[NewNode].NewModule == 0)) {
+      HardwareSocket = (*NewNodeSavedInfo)[NewNode].HardwareSocket;
+      break;
+    }
+  }
+  // We must have found a result, however, the hardware socket value doesn't have to be correct
+  // unless we are using the hardware socket naming method.  Northbridge code should return the
+  // node number for the hardware socket if hardware socket strapping is not supported (i.e. no sbi).
+  ASSERT (HardwareSocket != 0xFF);
+
+  // Set the node to socket maps for this processor.  Node zero is always handled specially,
+  // so skip it in this loop.
+  for (NewNode = 1; NewNode < (State->NodesDiscovered + 1); NewNode++) {
+    if ((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) {
+      // For the currently discovered logical processor, update node to socket
+      // map for all the processor's nodes.
+      State->HtInterface->SetNodeToSocketMap (
+        (*NewNodeSavedInfo)[NewNode].CurrentNode,
+        (*NewNodeSavedInfo)[NewNode].CurrentModule,
+        (*NewNodeSavedInfo)[NewNode].PackageLink,
+        NewNode,
+        HardwareSocket,
+        (*NewNodeSavedInfo)[NewNode].NewModule,
+        State);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Create and add a new link to the system data structure.
+ *
+ * Add the two port list data structures, source first, initializing
+ * the two node ids and the link values.  The node id of the remote
+ * node is its token value.  Also, update the adjacency matrix and
+ * node degree table.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  CurrentLink The Link on that node to explore.
+ * @param[in]  TempRoute   The temporary node route that goes over that link.
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ */
+VOID
+STATIC
+AddLinkToSystem (
+  IN       UINT8       CurrentNode,
+  IN       UINT8       CurrentLink,
+  IN       UINT8       TempRoute,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT8 Token;
+
+  ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
+
+  Token = State->Nb->ReadToken (TempRoute, State->Nb);
+
+  (*State->PortList)[State->TotalLinks * 2].Type = PORTLIST_TYPE_CPU;
+  (*State->PortList)[State->TotalLinks * 2].Link = CurrentLink;
+  (*State->PortList)[State->TotalLinks * 2].NodeID = CurrentNode;
+
+  (*State->PortList)[State->TotalLinks * 2 + 1].Type = PORTLIST_TYPE_CPU;
+  (*State->PortList)[State->TotalLinks * 2 + 1].Link = State->Nb->ReadDefaultLink (TempRoute, State->Nb);
+  (*State->PortList)[State->TotalLinks * 2 + 1].NodeID = Token;
+
+  State->TotalLinks++;
+
+  if ( !State->Fabric->SysMatrix[CurrentNode][Token] ) {
+    State->Fabric->SysDegree[CurrentNode]++;
+    State->Fabric->SysDegree[Token]++;
+    State->Fabric->SysMatrix[CurrentNode][Token] = TRUE;
+    State->Fabric->SysMatrix[Token][CurrentNode] = TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Start discovery from a new node.
+ *
+ * If the node is not the BSP, establish a route between the node and the
+ * BSP for request/response.
+ * Set the node id, and enable routing on this node.  This gives us control
+ * on that node to isolate links, by specifying each link in turn as the route
+ * to a possible new node.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ */
+VOID
+STATIC
+StartFromANewNode (
+  IN       UINT8       CurrentNode,
+  IN       STATE_DATA  *State
+  )
+{
+  if (CurrentNode != 0) {
+    // Set path from BSP to CurrentNode
+    routeFromBSP (CurrentNode, CurrentNode, State);
+
+    // Set path from BSP to CurrentNode for CurrentNode + 1 if
+    // CurrentNode + 1 != MAX_NODES
+    //
+    if ((CurrentNode + 1) != MAX_NODES) {
+      routeFromBSP (CurrentNode, (CurrentNode + 1), State);
+    }
+
+    // Configure CurrentNode to route traffic to the BSP through its
+    // default Link
+    //
+    State->Nb->WriteRoutingTable (CurrentNode, 0, State->Nb->ReadDefaultLink (CurrentNode, State->Nb), State->Nb);
+  }
+
+  // Set CurrentNode's NodeID field to CurrentNode
+  State->Nb->WriteNodeID (CurrentNode, CurrentNode, State->Nb);
+
+  // Enable routing tables on CurrentNode
+  State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Back up from exploring a one-deep internal node.
+ *
+ * When a newly discovered node has internal package links to another
+ * node in the same processor, discovery moves to that node to do the
+ * internal links.  Afterwards, this routine provides recovery from that.
+ * The node needs to respond again using deflnk rather than routing, so
+ * that connections from other nodes to that one can be identified.
+ *
+ * @param[in]  CurrentNode The node we are exploring from
+ * @param[in]  State       Access to Northbridge interface.
+ *
+ */
+VOID
+STATIC
+BackUpFromANode (
+  IN       UINT8       CurrentNode,
+  IN       STATE_DATA  *State
+  )
+{
+  if (CurrentNode != 0) {
+    // Disable routing tables on CurrentNode
+    State->Nb->DisableRoutingTables (CurrentNode, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Dynamically Discover all coherent devices in the system.
+ *
+ * @HtFeatMethod{::F_COHERENT_DISCOVERY}
+ *
+ * Initialize some basics like Node IDs and total Nodes found in the
+ * process. As we go we also build a representation of the discovered
+ * system which we will use later to program the routing tables.
+ * During this step, the routing is via default Link back to BSP and
+ * to each new Node on the Link it was discovered on (no coherency is
+ * active yet).
+ *
+ * In the case of multiple nodes per processor, do a one deep exploration of internal links
+ * to ensure those node pairs are always numbered n, n + 1.
+ *
+ * @param[in,out] State     our global state
+ *
+ */
+VOID
+CoherentDiscovery (
+  IN OUT   STATE_DATA *State
+  )
+{
+  UINT8 CurrentNode;
+  UINT8 OneDeepNode;
+  UINT8 OneDeepLink;
+  UINT8 CurrentLink;
+  UINT8 LogicalProcessor;
+  EXPLORE_NODE_STATUS ExplorationStatus;
+  LINK_ITERATOR_STATUS LinkIteratorStatus;
+  NEW_NODE_SAVED_INFO_ITEM NewNodeSavedInfoItems [MAX_NODES];
+  NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo;
+
+  // Initially no info exists for any node, but the BSP is part of logical processor zero.
+  for (CurrentNode = 0; CurrentNode < MAX_NODES; CurrentNode++) {
+    NewNodeSavedInfoItems [CurrentNode] = NoInfoSavedYet;
+  }
+  NewNodeSavedInfoItems[0].LogicalProcessor = 0;
+  NewNodeSavedInfoItems[0].HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
+  State->Nb->GetModuleInfo (0, &NewNodeSavedInfoItems[0].NewModuleType, &NewNodeSavedInfoItems[0].NewModule, State->Nb);
+  NewNodeSavedInfo = (NEW_NODE_SAVED_INFO_LIST) NewNodeSavedInfoItems;
+
+  CurrentNode = 0;
+  CurrentLink = LINK_ITERATOR_BEGIN;
+  LogicalProcessor = 0;
+  // An initial status, for node zero if you will.
+  ExplorationStatus = ExploreNodeStatusGood;
+
+  //
+  // Entries are always added in pairs, the even indices are the 'source'
+  // side closest to the BSP, the odd indices are the 'destination' side
+  //
+
+  while ((CurrentNode <= State->NodesDiscovered) && (ExplorationStatus != ExploreNodeStatusStop)) {
+    StartFromANewNode (CurrentNode, State);
+
+    //
+    // Explore all internal links
+    //
+    LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
+
+    while ((LinkIteratorStatus == LinkIteratorInternal) &&
+           (ExplorationStatus != ExploreNodeStatusStop)) {
+      if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
+        ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
+        if ((ExplorationStatus == ExploreNodeStatusGood) ||
+            (ExplorationStatus == ExploreNodeStatusNew)) {
+          AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
+        }
+      }
+      LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
+    }
+    if (CurrentNode == 0) {
+      // The BSP processor is completely discovered now.
+      ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
+      LogicalProcessor++;
+    }
+
+    //
+    // Explore all the external links from this node.
+    //
+
+    // Starting this iteration using the link that we last got in the iteration above.
+    while ((LinkIteratorStatus == LinkIteratorExternal) &&
+           (ExplorationStatus != ExploreNodeStatusStop)) {
+      if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
+        ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
+        if (ExplorationStatus == ExploreNodeStatusNew) {
+          AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
+          // If this is a new node, we need to explore to its internal mate, if any.
+          // This allows us to keep internal node pairs as ids n, n+1
+          // We use special link and node variables so we can keep our context.
+          OneDeepLink = 0xFF;
+          OneDeepNode = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
+          StartFromANewNode (OneDeepNode, State);
+          LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
+          while ((LinkIteratorStatus == LinkIteratorInternal) &&
+                 (ExplorationStatus != ExploreNodeStatusStop)) {
+            if (IsLinkToAdd (OneDeepNode, OneDeepLink, State)) {
+              ExplorationStatus = ExploreNode (OneDeepNode, OneDeepLink, LogicalProcessor, NewNodeSavedInfo, State);
+              if ((ExplorationStatus == ExploreNodeStatusGood) ||
+                  (ExplorationStatus == ExploreNodeStatusNew)) {
+                AddLinkToSystem (OneDeepNode, OneDeepLink, (OneDeepNode + 1), State);
+              }
+            }
+            LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
+          }
+          // Since we completed all the node's internal links, we found all the nodes in that processor.
+          ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
+          LogicalProcessor++;
+          // Restore node to discoverable state.  Otherwise you can't tell what links it is connected on.
+          BackUpFromANode (OneDeepNode, State);
+        } else {
+          if (ExplorationStatus == ExploreNodeStatusGood) {
+            AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
+          }
+        }
+      }
+      LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
+    }
+    CurrentNode++;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
new file mode 100755
index 0000000000..9331540e35
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatDynamicDiscovery.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * Coherent Discovery Interface.
+ *
+ * Contains interface to the coherent discovery feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_DYNAMIC_DISCOVERY_H_
+#define _HT_FEAT_DYNAMIC_DISCOVERY_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Dynamically Discover all coherent devices in the system.
+ *
+ */
+VOID
+CoherentDiscovery (
+  IN OUT   STATE_DATA *State
+  );
+
+#endif  /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
new file mode 100755
index 0000000000..1b25dd7c41
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.c
@@ -0,0 +1,215 @@
+/**
+ * @file
+ *
+ * Routines for re-ganging Links.
+ *
+ * Implement the reganging feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htFeatGanging.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATGANGING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ * @HtFeatMethod{::F_REGANG_LINKS}
+ *
+ * If they do, update the port list data to indicate that this should be done.
+ * @note  no actual hardware state is changed in this routine.
+ *
+ * @param[in,out] State          Our global state
+ */
+VOID
+RegangLinks (
+  IN OUT   STATE_DATA *State
+  )
+{
+  FINAL_LINK_STATE FinalLinkState;
+  UINT8 i;
+  UINT8 j;
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    // Data validation
+    ASSERT ((*State->PortList)[i].Type < 2 && (*State->PortList)[i].Link < State->Nb->MaxLinks);
+    ASSERT ((*State->PortList)[i + 1].Type < 2 && (*State->PortList)[i + 1].Link < State->Nb->MaxLinks);
+
+    // Regang is false unless we pass all conditions below
+    (*State->PortList)[i].SelRegang = FALSE;
+    (*State->PortList)[i + 1].SelRegang = FALSE;
+
+    // Only process cpu to cpu Links
+    if ( ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) ||
+         ((*State->PortList)[i + 1].Type != PORTLIST_TYPE_CPU)) {
+      continue;
+    }
+
+    for (j = i + 2; j < State->TotalLinks*2; j += 2) {
+      // Only process cpu to cpu Links
+      if ( ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) ||
+           ((*State->PortList)[j + 1].Type != PORTLIST_TYPE_CPU) ) {
+        continue;
+      }
+
+      // Links must be from the same source
+      if ((*State->PortList)[i].NodeID != (*State->PortList)[j].NodeID) {
+        continue;
+      }
+
+      // Link must be to the same target
+      if ((*State->PortList)[i + 1].NodeID != (*State->PortList)[j + 1].NodeID) {
+        continue;
+      }
+
+      // Ensure same source base port
+      if (((*State->PortList)[i].Link & 3) != ((*State->PortList)[j].Link & 3)) {
+        continue;
+      }
+
+      // Ensure same destination base port
+      if (((*State->PortList)[i + 1].Link & 3) != ((*State->PortList)[j + 1].Link & 3)) {
+        continue;
+      }
+
+      // Ensure subLink0 routes to subLink0
+      if (((*State->PortList)[i].Link & 4) != ((*State->PortList)[i + 1].Link & 4)) {
+        continue;
+      }
+
+      // (therefore subLink1 routes to subLink1)
+      ASSERT (((*State->PortList)[j].Link & 4) == ((*State->PortList)[j + 1].Link & 4));
+
+      FinalLinkState = State->HtInterface->GetSkipRegang ((*State->PortList)[i].NodeID,
+                                         (*State->PortList)[i].Link & 0x03,
+                                         (*State->PortList)[i + 1].NodeID,
+                                         (*State->PortList)[i + 1].Link & 0x03,
+                                         State);
+      if (FinalLinkState == MATCHED) {
+        continue;
+      } else if (FinalLinkState == POWERED_OFF) {
+        // StopLink will be done on the sublink 1, thus OR in 4 to the link to ensure it.
+        State->Nb->StopLink ((*State->PortList)[i].NodeID, ((*State->PortList)[i].Link | 4), State, State->Nb);
+        State->Nb->StopLink ((*State->PortList)[i + 1].NodeID, ((*State->PortList)[i + 1].Link | 4), State, State->Nb);
+      }
+
+      //
+      // Create a ganged portlist entry for the two regang-able subLinks.
+      //
+      // All info will be that of subLink zero.
+      // (If Link discovery order was other than ascending, fix the .Pointer field too.)
+      //
+      //
+      if (((*State->PortList)[i].Link & 4) != 0) {
+        (*State->PortList)[i].Pointer = (*State->PortList)[j].Pointer;
+        (*State->PortList)[i + 1].Pointer = (*State->PortList)[j + 1].Pointer;
+      }
+      (*State->PortList)[i].Link &= 0x03;                       // Force to point to subLink0
+      (*State->PortList)[i + 1].Link &= 0x03;
+      // If powered off, sublink 1 is removed but the link is still 8 bits.
+      if (FinalLinkState != POWERED_OFF) {
+        (*State->PortList)[i].SelRegang = TRUE;                   // Enable Link reganging
+        (*State->PortList)[i + 1].SelRegang = TRUE;
+        (*State->PortList)[i].PrvWidthOutCap = HT_WIDTH_16_BITS;
+        (*State->PortList)[i + 1].PrvWidthOutCap = HT_WIDTH_16_BITS;
+        (*State->PortList)[i].PrvWidthInCap = HT_WIDTH_16_BITS;
+        (*State->PortList)[i + 1].PrvWidthInCap = HT_WIDTH_16_BITS;
+      }
+
+      // Delete PortList[j, j + 1], slow but easy to debug implementation
+      State->TotalLinks--;
+      LibAmdMemCopy (&((*State->PortList)[j]),
+                     &((*State->PortList)[j + 2]),
+                     sizeof (PORT_DESCRIPTOR)*(State->TotalLinks* 2 - j),
+                     State->ConfigHandle);
+      LibAmdMemFill (&((*State->PortList)[State->TotalLinks * 2]), INVALID_LINK, (sizeof (PORT_DESCRIPTOR) * 2), State->ConfigHandle);
+
+      break; // Exit loop, advance to PortList[i + 2]
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
new file mode 100755
index 0000000000..48ba35b121
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatGanging.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * Link Reganging Interface.
+ *
+ * Contains interface to the Reganging feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *-----------------------------------------------------------------------------
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_GANGING_H_
+#define _HT_FEAT_GANGING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ */
+VOID
+RegangLinks (
+  IN OUT   STATE_DATA *State
+  );
+
+#endif  /* _HT_FEAT_GANGING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
new file mode 100755
index 0000000000..24fd5cc9a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.c
@@ -0,0 +1,313 @@
+/**
+ * @file
+ *
+ * Non-Coherent Discovery Routines.
+ *
+ * Contains routines for enumerating and initializing non-coherent devices.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htFeatNoncoherent.h"
+#include "htFeatOptimization.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                             Algorithms                              ***
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Process a non-coherent Link.
+ *
+ * @HtFeatMethod{::F_PROCESS_LINK}
+ *
+ * Enable a range of bus numbers, and set the device ID for all devices found.  Add
+ * non-coherent devices, links to the system data structure.
+ *
+ * @param[in]     Node          Node on which to process nc init
+ * @param[in]     Link          The non-coherent Link on that Node
+ * @param[in]     IsCompatChain Is this the chain with the southbridge? TRUE if yes.
+ * @param[in,out] State         our global state
+ */
+VOID
+ProcessLink (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 SecBus;
+  UINT8 SubBus;
+  UINT32 CurrentBuid;
+  UINT32 Temp;
+  UINT32 UnitIdCount;
+  PCI_ADDR CurrentPtr;
+  UINT8 Depth;
+  BUID_SWAP_LIST *SwapPtr;
+  UINT8  LastLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < State->Nb->MaxLinks));
+
+  if (!State->HtInterface->GetOverrideBusNumbers (Node, Link, &SecBus, &SubBus, State)) {
+    // Assign Bus numbers
+    if (State->AutoBusCurrent >= State->HtBlock->AutoBusMax) {
+      //  If we run out of Bus Numbers, notify and skip this chain
+      //
+      IDS_ERROR_TRAP;
+      NotifyErrorNcohBusMaxExceed (Node, Link, State->AutoBusCurrent, State);
+      return;
+    }
+
+    if (State->UsedCfgMapEntries >= 4) {
+      // If we have used all the PCI Config maps we can't add another chain.
+      // Notify and if call back is unimplemented or returns, skip this chain.
+      //
+      IDS_ERROR_TRAP;
+      NotifyErrorNcohCfgMapExceed (Node, Link, State);
+      return;
+    }
+
+    SecBus = State->AutoBusCurrent;
+    SubBus = SecBus + State->HtBlock->AutoBusIncrement - 1;
+    State->AutoBusCurrent = State->AutoBusCurrent + State->HtBlock->AutoBusIncrement;
+  }
+
+  State->Nb->SetConfigAddrMap (State->UsedCfgMapEntries, SecBus, SubBus, Node, Link, State, State->Nb);
+  State->UsedCfgMapEntries++;
+
+  if (State->HtInterface->GetManualBuidSwapList (Node, Link, &SwapPtr, State)) {
+    // Manual non-coherent BUID assignment
+    AGESA_TESTPOINT (TpProcHtManualNc, State->ConfigHandle);
+
+
+    if (!IsCompatChain || !State->IsUsingRecoveryHt) {
+      //  If this is the not southbridge chain or Recovery HT was not used
+      // then we need to assign BUIDs here.
+      //
+      Depth = 0;
+      // Assign BUID's per manual override
+      while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
+        CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, SwapPtr->Swaps[Depth].FromId, 0, 0);
+        if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
+          // Set the device's BUID field [20:16] to the current buid
+          CurrentBuid = SwapPtr->Swaps[Depth].ToId;
+          LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
+          Depth++;
+        } else {
+          // All non-coherent devices must have a slave interface capability.
+          ASSERT (FALSE);
+          break;
+        }
+      }
+    }
+
+    // Build chain of devices. Do this even if Recovery HT assign BUIDs for this chain.
+    Depth = 0;
+    while (SwapPtr->FinalIds[Depth] != 0xFF) {
+      ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
+      (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
+      // Note: depth == 0 is true before depth > 0. This makes LastLink variable work.
+      if (Depth == 0) {
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
+      } else {
+        // Fill in the host side port.  Link and base pointer can be deduced from the upstream link's
+        // downstream port.
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
+        (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Pointer;
+      }
+
+      (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
+
+      CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, (SwapPtr->FinalIds[Depth] & 0x3F), 0, 0);
+      if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
+        (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
+      } else {
+        // All non-coherent devices must have a slave interface capability.
+        ASSERT (FALSE);
+        break;
+      }
+
+      // Bit 6 indicates whether orientation override is desired.
+      // Bit 7 indicates the upstream Link if overriding.
+      //
+      // assert catches at least the one known incorrect setting, that a non-zero link
+      // is specified, but override desired is not set.
+      ASSERT (((SwapPtr->FinalIds[Depth] & 0x40) != 0) || ((SwapPtr->FinalIds[Depth] & 0x80) == 0));
+      if ((SwapPtr->FinalIds[Depth] & 0x40) != 0) {
+        // Override the device's orientation
+        LastLink = SwapPtr->FinalIds[Depth] >> 7;
+      } else {
+        // Detect the device's orientation, by reading the Master Host bit [26]
+        LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
+        LastLink = (UINT8)Temp;
+      }
+      (*State->PortList)[(State->TotalLinks * 2) + 1].Link = LastLink;
+
+      Depth++;
+      State->TotalLinks++;
+    }
+  } else {
+    // Automatic non-coherent device detection
+    AGESA_TESTPOINT (TpProcHtAutoNc, State->ConfigHandle);
+    Depth = 0;
+    CurrentBuid = 1;
+    for (; ; ) {
+      CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, 0, 0, 0);
+
+      LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
+      if (Temp == ((UINT32)0xFFFFFFFF)) {
+        // No device found at CurrentPtr
+        break;
+      }
+
+      ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
+
+      (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
+      if (Depth == 0) {
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
+      } else {
+        // Fill in the host side port.  Link and base pointer can be deduced from the upstream link's
+        // downstream port.
+        (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
+        (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
+        (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
+        (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Pointer;
+      }
+
+      (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
+      (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
+
+      if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
+
+        // Get device's unit id count [25:21]
+        LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIdCount, State->ConfigHandle);
+        if (((UnitIdCount + CurrentBuid) > MAX_BUID) || ((SecBus == 0) && ((UnitIdCount + CurrentBuid) > 24))) {
+          // An error handler for the case where we run out of BUID's on a chain
+          NotifyErrorNcohBuidExceed (Node, Link, Depth, (UINT8)CurrentBuid, (UINT8)UnitIdCount, State);
+          IDS_ERROR_TRAP;
+          break;
+        }
+        LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
+
+        CurrentPtr.Address.Device = CurrentBuid;
+        LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
+        if (Temp != CurrentBuid) {
+          // An error handler for this error,
+          // this often occurs in new BIOS ports and it means you need to use a Manual BUID Swap List.
+          NotifyErrorNcohDeviceFailed (Node, Link, Depth, (UINT8)CurrentBuid, State);
+          IDS_ERROR_TRAP;
+          break;
+        }
+
+        LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
+        (*State->PortList)[(State->TotalLinks * 2) + 1].Link = (UINT8)Temp;
+        (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
+
+        Depth++;
+        State->TotalLinks++;
+        CurrentBuid += UnitIdCount;
+      } else {
+        // All non-coherent devices must have a slave interface capability.
+        ASSERT (FALSE);
+        break;
+      }
+    }
+    // Provide information on automatic device results
+    NotifyInfoNcohAutoDepth (Node, Link, (Depth - 1), State);
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.h
new file mode 100755
index 0000000000..f19fffd602
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatNoncoherent.h
@@ -0,0 +1,80 @@
+/**
+ * @file
+ *
+ * Non-Coherent Discovery Interface.
+ *
+ * Contains interface to the Non-Coherent Link processing feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_NONCOHERENT_H_
+#define _HT_FEAT_NONCOHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Process a non-coherent Link.
+ *
+ */
+VOID
+ProcessLink (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  );
+
+#endif  /* _HT_FEAT_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
new file mode 100755
index 0000000000..21f033067d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.c
@@ -0,0 +1,886 @@
+/**
+ * @file
+ *
+ * Link Optimization Routines.
+ *
+ * Contains routines for determining width, frequency, and other
+ * Link features
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htFeatOptimization.h"
+#include "htNotify.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE
+
+extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define PCI_CONFIG_COMMAND_REG04  4
+#define PCI_CONFIG_REVISION_REG08 8
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Given the bits set in the register field, return the width it represents.
+ *
+ * As invalid width values or encodings are rare except during debug, catch those using
+ * ASSERT().  This means theoretically we are returning an incorrect result if that
+ * happens.  The default chosen for the result is arbitrarily 8 bits.  This is likely
+ * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
+ * Hardware often ignores writes of invalid width encodings.
+ *
+ * @note This routine is used for CPUs as well as IO devices, as all comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]     Value The bits for the register
+ *
+ * @return The width
+ */
+UINT8
+STATIC
+ConvertBitsToWidth (
+  IN       UINT8       Value
+  )
+{
+  UINT8 Result;
+
+  Result = 0;
+
+  switch (Value) {
+
+  case  1:
+    Result = 16;
+    break;
+
+  case  0:
+    Result = 8;
+    break;
+
+  case 3:
+    Result = 32;
+    break;
+
+  case  5:
+    Result = 4;
+    break;
+
+  case  4:
+    Result = 2;
+    break;
+
+  default:
+    ASSERT (FALSE);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ *
+ * As invalid width values or encodings are rare except during debug, catch those using
+ * ASSERT().  This means theoretically we are returning an incorrect result if that
+ * happens.  The default chosen for the result is arbitrarily 8 bits.  This is likely
+ * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
+ * Hardware often ignores writes of invalid width encodings.
+ *
+ * @note This routine is used for CPUs as well as IO devices, as all comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]     Value   the width Value
+ *
+ * @return The bits for the register
+ */
+UINT8
+ConvertWidthToBits (
+  IN       UINT8       Value
+  )
+{
+  UINT8 Result;
+
+  Result = 8;
+
+  switch (Value) {
+
+  case 16:
+    Result = 1;
+    break;
+
+  case 8:
+    Result = 0;
+    break;
+
+  case 32:
+    Result = 3;
+    break;
+
+  case 4:
+    Result = 5;
+    break;
+
+  case 2:
+    Result = 4;
+    break;
+
+  default:
+    ASSERT (FALSE);
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Access HT Link Control Register.
+ *
+ * @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS}
+ *
+ * Provide a common routine for accessing the HT Link Control registers (84, a4, c4,
+ * e4), to enforce not clearing the HT CRC error bits.  Replaces direct use of
+ * AmdPCIWriteBits().
+ *
+ * @note: This routine is called for CPUs as well as IO Devices! All comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]     Reg      the PCI config address the control register
+ * @param[in]     HiBit    the high bit number
+ * @param[in]     LoBit    the low bit number
+ * @param[in]     Value    the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]     State    Our state, config handle for lib
+ */
+VOID
+SetHtControlRegisterBits (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT32 Temp;
+  UINT32 mask;
+
+  ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0));
+  ASSERT ((HiBit < 8) || (LoBit > 9));
+
+  // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
+  if ((HiBit - LoBit) != 31) {
+    mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1);
+  } else {
+    mask = (UINT32)0xFFFFFFFF;
+  }
+
+  LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+  Temp &= ~(mask << LoBit);
+  Temp |= (*Value & mask) << LoBit;
+  Temp &= (UINT32)HT_CONTROL_CLEAR_CRC;
+  LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set HT Frequency register for IO Devices
+ *
+ * Provide a common routine for accessing the HT Link Frequency registers at offset 8
+ * and 0x10, to enforce not clearing the HT Link error bits.  Replaces direct use of
+ * AmdPCIWriteBits().
+ *
+ * @note This routine is called for IO Devices only!! All comply to the
+ * "HyperTransport I/O Link Specification ".
+ *
+ * @param[in]    Reg       the PCI config address the control register
+ * @param[in]    Hibit     the high bit number
+ * @param[in]    Lobit     the low bit number
+ * @param[in]    Value     the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]    State     Our state, config handle for lib
+ */
+VOID
+STATIC
+SetHtIoFrequencyRegisterBits (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       Hibit,
+  IN       UINT8       Lobit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  )
+{
+  UINT32 Mask;
+  UINT32 Temp;
+
+  ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
+  ASSERT ((Hibit < 12) || (Lobit > 14));
+
+  // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+  if ((Hibit - Lobit) != 31) {
+    Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
+  } else {
+    Mask = (UINT32)0xFFFFFFFF;
+  }
+
+  LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+  Temp &= ~(Mask << Lobit);
+  Temp |= (*Value & Mask) << Lobit;
+  Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
+  LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtFeatMethod{::F_GATHER_LINK_DATA}
+ *
+ * For all discovered Links, populate the port list with the frequency and width
+ * capabilities. Gather support data for:
+ * - Unit ID Clumping
+ *
+ * @param[in]     State our global state, port list
+ */
+VOID
+GatherLinkData (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 i;
+  PCI_ADDR LinkBase;
+  PCI_ADDR Reg;
+  UINT32 Bits;
+  UINT8 Revision;
+
+  // Get the capability base for whatever device type the link port is on
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+    if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+      LinkBase = State->Nb->MakeLinkBase ((*State->PortList)[i].NodeID, (*State->PortList)[i].Link, State->Nb);
+      (*State->PortList)[i].Pointer = LinkBase;
+    } else {
+      LinkBase = (*State->PortList)[i].Pointer;
+      if ((*State->PortList)[i].Link == 1) {
+        LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
+      }
+    }
+
+    // Getting the Width is standard across device types
+    Reg = LinkBase;
+    Reg.Address.Register += HTSLAVE_LINK_CONTROL_0_REG;
+    LibAmdPciReadBits (Reg, 22, 20, &Bits, State->ConfigHandle);
+    (*State->PortList)[i].PrvWidthOutCap = ConvertBitsToWidth ((UINT8)Bits);
+
+    LibAmdPciReadBits (Reg, 18, 16, &Bits, State->ConfigHandle);
+    (*State->PortList)[i].PrvWidthInCap = ConvertBitsToWidth ((UINT8)Bits);
+
+    // Get Frequency and other device type specific features
+    if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+      State->Nb->GatherLinkFeatures (&(*State->PortList)[i], State->HtInterface, State->Nb);
+    } else {
+      Reg = LinkBase;
+      Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
+      LibAmdPciReadBits (Reg, 31, 16, &Bits, State->ConfigHandle);
+      (*State->PortList)[i].PrvFrequencyCap = Bits;
+
+      // Unit ID Clumping Support
+      if (State->IsUsingUnitIdClumping) {
+        if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
+          Reg.Address.Register += HTUNIT_SUPPORT_REG;
+          LibAmdPciReadBits (Reg, 31, 0, &Bits, State->ConfigHandle);
+        } else {
+          // Not there, that's ok, we don't know that it should have one.
+          // Check for Passive support. (Bit 0 won't be set if full support is implemented,
+          // so we can use it to indicate passive support in our portlist struct).
+          Reg = LinkBase;
+          Reg.Address.Register += HTSLAVE_FEATURECAP_REG;
+          Bits = 1;
+          LibAmdPciWriteBits (Reg, 5, 5, &Bits, State->ConfigHandle);
+          LibAmdPciReadBits (Reg, 5, 5, &Bits, State->ConfigHandle);
+        }
+        (*State->PortList)[i].ClumpingSupport = Bits;
+      } else {
+        (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
+      }
+
+      Reg = LinkBase;
+      Reg.Address.Register = PCI_CONFIG_REVISION_REG08;
+      LibAmdPciReadBits ( LinkBase, 7, 0, &Bits, State->ConfigHandle);
+      Revision = (UINT8) Bits;
+
+      LinkBase.Address.Register = 0;
+      LibAmdPciRead (AccessWidth32, LinkBase, &Bits, State->ConfigHandle);
+
+      State->HtInterface->GetDeviceCapOverride ((*State->PortList)[i].NodeID,
+                           (*State->PortList)[i].HostLink,
+                           (*State->PortList)[i].HostDepth,
+                           (*State->PortList)[i].Pointer,
+                           Bits,
+                           Revision,
+                           (*State->PortList)[i].Link,
+                           &((*State->PortList)[i].PrvWidthInCap),
+                           &((*State->PortList)[i].PrvWidthOutCap),
+                           &((*State->PortList)[i].PrvFrequencyCap),
+                           &((*State->PortList)[i].ClumpingSupport),
+                           State);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Optimize Links.
+ *
+ * @HtFeatMethod{::F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY}
+ *
+ * For all Links:
+ * Examine both sides of a Link and determine the optimal frequency and width,
+ * taking into account externally provided limits and enforcing any other limit
+ * or matching rules as applicable except subLink balancing. Update the port
+ * list data with the optimal settings.
+ *
+ * @note no hardware state changes in this routine.
+ *
+ * @param[in,out]    State         Process and update portlist
+ */
+VOID
+SelectOptimalWidthAndFrequency (
+  IN OUT   STATE_DATA   *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 Freq;
+  UINT32 Temp;
+  UINT32 CbPcbFreqLimit;
+  UINT8 CbPcbABDownstreamWidth;
+  UINT8 CbPcbBAUpstreamWidth;
+
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    CbPcbFreqLimit = HT_FREQUENCY_NO_LIMIT;
+    CbPcbABDownstreamWidth = HT_WIDTH_16_BITS;
+    CbPcbBAUpstreamWidth = HT_WIDTH_16_BITS;
+
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+      State->HtInterface->GetCpu2CpuPcbLimits ((*State->PortList)[i].NodeID,
+                           (*State->PortList)[i].Link,
+                           (*State->PortList)[i + 1].NodeID,
+                           (*State->PortList)[i + 1].Link,
+                           &CbPcbABDownstreamWidth,
+                           &CbPcbBAUpstreamWidth,
+                           &CbPcbFreqLimit,
+                           State
+        );
+    } else {
+      State->HtInterface->GetIoPcbLimits ((*State->PortList)[i + 1].NodeID,
+                      (*State->PortList)[i + 1].HostLink,
+                      (*State->PortList)[i + 1].HostDepth,
+                      &CbPcbABDownstreamWidth,
+                      &CbPcbBAUpstreamWidth,
+                      &CbPcbFreqLimit,
+                      State
+        );
+    }
+
+    Temp = (*State->PortList)[i].PrvFrequencyCap;
+    Temp &= (*State->PortList)[i + 1].PrvFrequencyCap;
+    Temp &= CbPcbFreqLimit;
+    (*State->PortList)[i].CompositeFrequencyCap = (UINT32)Temp;
+    (*State->PortList)[i + 1].CompositeFrequencyCap = (UINT32)Temp;
+
+    ASSERT (Temp != 0);
+    Freq = LibAmdBitScanReverse (Temp);
+    (*State->PortList)[i].SelFrequency = Freq;
+    (*State->PortList)[i + 1].SelFrequency = Freq;
+
+    Temp = (*State->PortList)[i].PrvWidthOutCap;
+    if ((*State->PortList)[i + 1].PrvWidthInCap < Temp) {
+      Temp = (*State->PortList)[i + 1].PrvWidthInCap;
+    }
+    if (CbPcbABDownstreamWidth < Temp) {
+      Temp = CbPcbABDownstreamWidth;
+    }
+    (*State->PortList)[i].SelWidthOut = (UINT8)Temp;
+    (*State->PortList)[i + 1].SelWidthIn = (UINT8)Temp;
+
+    Temp = (*State->PortList)[i].PrvWidthInCap;
+    if ((*State->PortList)[i + 1].PrvWidthOutCap < Temp) {
+      Temp = (*State->PortList)[i + 1].PrvWidthOutCap;
+    }
+    if (CbPcbBAUpstreamWidth < Temp) {
+      Temp = CbPcbBAUpstreamWidth;
+    }
+    (*State->PortList)[i].SelWidthIn = (UINT8)Temp;
+    (*State->PortList)[i + 1].SelWidthOut = (UINT8)Temp;
+  }
+  // Calculate unit id clumping
+  //
+  // Find the root of each IO Chain, process the chain for clumping support.
+  // The root is always the first link of the chain in the port list.
+  // Clumping is not device link specific, so we can just look at the upstream ports (j+1). Use ASSERTs to sanity
+  // check the downstream ports (j).  If any device on the chain does not support clumping, the entire chain will be
+  // disabled for clumping.
+  // After analyzing the clumping support on the chain the CPU's portlist has the enable mask.  Update all the
+  // IO Devices on the chain with the enable mask.  If any device's only have passive support, that is already enabled.
+  //
+  if (State->IsUsingUnitIdClumping) {
+    for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+      if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_IO)) {
+        (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
+        if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
+          (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[i + 1].ClumpingSupport;
+          for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
+            if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
+              if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
+                  ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
+                ASSERT (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
+                        ((*State->PortList)[i].Link == (*State->PortList)[j].HostLink));
+                if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
+                  ASSERT ((((*State->PortList)[j + 1].ClumpingSupport & HT_CLUMPING_PASSIVE) == 0) ||
+                          (((*State->PortList)[j + 1].ClumpingSupport & ~(HT_CLUMPING_PASSIVE)) == 0));
+                  (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[j + 1].ClumpingSupport;
+                } else {
+                  (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
+                  break;
+                }
+              }
+            }
+          }
+          if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
+            (*State->PortList)[i + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
+          }
+          for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
+            if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
+              if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
+                  ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
+                if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
+                  (*State->PortList)[j + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
+                  // The downstream isn't really passive, just mark it so in order to write the device only once.
+                  (*State->PortList)[j].ClumpingSupport = HT_CLUMPING_PASSIVE;
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtFeatMethod{::F_SET_LINK_DATA}
+ *
+ * @param[in]     State   our global state, port list
+ */
+VOID
+SetLinkData (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 i;
+  PCI_ADDR LinkBase;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  UINT32 Widthin;
+  UINT32 Widthout;
+  UINT32 Bits;
+  PCI_ADDR CurrentPtr;
+  HTIDS_PORT_OVERRIDE_LIST PortOverrides;
+
+  PortOverrides = NULL;
+
+  for (i = 0; i < (State->TotalLinks * 2); i++) {
+
+    ASSERT ((*State->PortList)[i & 0xFE].SelWidthOut == (*State->PortList)[ (i & 0xFE) + 1].SelWidthIn);
+    ASSERT ((*State->PortList)[i & 0xFE].SelWidthIn == (*State->PortList)[ (i & 0xFE) + 1].SelWidthOut);
+    ASSERT ((*State->PortList)[i & 0xFE].SelFrequency == (*State->PortList)[ (i & 0xFE) + 1].SelFrequency);
+
+    if ((*State->PortList)[i].SelRegang) {
+      ASSERT ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU);
+      ASSERT ((*State->PortList)[i].Link < 4);
+      State->Nb->SetLinkRegang (
+        (*State->PortList)[i].NodeID,
+        (*State->PortList)[i].Link,
+        State->Nb
+        );
+    }
+
+    //
+    // IDS port override for CPUs and IO Devices
+    //
+    pf_HtIdsGetPortOverride ((BOOLEAN) ((i & 1) == 0), &(*State->PortList)[i], &(*State->PortList)[i + 1], &PortOverrides, State);
+
+    LinkBase = (*State->PortList)[i].Pointer;
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[i].Link == 1)) {
+      LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
+    }
+
+    // HT CRC Feature, set if configured.  The default is not to set it, because with some chipsets it
+    // will lock up if done here.
+    if (State->IsSetHtCrcFlood) {
+      Temp = 1;
+      Reg = LinkBase;
+      Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+      State->HtFeatures->SetHtControlRegisterBits (Reg, 1, 1, &Temp, State);
+      if ((*State->PortList)[i].Type == PORTLIST_TYPE_IO) {
+        // IO Devices also need to have SERR enabled.
+        Reg = LinkBase;
+        Reg.Address.Register = PCI_CONFIG_COMMAND_REG04;
+        LibAmdPciWriteBits (Reg, 8, 8, &Temp, State->ConfigHandle);
+      }
+    }
+
+    // Some IO devices don't work properly when setting widths, so write them in a single operation,
+    // rather than individually.
+    //
+    Widthout = ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
+    ASSERT (Widthout == 1 || Widthout == 0 || Widthout == 5 || Widthout == 4);
+    Widthin = ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
+    ASSERT (Widthin == 1 || Widthin == 0 || Widthin == 5 || Widthin == 4);
+
+    Temp = (Widthin & 7) | ((Widthout & 7) << 4);
+    Reg = LinkBase;
+    Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
+    State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
+
+    Temp = (*State->PortList)[i].SelFrequency;
+    if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+      State->Nb->SetLinkFrequency (
+        (*State->PortList)[i].NodeID,
+        (*State->PortList)[i].Link,
+        (UINT8)Temp,
+        State->Nb
+        );
+      printk(BIOS_DEBUG, "Node:0x%02x Link:0x%02x, HT frequency = 0x%02x\n",
+		      (*State->PortList)[i].NodeID,
+		      (*State->PortList)[i].Link,
+		      (UINT8)Temp);
+    } else {
+      ASSERT (Temp <= HT_FREQUENCY_2600M);
+      // Write the frequency setting
+      Reg = LinkBase;
+      Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
+      SetHtIoFrequencyRegisterBits (Reg, 11, 8, &Temp, State);
+
+      // Handle additional HT3 frequency requirements, if needed,
+      // or clear them if switching down to ht1 on a warm reset.
+      // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
+      //
+      // Even though we assert if debugging, we need to check that the capability was
+      // found always, since this is an unknown hardware device, also we are taking
+      // unqualified frequency from the external interface (could be trying to do ht3
+      // on an ht1 IO device).
+      //
+
+      if (Temp > HT_FREQUENCY_1000M) {
+        // Enabling features if gen 3
+        Bits = 1;
+      } else {
+        // Disabling features if gen 1
+        Bits = 0;
+      }
+
+      // Retry Enable
+      if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_RETRY_CAPABILITY, &CurrentPtr, State)) {
+        ASSERT ((*State->PortList)[i].Link < 2);
+        CurrentPtr.Address.Register += HTRETRY_CONTROL_REG;
+        LibAmdPciWriteBits (CurrentPtr,
+                            ((*State->PortList)[i].Link * 16),
+                            ((*State->PortList)[i].Link * 16),
+                            &Bits,
+                            State->ConfigHandle);
+      } else {
+        //  If we are turning it off, that may mean the device was only ht1 capable,
+        // so don't complain that we can't do it.
+        //
+        if (Bits != 0) {
+          NotifyWarningOptRequiredCapRetry ((*State->PortList)[i].NodeID,
+                                            (*State->PortList)[i].HostLink,
+                                            (*State->PortList)[i].HostDepth,
+                                            State);
+        }
+      }
+
+      // Scrambling enable
+      if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_GEN3_CAPABILITY, &CurrentPtr, State)) {
+        ASSERT ((*State->PortList)[i].Link < 2);
+        CurrentPtr.Address.Register = CurrentPtr.Address.Register +
+          HTGEN3_LINK_TRAINING_0_REG +
+          ((*State->PortList)[i].Link * HTGEN3_LINK01_OFFSET);
+        LibAmdPciWriteBits (CurrentPtr, 3, 3, &Bits, State->ConfigHandle);
+      } else {
+        //  If we are turning it off, that may mean the device was only ht1 capable,
+        // so don't complain that we can't do it.
+        //
+        if (Bits != 0) {
+          NotifyWarningOptRequiredCapGen3 ((*State->PortList)[i].NodeID,
+                                           (*State->PortList)[i].HostLink,
+                                           (*State->PortList)[i].HostDepth,
+                                           State);
+        }
+      }
+    }
+    // Enable Unit ID Clumping if supported.
+    if (State->IsUsingUnitIdClumping) {
+      if (((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_PASSIVE) &&
+          ((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_DISABLE)) {
+        Bits = (*State->PortList)[i].ClumpingSupport;
+        if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
+          State->Nb->SetLinkUnitIdClumping (
+            (*State->PortList)[i].NodeID,
+            (*State->PortList)[i].Link,
+            (*State->PortList)[i].ClumpingSupport,
+            State->Nb
+            );
+        } else {
+          if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
+            Reg.Address.Register += HTUNIT_ENABLE_REG;
+            LibAmdPciWriteBits (Reg, 31, 0, &Bits, State->ConfigHandle);
+          } else {
+            // If we found one when gathering support, we have to find one now.
+            ASSERT (FALSE);
+          }
+        }
+      }
+    }
+  }
+}
+
+/*------------------------------------------------------------------------------------------*/
+/**
+ * Find a specific HT capability type.
+ *
+ * Search all the PCI Config space capabilities on any type of device for an
+ * HT capability of the specific subtype.
+ *
+ * @param[in]  DevicePointer     A PCI Config address somewhere in the device config space
+ * @param[in]  CapSubType        The HT capability subtype to find
+ * @param[out] CapabilityBase    The Config space base address of the capability, if found.
+ * @param[in]  State             Our State
+ *
+ * @retval TRUE     the capability was found
+ * @retval FALSE    the capability was not found
+ */
+BOOLEAN
+DoesDeviceHaveHtSubtypeCap (
+  IN       PCI_ADDR         DevicePointer,
+  IN       UINT8            CapSubType,
+     OUT   PCI_ADDR         *CapabilityBase,
+  IN       STATE_DATA       *State
+  )
+{
+  BOOLEAN IsFound;
+  BOOLEAN IsDone;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  UINT32 RegSubType;
+  UINT32 RegSubTypeMask;
+
+  // Set the PCI Config Space base and the match value.
+  IsFound = FALSE;
+  IsDone = FALSE;
+  Reg = DevicePointer;
+  Reg.Address.Register = 0;
+  if (CapSubType < (HT_HOST_CAPABILITY + 1)) {
+    // HT Interface sub type
+    RegSubType = ((UINT32) (CapSubType << 29) | (UINT32)8);
+    RegSubTypeMask = HT_INTERFACE_CAP_SUBTYPE_MASK;
+  } else {
+    // Other HT capability subtype
+    RegSubType = ((UINT32) (CapSubType << 27) | (UINT32)8);
+    RegSubTypeMask = HT_CAP_SUBTYPE_MASK;
+  }
+  (*CapabilityBase).AddressValue = (UINT32)ILLEGAL_SBDFO;
+
+  // Find it
+  do {
+    LibAmdPciFindNextCap (&Reg, State->ConfigHandle);
+    if (Reg.AddressValue != (UINT32)ILLEGAL_SBDFO) {
+      LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
+      // HyperTransport and subtype capability ?
+      if ((Temp & RegSubTypeMask) == RegSubType) {
+        *CapabilityBase = Reg;
+        IsFound = TRUE;
+      }
+      // Some other capability, keep looking
+    } else {
+      //  Not there
+      IsDone = TRUE;
+    }
+  } while (!IsFound && !IsDone);
+
+  return IsFound;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ * @HtFeatMethod{::F_SET_LINK_DATA}
+ *
+ * Effectively, this means HT3 on some links cannot be mixed with HT1 on others.
+ * Scan the CPU to CPU links for this condition and limit those frequencies to HT1
+ * if it is detected.
+ * (Non-coherent links are independent.)
+ *
+ * @param[in,out]   State       global state, port frequency settings.
+ *
+ * @retval          TRUE        Fixup occurred, all coherent links HT1
+ * @retval          FALSE       No changes
+ */
+BOOLEAN
+IsCoherentRetryFixup (
+  IN       STATE_DATA       *State
+  )
+{
+  UINT8 Freq;
+  UINT8 i;
+  UINT8 DetectedFrequencyState;
+  BOOLEAN IsMixed;
+  UINT32 Temp;
+
+  //
+  // detectedFrequencyState:
+  //   0 - initial state
+  //   1 - HT1 Frequencies detected
+  //   2 - HT3 Frequencies detected
+  //
+  IsMixed = FALSE;
+  DetectedFrequencyState = 0;
+
+  // Scan coherent links for a mix of HT3 / HT1
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+      // At this point, Frequency of port [i+1] must equal [i], so just check one of them.
+      switch (DetectedFrequencyState) {
+      case 0:
+        // Set current state to indicate what link frequency we found first
+        if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
+          // HT3 frequencies
+          DetectedFrequencyState = 2;
+        } else {
+          // HT1 frequencies
+          DetectedFrequencyState = 1;
+        }
+        break;
+      case 1:
+        // If HT1 frequency detected, fail any HT3 frequency
+        if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
+          IsMixed = TRUE;
+        }
+        break;
+      case 2:
+        // If HT3 frequency detected, fail any HT1 frequency
+        if ((*State->PortList)[i].SelFrequency <= HT_FREQUENCY_1000M) {
+          IsMixed = TRUE;
+        }
+        break;
+      default:
+        ASSERT (FALSE);
+      }
+      if (IsMixed) {
+        // Don't need to keep checking after we find a mix.
+        break;
+      }
+    }
+  }
+
+  if (IsMixed) {
+    for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+      if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+        // Limit coherent links to HT 1 frequencies.
+        Temp = (*State->PortList)[i].CompositeFrequencyCap & (*State->PortList)[i + 1].CompositeFrequencyCap;
+        Temp &= HT_FREQUENCY_LIMIT_HT1_ONLY;
+        ASSERT (Temp != 0);
+        (*State->PortList)[i].CompositeFrequencyCap = Temp;
+        (*State->PortList)[i + 1].CompositeFrequencyCap = Temp;
+        Freq = LibAmdBitScanReverse (Temp);
+        (*State->PortList)[i].SelFrequency = Freq;
+        (*State->PortList)[i + 1].SelFrequency = Freq;
+      }
+    }
+  }
+  return (IsMixed);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.h
new file mode 100755
index 0000000000..1d1ea70ceb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatOptimization.h
@@ -0,0 +1,139 @@
+/**
+ * @file
+ *
+ * Link Optimization Feature.
+ *
+ * Contains interface for Link Optimization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_OPTIMIZATION_H_
+#define _HT_FEAT_OPTIMIZATION_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ */
+UINT8
+ConvertWidthToBits (
+  IN       UINT8       Value
+  );
+
+/**
+ * Access HT Link Control Register.
+ *
+ */
+VOID
+SetHtControlRegisterBits (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  );
+
+/**
+ * Get Link features into system data structure.
+ *
+ */
+VOID
+GatherLinkData (
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Optimize Links.
+ *
+ */
+VOID
+SelectOptimalWidthAndFrequency (
+  IN OUT   STATE_DATA   *State
+  );
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ */
+VOID
+SetLinkData (
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ */
+BOOLEAN
+IsCoherentRetryFixup (
+  IN       STATE_DATA       *State
+  );
+
+/**
+ * Find a specific HT capability type.
+ *
+ * @retval FALSE    the capability was not found
+ */
+BOOLEAN
+DoesDeviceHaveHtSubtypeCap (
+  IN       PCI_ADDR         DevicePointer,
+  IN       UINT8            CapSubType,
+     OUT   PCI_ADDR         *CapabilityBase,
+  IN       STATE_DATA       *State
+  );
+
+#endif  /* _HT_FEAT_OPTIMIZATION_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
new file mode 100755
index 0000000000..f76b48a107
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.c
@@ -0,0 +1,467 @@
+/**
+ * @file
+ *
+ * Routing Routines
+ *
+ * Contains routines for isomorphic topology matching,
+ * routing determination, and routing initialization.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htGraph.h"
+#include "htFeatRouting.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATROUTING_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+typedef struct {
+  UINT8   **CurrentPosition;
+  BOOLEAN IsCustomList;
+} TOPOLOGY_CONTEXT;
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***          ISOMORPHISM BASED ROUTING TABLE GENERATION CODE            ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the Link on source Node which connects to target Node
+ *
+ * @param[in] SourceNode   The Node on which to find the Link
+ * @param[in] TargetNode   The Link will connect to this Node
+ * @param[in] State        Our global state
+ *
+ * @return    the Link to target
+ */
+UINT8
+STATIC
+FindLinkToNode (
+  IN       UINT8        SourceNode,
+  IN       UINT8        TargetNode,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT8 TargetLink;
+  UINT8 k;
+
+  // A node linked to itself is not a supported topology graph, this is probably an error in the
+  // topology data.  There is not going to be a portlist match for it.
+  ASSERT (SourceNode != TargetNode);
+  TargetLink = INVALID_LINK;
+  for (k = 0; k < State->TotalLinks*2; k += 2) {
+    if (((*State->PortList)[k].NodeID == SourceNode) && ((*State->PortList)[k + 1].NodeID == TargetNode)) {
+      TargetLink = (*State->PortList)[k].Link;
+      break;
+    } else if (((*State->PortList)[k + 1].NodeID == SourceNode) && ((*State->PortList)[k].NodeID == TargetNode)) {
+      TargetLink = (*State->PortList)[k + 1].Link;
+      break;
+    }
+  }
+  ASSERT (TargetLink != INVALID_LINK);
+
+  return TargetLink;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *      Is graphA isomorphic to graphB?
+ *
+ *  If this function returns true, then Perm will contain the permutation
+ *  required to transform graphB into graphA.
+ *  We also use the degree of each Node, that is the number of connections it has, to
+ *  speed up rejection of non-isomorphic graphs (if there is a Node in graphA with n
+ *  connections, there must be at least one unmatched in graphB with n connections).
+ *
+ * @param[in]     Node     the discovered Node which we are trying to match
+ *                      with a permutation the topology
+ * @param[in,out] State our global state, degree and adjacency matrix,
+ *                      output a permutation if successful
+ * @retval TRUE         the graphs are isomorphic
+ * @retval FALSE        the graphs are not isomorphic
+ *
+ */
+BOOLEAN
+STATIC
+IsIsomorphic (
+  IN       UINT8         Node,
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 j;
+  UINT8 k;
+  UINT8 Nodecnt;
+
+  // We have only been called if Nodecnt == pSelected->size !
+  Nodecnt = State->NodesDiscovered + 1;
+
+  if (Node != Nodecnt) {
+    // Keep building the permutation
+    for (j = 0; j < Nodecnt; j++) {
+      // Make sure the degree matches
+      if (State->Fabric->SysDegree[Node] != State->Fabric->DbDegree[j]) {
+        continue;
+      }
+
+      // Make sure that j hasn't been used yet (ought to use a "used"
+      // array instead, might be faster)
+      for (k = 0; k < Node; k++) {
+        if (State->Fabric->Perm[k] == j) {
+          break;
+        }
+      }
+      if (k != Node) {
+        continue;
+      }
+      State->Fabric->Perm[Node] = j;
+      if (IsIsomorphic (Node + 1, State)) {
+        return TRUE;
+      }
+    }
+    return FALSE;
+  } else {
+    // Test to see if the permutation is isomorphic
+    for (j = 0; j < Nodecnt; j++) {
+      for (k = 0; k < Nodecnt; k++) {
+        if (State->Fabric->SysMatrix[j][k] != State->Fabric->DbMatrix[State->Fabric->Perm[j]][State->Fabric->Perm[k]] ) {
+          return FALSE;
+        }
+      }
+    }
+    return TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Topology List iterator context to the Beginning and provide the first topology.
+ *
+ * Check the interface for a custom topology list.  If one is found, set context to the
+ * first item, and return that item. Otherwise return the first item in the built in list.
+ *
+ * @param[in,out] TopologyContextHandle  Initialize this context to beginning of lists.
+ * @param[out]     NextTopology           The next topology, NULL if end.
+ * @param[in]      State                  Access to interface, handles.
+ *
+ */
+VOID
+STATIC
+BeginTopologies (
+     OUT   TOPOLOGY_CONTEXT  *TopologyContextHandle,
+     OUT   UINT8             **NextTopology,
+  IN       STATE_DATA        *State
+  )
+{
+  if (State->HtBlock->Topolist != NULL) {
+    // Start with a custom list
+    TopologyContextHandle->CurrentPosition = State->HtBlock->Topolist;
+    TopologyContextHandle->IsCustomList = TRUE;
+  } else {
+    // Start with the built in list
+    GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
+    TopologyContextHandle->IsCustomList = FALSE;
+  }
+  *NextTopology = *TopologyContextHandle->CurrentPosition;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Iterate through available topologies.
+ *
+ * Increment to the next list item.  If we are doing a custom list, when we reach the end
+ * switch to the built in list.
+ *
+ * @param[in,out]  TopologyContextHandle  Maintain iterator's context from one call to the next
+ * @param[out]     NextTopology           The next topology, NULL if end.
+ *
+ */
+VOID
+STATIC
+GetNextTopology (
+  IN OUT   TOPOLOGY_CONTEXT  *TopologyContextHandle,
+     OUT   UINT8             **NextTopology
+  )
+{
+  // Not valid to continue calling this routine after reaching the end.
+  ASSERT (TopologyContextHandle->CurrentPosition != NULL);
+
+  if (TopologyContextHandle->IsCustomList) {
+    // We are iterating the custom list from the interface.
+    TopologyContextHandle->CurrentPosition++;
+    if (*TopologyContextHandle->CurrentPosition == NULL) {
+      // We are at the end of the custom list, switch to the built in list.
+      TopologyContextHandle->IsCustomList = FALSE;
+      GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
+    }
+  } else {
+    // We are iterating the built in list
+    TopologyContextHandle->CurrentPosition++;
+    // If we are at the end of the built in list, NextTopology == NULL is the AtEnd.
+  }
+  *NextTopology = *TopologyContextHandle->CurrentPosition;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ * @HtFeatMethod{::F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES}
+ *
+ * A supported topology description matches the discovered fabric if the Nodes can be
+ * matched in such a way that all the Nodes connected in one set are exactly the
+ * Nodes connected in the other (formally, that the graphs are isomorphic).  Which
+ * Links are used is not really important to matching.  If the graphs match, then
+ * there is a permutation of one that translates the Node positions and Linkages to
+ * the other.
+ *
+ * In order to make the isomorphism test efficient, we test for matched number of Nodes
+ * (a 4 Node fabric is not isomorphic to a 2 Node topology), and provide degrees of Nodes
+ * to the isomorphism test.
+ *
+ * The generic routing table solution for any topology is predetermined and represented
+ * as part of the topology.  The permutation we computed tells us how to interpret the
+ * routing onto the fabric we discovered.  We do this working backward from the last
+ * Node discovered to the BSP, writing the routing tables as we go.
+ *
+ * @param[in,out]    State    the discovered fabric, degree matrix, permutation
+ *
+ */
+VOID
+LookupComputeAndLoadRoutingTables (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  TOPOLOGY_CONTEXT   TopologyContextHandle;
+  UINT8 *Selected;
+  UINT8 Size;
+  UINT8 PairCounter;
+  UINT8 ReqTargetLink;
+  UINT8 RspTargetLink;
+  UINT8 ReqTargetNode;
+  UINT8 RspTargetNode;
+  UINT8 AbstractBcTargetNodes;
+  UINT32 BcTargetLinks;
+  UINT8 NodeCounter;
+  UINT8 NodeBeingRouted;
+  UINT8 NodeRoutedTo;
+  UINT8 BroadcastSourceNode;
+
+  Size = State->NodesDiscovered + 1;
+  BeginTopologies (&TopologyContextHandle, &Selected, State);
+  while (Selected != NULL) {
+    if (GraphHowManyNodes (Selected) == Size) {
+      // Build Degree vector and Adjacency Matrix for this entry
+      for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
+        State->Fabric->DbDegree[NodeCounter] = 0;
+        for (PairCounter = 0; PairCounter < Size; PairCounter++) {
+          if (GraphIsAdjacent (Selected, NodeCounter, PairCounter)) {
+            State->Fabric->DbMatrix[NodeCounter][PairCounter] = TRUE;
+            State->Fabric->DbDegree[NodeCounter]++;
+          } else {
+            State->Fabric->DbMatrix[NodeCounter][PairCounter] = FALSE;
+          }
+        }
+      }
+
+      if (IsIsomorphic (0, State)) {
+        break;  // A matching topology was found
+      }
+    }
+    GetNextTopology (&TopologyContextHandle, &Selected);
+  }
+
+  if (Selected != NULL) {
+    // Compute the reverse Permutation
+    for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
+      State->Fabric->ReversePerm[State->Fabric->Perm[NodeCounter]] = NodeCounter;
+    }
+
+    // Start with the last discovered Node, and move towards the BSP
+    for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
+      NodeBeingRouted = ((Size - 1) - NodeCounter);
+      for (NodeRoutedTo = 0; NodeRoutedTo < Size; NodeRoutedTo++) {
+        BcTargetLinks = 0;
+        AbstractBcTargetNodes = GraphGetBc (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
+
+        for (BroadcastSourceNode = 0; BroadcastSourceNode < MAX_NODES; BroadcastSourceNode++) {
+          if ((AbstractBcTargetNodes & ((UINT32)1 << BroadcastSourceNode)) != 0) {
+            // Accepting broadcast from yourself is handled in Nb, so in the topology graph it is an error.
+            ASSERT (NodeBeingRouted != State->Fabric->ReversePerm[BroadcastSourceNode]);
+            BcTargetLinks |= (UINT32)1 << FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[BroadcastSourceNode], State);
+          }
+        }
+
+        if (NodeBeingRouted == NodeRoutedTo) {
+          ReqTargetLink = ROUTE_TO_SELF;
+          RspTargetLink = ROUTE_TO_SELF;
+        } else {
+          ReqTargetNode = GraphGetReq (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
+          ReqTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[ReqTargetNode], State);
+
+          RspTargetNode = GraphGetRsp (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
+          RspTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[RspTargetNode], State);
+        }
+        State->Nb->WriteFullRoutingTable (NodeBeingRouted, NodeRoutedTo, ReqTargetLink, RspTargetLink, BcTargetLinks, State->Nb);
+      }
+      //  Clean up discovery 'footprint' that otherwise remains in the routing table.  It didn't hurt
+      // anything, but might cause confusion during debug and validation.  Do this by setting the
+      // route back to all self routes. Since it's the Node that would be one more than actually installed,
+      // this only applies if less than MaxNodes were found.
+      //
+      if (Size < MAX_NODES) {
+        State->Nb->WriteFullRoutingTable (NodeBeingRouted, Size, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
+      }
+    }
+  } else {
+    //
+    // No Matching Topology was found
+    // Error Strategy:
+    // Auto recovery doesn't seem likely, Force boot as 1P.
+    // For reporting, logging, provide number of Nodes
+    // If not implemented or returns, boot as BSP uniprocessor.
+    //
+    // This can be caused by not supplying an additional topology list, if your board is not one of the built-in topologies.
+    //
+    NotifyErrorCohNoTopology (State->NodesDiscovered, State);
+    IDS_ERROR_TRAP;
+    // Force 1P
+    State->NodesDiscovered = 0;
+    State->TotalLinks = 0;
+    State->Nb->EnableRoutingTables (0, State->Nb);
+    State->HtInterface->CleanMapsAfterError (State);
+  }
+  // Save the topology pointer, or NULL, for other features
+  State->Fabric->MatchedTopology = Selected;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ * @HtFeatMethod{::F_MAKE_HOP_COUNT_TABLE}
+ *
+ * For SLIT, create a node x node matrix with the number of hops.  We can do this
+ * using the topology and the permutation, counting the nodes visited in the routes between
+ * nodes.
+ *
+ * @param[in,out]   State    access topology, permutation, update hop table
+ *
+ */
+VOID
+MakeHopCountTable (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 Origin;
+  UINT8 Target;
+  UINT8 Current;
+  UINT8 Hops;
+  UINT8 Size;
+
+  ASSERT (State->Fabric != NULL);
+  if (State->HopCountTable != NULL) {
+    if (State->Fabric->MatchedTopology != NULL) {
+      Size = GraphHowManyNodes (State->Fabric->MatchedTopology);
+      State->HopCountTable->Size = Size;
+      //
+      // For each node, targeting each node, follow the request path through the database graph,
+      // counting the number of edges.
+      //
+      for (Origin = 0; Origin < Size; Origin++) {
+        for (Target = 0; Target < Size; Target++) {
+          // If both nodes are the same the answer will be zero
+          Hops = 0;
+          // Current starts as the database node corresponding to system node Origin.
+          Current = State->Fabric->Perm[Origin];
+          // Stop if Current is the database node corresponding to system node Target
+          while (Current != State->Fabric->Perm[Target]) {
+            // This is a hop, so count it. Move Current to the next intermediate database node.
+            Hops++;
+            Current = GraphGetReq (State->Fabric->MatchedTopology, Current, State->Fabric->Perm[Target]);
+          }
+          // Put the hop count in the table.
+          State->HopCountTable->Hops[ ((Origin * Size) + Target)] = Hops;
+        }
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
new file mode 100755
index 0000000000..c34dbd404e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatRouting.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * Routing Feature Interface.
+ *
+ * Interfaces to routing and isomorphism routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_ROUTING_H_
+#define _HT_FEAT_ROUTING_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ */
+VOID
+LookupComputeAndLoadRoutingTables (
+  IN OUT   STATE_DATA    *State
+  );
+
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ */
+VOID
+MakeHopCountTable (
+  IN OUT   STATE_DATA    *State
+  );
+
+#endif  /* _HT_FEAT_ROUTING_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSets.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSets.c
new file mode 100755
index 0000000000..d2b59acd47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSets.c
@@ -0,0 +1,110 @@
+/**
+ * @file
+ *
+ * HyperTransport feature sets initializers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "CommonReturns.h"
+#include "htFeatDynamicDiscovery.h"
+#include "htFeatRouting.h"
+#include "htFeatNoncoherent.h"
+#include "htFeatOptimization.h"
+#include "htFeatGanging.h"
+#include "htFeatSublinks.h"
+#include "htFeatTrafficDistribution.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATSETS_FILECODE
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/**
+ * Initializer for the default feature set implementation,
+ * full features.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesDefault =
+{
+  CoherentDiscovery,
+  LookupComputeAndLoadRoutingTables,
+  MakeHopCountTable,
+  ProcessLink,
+  GatherLinkData,
+  SelectOptimalWidthAndFrequency,
+  RegangLinks,
+  SubLinkRatioFixup,
+  IsCoherentRetryFixup,
+  SetLinkData,
+  TrafficDistribution,
+  SetHtControlRegisterBits,
+  ConvertWidthToBits
+};
+
+/**
+ * Initializer for the non-coherent only build option.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesNonCoherentOnly =
+{
+  (PF_COHERENT_DISCOVERY)CommonVoid,
+  (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
+  (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
+  ProcessLink,
+  GatherLinkData,
+  SelectOptimalWidthAndFrequency,
+  (PF_REGANG_LINKS)CommonVoid,
+  (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
+  (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
+  SetLinkData,
+  (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
+  SetHtControlRegisterBits,
+  ConvertWidthToBits
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
new file mode 100755
index 0000000000..5574772a7b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.c
@@ -0,0 +1,228 @@
+/**
+ * @file
+ *
+ * SubLink management Routines.
+ *
+ * Contains routines for subLink frequency ratios.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "amdlib.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htFeatSublinks.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+typedef struct {
+  UINT8 HiFreq;
+  UINT8 LoFreq;
+} VALID_RATIO_ITEM;
+
+STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
+{
+  {HT_FREQUENCY_3200M, HT_FREQUENCY_1600M},   // 3200MHz / 1600MHz 2:1
+  {HT_FREQUENCY_3200M, HT_FREQUENCY_800M},    // 3200MHz / 800MHz  4:1
+  {HT_FREQUENCY_3200M, HT_FREQUENCY_400M},    // 3200MHz / 400MHz  8:1
+  {HT_FREQUENCY_2800M, HT_FREQUENCY_1400M},   // 2800MHz / 1400MHz 2:1
+  {HT_FREQUENCY_2400M, HT_FREQUENCY_1200M},   // 2400MHz / 1200MHz 2:1
+  {HT_FREQUENCY_2400M, HT_FREQUENCY_600M},    // 2400MHz /  600MHz 4:1
+  {HT_FREQUENCY_2400M, HT_FREQUENCY_400M},    // 2400MHz /  400MHz 6:1
+  {HT_FREQUENCY_2000M, HT_FREQUENCY_1000M},   // 2000MHz / 1000MHz 2:1
+  {HT_FREQUENCY_1600M, HT_FREQUENCY_800M},    // 1600MHz /  800MHz 2:1
+  {HT_FREQUENCY_1600M, HT_FREQUENCY_400M},    // 1600MHz /  400MHz 4:1
+  {HT_FREQUENCY_1600M, HT_FREQUENCY_200M},    // 1600MHz /  200Mhz 8:1
+  {HT_FREQUENCY_1200M, HT_FREQUENCY_600M},    // 1200MHz /  600MHz 2:1
+  {HT_FREQUENCY_1200M, HT_FREQUENCY_200M},    // 1200MHz /  200MHz 6:1
+  {HT_FREQUENCY_800M,  HT_FREQUENCY_400M},    // 800MHz /  400MHz 2:1
+  {HT_FREQUENCY_800M,  HT_FREQUENCY_200M},    // 800MHz /  200MHz 4:1
+  {HT_FREQUENCY_400M,  HT_FREQUENCY_200M}     // 400MHz /  200MHz 2:1
+};
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ * @HtFeatMethod{::F_SUBLINK_RATIO_FIXUP}
+ *
+ * Make the adjustment to the port list data so that the frequencies
+ * are at a valid ratio, reducing frequency as needed to achieve
+ * this. (All Links support the minimum 200 MHz frequency.)  Repeat
+ * the above until no adjustments are needed.
+ * @note no hardware state changes in this routine.
+ *
+ * @param[in,out]     State     Link state and port list
+ *
+ */
+VOID
+SubLinkRatioFixup (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 ValidRatioItem;
+  BOOLEAN Changes;
+  BOOLEAN Downgrade;
+  UINT8 HiIndex;
+  UINT8 HiFreq;
+  UINT8 LoFreq;
+
+  UINT32 Temp;
+
+  do {
+    Changes = FALSE;
+    for (i = 0; i < State->TotalLinks*2; i++) {
+      // Must be a CPU Link
+      if ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) {
+        continue;
+      }
+      // Only look for subLink1's
+      if ((*State->PortList)[i].Link < 4) {
+        continue;
+      }
+
+      for (j = 0; j < State->TotalLinks*2; j++) {
+        // Step 1. Find the matching subLink0
+        if ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) {
+          continue;
+        }
+        if ((*State->PortList)[j].NodeID != (*State->PortList)[i].NodeID) {
+          continue;
+        }
+        if ((*State->PortList)[j].Link != ((*State->PortList)[i].Link & 0x03)) {
+          continue;
+        }
+
+        // Step 2. Check for an illegal frequency ratio
+        if ((*State->PortList)[i].SelFrequency >= (*State->PortList)[j].SelFrequency) {
+          HiIndex = i;
+          HiFreq = (*State->PortList)[i].SelFrequency;
+          LoFreq = (*State->PortList)[j].SelFrequency;
+        } else {
+          HiIndex = j;
+          HiFreq = (*State->PortList)[j].SelFrequency;
+          LoFreq = (*State->PortList)[i].SelFrequency;
+        }
+
+        // The frequencies are 1:1, no need to do anything
+        if (HiFreq == LoFreq) {
+          break;
+        }
+
+        Downgrade = TRUE;
+
+        for (ValidRatioItem = 0; ValidRatioItem < (sizeof (ValidRatioList) / sizeof (VALID_RATIO_ITEM)); ValidRatioItem++) {
+          if ((HiFreq == ValidRatioList[ValidRatioItem].HiFreq) &&
+              (LoFreq == ValidRatioList[ValidRatioItem].LoFreq)) {
+            Downgrade = FALSE;
+            break;
+          }
+        }
+
+        // Step 3. Downgrade the higher of the two frequencies, and set Changes to FALSE
+        if (Downgrade) {
+          // Although the problem was with the port specified by hiIndex, we need to
+          // Downgrade both ends of the Link.
+          HiIndex = HiIndex & 0xFE; // Select the 'upstream' (i.e. even) port
+
+          Temp = (*State->PortList)[HiIndex].CompositeFrequencyCap;
+
+          // Remove HiFreq from the list of valid frequencies
+          Temp = Temp & ~((UINT32)1 << HiFreq);
+          ASSERT (Temp != 0);
+          (*State->PortList)[HiIndex].CompositeFrequencyCap = (UINT32)Temp;
+          (*State->PortList)[HiIndex + 1].CompositeFrequencyCap = (UINT32)Temp;
+
+          HiFreq = LibAmdBitScanReverse (Temp);
+
+          (*State->PortList)[HiIndex].SelFrequency = HiFreq;
+          (*State->PortList)[HiIndex + 1].SelFrequency = HiFreq;
+
+          Changes = TRUE;
+        }
+      }
+    }
+  } while (Changes); // Repeat until a valid configuration is reached
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
new file mode 100755
index 0000000000..7a089001ae
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatSublinks.h
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * SubLink Interface.
+ *
+ * Contains interface to subLink management feature, for unganged subLinks.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_FEAT_SUBLINKS_H_
+#define _HT_FEAT_SUBLINKS_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ */
+VOID
+SubLinkRatioFixup (
+  IN OUT   STATE_DATA    *State
+  );
+
+#endif  /* _HT_FEAT_SUBLINKS_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
new file mode 100755
index 0000000000..877c578ba7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.c
@@ -0,0 +1,265 @@
+/**
+ * @file
+ *
+ * Traffic Distribution Routines.
+ *
+ * Contains routines for traffic distribution
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htNotify.h"
+#include "htFeatTrafficDistribution.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ * @HtFeatMethod{::F_TRAFFIC_DISTRIBUTION}
+ *
+ * If there are redundant links between any nodes, traffic distribution allows the
+ * redundant links to be used to improve performance.
+ *
+ * There are two types of traffic distribution. Their use is mutually exclusive, both
+ * can not be used at once.
+ *
+ * Coherent Traffic Distribution is for systems of exactly two nodes only.  All links must
+ * be symmetrical (the same width).  As many links as are connected can be distributed over.
+ *
+ * Link Pair Traffic Distribution works with redundant pairs of links between any two nodes,
+ * it does not matter how many nodes are in the system or how many have a redundant link pair.
+ * A node can have redundant link pairs with more than one other node.
+ * The link pair can be asymmetric, the largest link must be used as the master.  However,
+ * between any pair of nodes there is only one pair of redundant links, and there is a limit
+ * to the total number of pairs each node can have.  So not all links will necessarily be
+ * made usable.
+ *
+ * @param[in]   State   port list data
+ */
+VOID
+TrafficDistribution (
+  IN       STATE_DATA *State
+  )
+{
+  UINT32 Links01;
+  UINT32 Links10;
+  UINT8  LinkCount;
+  UINT8  i;
+  UINT8  LastLink;
+  BOOLEAN IsAsymmetric;
+  UINT8 RedundantLinkCount[MAX_NODES][MAX_NODES];
+  UINT8 MasterLinkPort[MAX_NODES][MAX_NODES];
+  UINT8 AlternateLinkPort[MAX_NODES][MAX_NODES];
+  UINT8 NodeA;
+  UINT8 NodeB;
+  UINT8 PairCount;
+
+  LastLink = 0xFF;
+  IsAsymmetric = FALSE;
+
+  // Traffic Distribution is only used when there are exactly two Nodes in the system
+  // and when all the links are symmetric, same width.
+  if ((State->NodesDiscovered + 1) == 2) {
+    Links01 = 0;
+    Links10 = 0;
+    LinkCount = 0;
+    for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+      if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
+          ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+        if ((LastLink != 0xFF) &&
+            ((*State->PortList)[i].SelWidthOut != (*State->PortList)[LastLink].SelWidthOut) &&
+            ((*State->PortList)[i + 1].SelWidthOut != (*State->PortList)[LastLink + 1].SelWidthOut)) {
+          IsAsymmetric = TRUE;
+          break;
+        }
+        Links01 |= (UINT32)1 << (*State->PortList)[i].Link;
+        Links10 |= (UINT32)1 << (*State->PortList)[i + 1].Link;
+        LinkCount++;
+        LastLink = i;
+      }
+    }
+    ASSERT (LinkCount != 0);
+    //  Don't setup Traffic Distribution if only one Link is being used or there were asymmetric widths
+    if ((LinkCount != 1) && !IsAsymmetric) {
+      State->Nb->WriteTrafficDistribution (Links01, Links10, State->Nb);
+      // If we did Traffic Distribution, we must not do Link Pair, so get out of here.
+      return;
+    }
+  }
+  // Either there are more than two nodes, Asymmetric links, or no redundant links.
+  // See if we can use Link Pair Traffic Distribution
+  LibAmdMemFill (&RedundantLinkCount, 0, (MAX_NODES * MAX_NODES), State->ConfigHandle);
+  for (i = 0; i < (State->TotalLinks * 2); i += 2) {
+    if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
+        ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
+      NodeA = (*State->PortList)[i].NodeID;
+      NodeB = (*State->PortList)[i + 1].NodeID;
+      if (RedundantLinkCount[NodeA][NodeB] == 0) {
+        // This is the first link connecting two nodes
+        ASSERT (RedundantLinkCount[NodeB][NodeA] == 0);
+        MasterLinkPort[NodeA][NodeB] = i;
+        MasterLinkPort[NodeB][NodeA] = i + 1;
+      } else {
+        // This is a redundant link.  If it is larger than the current master link,
+        // make it the new master link.
+        //
+        if (((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
+            ((*State->PortList)[MasterLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
+          // Make the old master link the alternate, we don't need to check, it is bigger.
+          AlternateLinkPort[NodeA][NodeB] = MasterLinkPort[NodeA][NodeB];
+          AlternateLinkPort[NodeB][NodeA] = MasterLinkPort[NodeB][NodeA];
+          MasterLinkPort[NodeA][NodeB] = i;
+          MasterLinkPort[NodeB][NodeA] = i + 1;
+        } else {
+          // Since the new link isn't bigger than the Master, check if it is bigger than the alternate,
+          // if we have an alternate. If we don't have an alternate yet, make this link the alternate.
+          if (RedundantLinkCount[NodeA][NodeB] == 1) {
+            AlternateLinkPort[NodeA][NodeB] = i;
+            AlternateLinkPort[NodeB][NodeA] = i + 1;
+          } else {
+            if (((*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
+                ((*State->PortList)[AlternateLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
+              // Warning: the alternate link is an unusable redundant link
+              // Then make the new link the alternate link.
+              NotifyWarningOptUnusedLinks (
+                NodeA,
+                (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
+                NodeB,
+                (*State->PortList)[AlternateLinkPort[NodeB][NodeA]].Link,
+                State
+                );
+              ASSERT (RedundantLinkCount[NodeB][NodeA] > 1);
+              AlternateLinkPort[NodeA][NodeB] = i;
+              AlternateLinkPort[NodeB][NodeA] = i + 1;
+            } else {
+              // Warning the current link is an unusable redundant link
+              NotifyWarningOptUnusedLinks (NodeA, (*State->PortList)[i].Link, NodeB, (*State->PortList)[i].Link, State);
+            }
+          }
+        }
+      }
+      RedundantLinkCount[NodeA][NodeB]++;
+      RedundantLinkCount[NodeB][NodeA]++;
+    }
+  }
+  // If we found any, now apply up to 4 per node
+  for (NodeA = 0; NodeA < MAX_NODES; NodeA++) {
+    PairCount = 0;
+    for (NodeB = 0; NodeB < MAX_NODES; NodeB++) {
+      if (RedundantLinkCount[NodeA][NodeB] > 1) {
+        // Then there is a pair of links (at least, but we only care about the pair not the extras)
+        if (PairCount < MAX_LINK_PAIRS) {
+          // Program it
+          if ((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut
+              != (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut) {
+            IsAsymmetric = TRUE;
+          } else {
+            IsAsymmetric = FALSE;
+          }
+          State->Nb->WriteLinkPairDistribution (
+            NodeA,
+            NodeB,
+            PairCount,
+            IsAsymmetric,
+            (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
+            (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
+            State->Nb
+            );
+          PairCount++;
+        } else {
+          // Warning: More link pairs than can be distributed
+          NotifyWarningOptLinkPairExceed (
+            NodeA, NodeB,
+            (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
+            (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
+            State);
+          // Disable the link pair from the other node, the analysis loop made sure there
+          // can only be a single link pair between a pair of nodes.
+          RedundantLinkCount[NodeB][NodeA] = 1;
+        }
+      }
+    }
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
new file mode 100755
index 0000000000..64beb89bea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htFeatTrafficDistribution.h
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * Traffic Distribution Interface.
+ *
+ * Interface to traffic distribution feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
+#define _H_TFEAT_TRAFFIC_DISTRIBUTION_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ */
+VOID
+TrafficDistribution (
+  IN       STATE_DATA *State
+  );
+
+#endif  /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
+
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
new file mode 100755
index 0000000000..72d9dfe641
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/Features/htIds.c
@@ -0,0 +1,148 @@
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Implementation.
+ *
+ * Contains AMD AGESA Integrated Debug HT related support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ *
+ ***************************************************************************/
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
+
+
+/*-------------------------------------------------------------------------------------*/
+/**
+ * Apply an IDS port override to the desired HT link.
+ *
+ * The IDS port override allows absolute control of a link's frequency and width, such as
+ * would be used for board characterization and test.  The IDS backend code is responsible
+ * for handling the NV items and building them into a port override list.  Here we search
+ * that list for any overrides which apply, and update the data used by the HT feature code.
+ *
+ * @param[in]      IsSourcePort         Since we handle both ports on a match, only do that if TRUE.
+ * @param[in,out]  Port0                The PORTLIST item for the first endpoint of a link.
+ * @param[in,out]  Port1                The PORTLIST item for the second endpoint of a link.
+ * @param[in,out]  PortOverrideList     IN: A pointer to the port override list or NULL,
+ *                                      OUT: A pointer to the port override list.
+ * @param[in]      State                access to ht interface and nb support methods.
+ *
+ */
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  )
+{
+  LOCATE_HEAP_PTR LocHeapParams;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+  HTIDS_PORT_OVERRIDE_LIST   p;
+
+  if (IsSourcePort) {
+    ASSERT (PortOverrideList != NULL);
+    // The caller can cache the override list by providing the pointer (to the heap buffer).
+    // If the pointer to the port override list is null, then check if it is on the heap,
+    // and update the caller's pointer so it is cached.
+    // If the buffer is not in heap, call the IDS backend to get the NV data (which is likely also
+    // in heap).
+    if (*PortOverrideList == NULL) {
+      // locate the table in heap
+      LocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
+      if (HeapLocateBuffer (&LocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+        *PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST)LocHeapParams.BufferPtr;
+      } else {
+        // Ask IDS backend code for the list
+        IDS_OPTION_HOOK (IDS_HT_CONTROL, PortOverrideList, State->ConfigHandle);
+      }
+    }
+    ASSERT (*PortOverrideList != NULL);
+
+    // Search the port override list to see if there is an override that applies to this link.
+    // The match criteria are if either endpoint of the current port list item matches
+    // port override.
+    p = *PortOverrideList;
+    SocketA = State->HtInterface->GetSocketFromMap (Port0->NodeID, State);
+    PackageLinkA = State->Nb->GetPackageLink (Port0->NodeID, Port0->Link, State->Nb);
+    SocketB = State->HtInterface->GetSocketFromMap (Port1->NodeID, State);
+    PackageLinkB = State->Nb->GetPackageLink (Port1->NodeID, Port1->Link, State->Nb);
+
+    while ((p != NULL) && (p->Socket != HT_LIST_TERMINAL)) {
+      if ((((p->Socket == SocketA) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLinkA) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA))))) ||
+          (((p->Socket == SocketB) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLinkB) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB)))))) {
+        // Found a match, update width and frequency of both endpoints.
+        if (p->WidthIn != HT_LIST_TERMINAL) {
+          Port0->SelWidthIn = p->WidthIn;
+          Port1->SelWidthOut = p->WidthIn;
+        }
+        if (p->WidthOut != HT_LIST_TERMINAL) {
+          Port0->SelWidthOut = p->WidthOut;
+          Port1->SelWidthIn = p->WidthOut;
+        }
+        if (p->Frequency != HT_LIST_TERMINAL) {
+          Port0->SelFrequency = p->Frequency;
+          Port1->SelFrequency = p->Frequency;
+        }
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
new file mode 100755
index 0000000000..18cee2db47
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.c
@@ -0,0 +1,488 @@
+/**
+ * @file
+ *
+ * Coherent Feature Northbridge routines.
+ *
+ * Provide access to hardware for routing, coherent discovery.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbCoherent.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Establish a Temporary route from one Node to another.
+ *
+ * @HtNbMethod{::F_WRITE_ROUTING_TABLE}
+ *
+ * This routine will modify the routing tables on the
+ * SourceNode to cause it to route both request and response traffic to the
+ * targetNode through the specified Link.
+ *
+ * @note: This routine is to be used for early discovery and initialization.  The
+ * final routing tables must be loaded some other way because this
+ * routine does not address the issue of probes, or independent request
+ * response paths.
+ *
+ * @param[in]     Node     the Node that will have it's routing tables modified.
+ * @param[in]     Target   For routing to Node target
+ * @param[in]     Link     Link from Node to target
+ * @param[in]     Nb       this northbridge
+ */
+VOID
+WriteRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES) && (Link < Nb->MaxLinks));
+  Temp = (Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (Link + 1);
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_ROUTE0_0X40 + (Target * 4));
+  LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ * @HtNbMethod{::F_WRITE_NODEID}
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     NodeID the new value for NodeID
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+WriteNodeID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = NodeID;
+  ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_NODE_ID_0X60);
+  LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read the Default Link
+ *
+ * @HtNbMethod{::F_READ_DEFAULT_LINK}
+ *
+ * Read the DefLnk (the source Link of the current packet) from Node. Since this code
+ * is running on the BSP, this should be the Link pointing back towards the BSP.
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     Nb     this northbridge
+ *
+ * @return The HyperTransport Link where the request to
+ *         read the default Link came from.
+ */
+UINT8
+ReadDefaultLink (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 DefaultLink;
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  DefaultLink = 0;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_INIT_CONTROL_0X6C);
+
+  ASSERT ((Node < MAX_NODES));
+  LibAmdPciReadBits (Reg, 3, 2, &DefaultLink, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
+  DefaultLink |= (Temp << 2);
+  return (UINT8)DefaultLink;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Turns routing tables on for a given Node
+ *
+ * @HtNbMethod{::F_ENABLE_ROUTING_TABLES}
+ *
+ * @param[in] Node the Node that will have it's routing tables enabled
+ * @param[in] Nb   this northbridge
+ */
+VOID
+EnableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = 0;
+  ASSERT ((Node < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_INIT_CONTROL_0X6C);
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Turns routing tables off for a given Node
+ *
+ * @HtNbMethod{::F_DISABLE_ROUTING_TABLES}
+ *
+ * @param[in] Node the Node that will have it's routing tables disabled
+ * @param[in] Nb   this northbridge
+ */
+VOID
+DisableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = 1;
+  ASSERT ((Node < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_INIT_CONTROL_0X6C);
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+ * @HtNbMethod{::F_VERIFY_LINK_IS_COHERENT}
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link has the following status
+ *                        -  LinkCon=1,           Link is connected
+ *                        -  InitComplete=1,      Link initialization is complete
+ *                        -  NC=0,                Link is coherent
+ *                        -  UniP-cLDT=0,         Link is not Uniprocessor cLDT
+ *                        -  LinkConPend=0        Link connection is not pending
+ *  @retval       FALSE   The Link has some other status
+*/
+BOOLEAN
+VerifyLinkIsCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 LinkType;
+  PCI_ADDR LinkBase;
+
+  ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
+
+  LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
+
+  //  FN0_98/A4/C4 = LDT Type Register
+  LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
+  LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
+
+  //  Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0
+  return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) ==  HTHOST_TYPE_COHERENT);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ * @HtNbMethod{::F_READ_TOKEN}
+ *
+ * Use the CPU core count as a scratch pad.
+ *
+ * @note The location used to store the token is arbitrary.  The only requirement is
+ * that the location warm resets to zero, and that using it will have no ill-effects
+ * during HyperTransport initialization.
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ *
+ * @return        the Token read from the Node
+ */
+UINT8
+ReadToken (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  ASSERT ((Node < MAX_NODES));
+  // Use CpuCnt as a scratch register
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_NODE_ID_0X60);
+  LibAmdPciReadBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
+
+  return (UINT8)Temp;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write the token stored in the scratchpad register
+ *
+ * @HtNbMethod{::F_WRITE_TOKEN}
+ *
+ * Use the CPU core count as a scratch pad.
+ *
+ * @note The location used to store the token is arbitrary.  The only requirement is
+ * that the location warm resets to zero, and that using it will have no ill-effects
+ * during HyperTransport initialization.
+ *
+ * @param[in]     Node  the Node that marked with token
+ * @param[in]     Value the token Value
+ * @param[in]     Nb    this northbridge
+ */
+VOID
+WriteToken (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+  Temp = Value;
+  ASSERT ((Node < MAX_NODES));
+  // Use CpuCnt as a scratch register
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_NODE_ID_0X60);
+  LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Full Routing Table Register initialization
+ *
+ * @HtNbMethod{::F_WRITE_FULL_ROUTING_TABLE}
+ *
+ * Write the routing table entry for Node to target, using the request Link, response
+ * Link, and broadcast Links provided.
+ *
+ * @param[in]     Node            the Node that will be examined
+ * @param[in]     Target          the Target Node for these routes
+ * @param[in]     ReqLink         the Link for requests to Target
+ * @param[in]     RspLink         the Link for responses to Target
+ * @param[in]     BroadcastLinks  the broadcast Links
+ * @param[in]     Nb              this northbridge
+ */
+VOID
+WriteFullRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Value;
+
+  Value = 0;
+  ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES));
+  if (ReqLink == ROUTE_TO_SELF) {
+    Value |= Nb->SelfRouteRequestMask;
+  } else {
+    Value |= Nb->SelfRouteRequestMask << (ReqLink + 1);
+  }
+
+  if (RspLink == ROUTE_TO_SELF) {
+    Value |= Nb->SelfRouteResponseMask;
+  } else {
+    Value |= Nb->SelfRouteResponseMask << (RspLink + 1);
+  }
+
+  // Allow us to accept a Broadcast ourselves, then set broadcasts for routes
+  Value |= (UINT32)1 << Nb->BroadcastSelfBit;
+  Value |= (UINT32)BroadcastLinks << (Nb->BroadcastSelfBit + 1);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_ROUTE0_0X40 + (Target * 4));
+  LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ * @HtNbMethod{::F_IS_ILLEGAL_TYPE_MIX}.
+ *
+ * Currently, that means the family, extended family of the new Node are the
+ * same as the BSP's.
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @retval   TRUE    the new node is not compatible
+ * @retval   FALSE   the new node is compatible
+ */
+BOOLEAN
+IsIllegalTypeMix (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbMethod{::F_HANDLE_SPECIAL_NODE_CASE}.
+ *
+ * Currently, this routine is implemented for all coherent HT families to check
+ * vendor ID of coherent Node. If the vendor ID is 0x1022 then return FALSE,
+ * or return TRUE.
+ *
+ * @param[in] Node  The Node which need to be checked.
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This node received special handling.
+ * @retval    FALSE This node was not handled specially, handle it normally.
+ *
+ */
+BOOLEAN
+HandleSpecialNodeCase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  BOOLEAN Result;
+  PCI_ADDR Reg;
+  UINT32 VendorID;
+
+  Result = TRUE;
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 0,
+                                 0);
+
+  LibAmdPciReadBits (Reg, 15, 0, &VendorID, Nb->ConfigHandle);
+  if (VendorID == 0x1022) {
+    Result = FALSE;
+  }
+
+  return Result;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
new file mode 100755
index 0000000000..43053a8924
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbCoherent.h
@@ -0,0 +1,177 @@
+/**
+ * @file
+ *
+ * Coherent Feature Northbridge common routines.
+ *
+ * Provide access to hardware for routing, coherent discovery.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE GENERIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+/**
+ * Establish a Temporary route from one Node to another.
+ *
+ */
+VOID
+WriteRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ */
+VOID
+WriteNodeID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Read the Default Link
+ *
+ */
+UINT8
+ReadDefaultLink (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Turns routing tables on for a given Node
+ *
+ */
+VOID
+EnableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Turns routing tables off for a given Node
+ *
+ */
+VOID
+DisableRoutingTables (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+*/
+BOOLEAN
+VerifyLinkIsCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ */
+UINT8
+ReadToken (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Write the token stored in the scratchpad register
+ *
+ */
+VOID
+WriteToken (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Full Routing Table Register initialization
+ *
+ */
+VOID
+WriteFullRoutingTable (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ */
+BOOLEAN
+IsIllegalTypeMix (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ */
+BOOLEAN
+HandleSpecialNodeCase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
new file mode 100755
index 0000000000..ba976458e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.c
@@ -0,0 +1,138 @@
+/**
+ * @file
+ *
+ *  Northbridge generic non-coherent support routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbNonCoherent.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                    Northbridge access routines                      ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the Link to the Southbridge
+ *
+ * @HtNbMethod{::F_READ_SB_LINK}
+ *
+ * @param[in] Nb this northbridge
+ *
+ * @return the Link to the southbridge
+ */
+UINT8
+ReadSouthbridgeLink (
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
+                                 MakePciBusFromNode (0),
+                                 MakePciDeviceFromNode (0),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_UNIT_ID_0X64);
+  LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
+  return (UINT8)Temp;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ * @HtNbMethod{::F_VERIFY_LINK_IS_NON_COHERENT}
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link has the following status
+ *                            - LinkCon=1,        Link is connected
+ *                            - InitComplete=1,   Link initialization is complete
+ *                            - NC=1,             Link is noncoherent
+ *                            - UniP-cLDT=0,      Link is not Uniprocessor cLDT
+ *                            - LinkConPend=0     Link connection is not pending
+ *  @retval       FALSE   The Link has some other status
+ */
+BOOLEAN
+VerifyLinkIsNonCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 LinkType;
+  PCI_ADDR LinkBase;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
+  LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
+
+  // FN0_98/A4/C4 = LDT Type Register
+  LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
+
+  // Verify LinkCon = 1, InitComplete = 1, NC = 1, UniP-cLDT = 0, LinkConPend = 0
+  return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) ==  HTHOST_TYPE_NONCOHERENT);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h
new file mode 100755
index 0000000000..3b161b61af
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbNonCoherent.h
@@ -0,0 +1,61 @@
+/**
+ * @file
+ *
+ *  Northbridge generic non-coherent support routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return the Link to the Southbridge
+ */
+UINT8
+ReadSouthbridgeLink (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ */
+BOOLEAN
+VerifyLinkIsNonCoherent (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
new file mode 100755
index 0000000000..344aea7574
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.c
@@ -0,0 +1,252 @@
+/**
+ * @file
+ *
+ * Link optimization support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "IdsHt.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbOptimization.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtNbMethod{::F_GATHER_LINK_FEATURES}
+ *
+ * For a specific discovered CPU Link, populate the port list with the frequency
+ * capabilities.  Support for other link oriented capabilities, currently:
+ * - Unit ID Clumping. Set to disabled. This doesn't mean the CPU doesn't support clumping,
+ *   it just means:
+ *   - The CPU doesn't clump its host unit ids, and
+ *   - We don't have to check as carefully in SetLinkData whether the port is an IO host link.
+ *
+ * @param[in,out] ThisPort       The PortList structure entry for this link's port
+ * @param[in]     Interface      Access to non-HT support functions.
+ * @param[in]     Nb             this northbridge
+ */
+VOID
+GatherLinkFeatures (
+  IN OUT   PORT_DESCRIPTOR  *ThisPort,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Frequency;
+  UINT32 ExtendedFrequency;
+
+  Reg = ThisPort->Pointer;
+  Reg.Address.Register += HTHOST_FREQ_REV_REG;
+  LibAmdPciReadBits (Reg, 30, 16, &Frequency, Nb->ConfigHandle);
+  Reg = ThisPort->Pointer;
+  Reg.Address.Register += HTHOST_FREQ_EXTENSION;
+  LibAmdPciReadBits (Reg, 15, 1, &ExtendedFrequency, Nb->ConfigHandle);
+  ThisPort->PrvFrequencyCap = ((Frequency | (ExtendedFrequency << HT_FREQUENCY_2800M)) &
+                               Nb->NorthBridgeFreqMask (ThisPort->NodeID, Interface, Nb));
+  // Check for Internal link restriction not to run at 1000 MHz (but allow lower)
+  if (IsPackageLinkInternal (Nb->GetPackageLink (ThisPort->NodeID, ThisPort->Link, Nb))) {
+    ThisPort->PrvFrequencyCap &= ~(HT_FREQUENCY_LIMIT_1000M & ~HT_FREQUENCY_LIMIT_800M);
+  }
+  ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure for link reganging.
+ *
+ * @HtNbMethod{::F_SET_LINK_REGANG}
+ *
+ * @param[in]     Node   the node on which to regang a link
+ * @param[in]     Link   the sublink 0 of the sublink pair to regang
+ * @param[in]     Nb     this northbridge
+ */
+VOID
+SetLinkRegang (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+  UINT32 Temp;
+
+  Temp = 1;
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
+
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure  for Unit Id Clumping.
+ *
+ * @HtNbMethod{::F_SET_LINK_UNITID_CLUMPING}
+ *
+ * This applies to the host root of a non-coherent chain.
+ *
+ * @param[in]     Node              the node on which to enable clumping
+ * @param[in]     Link              the link for which to enable clumping
+ * @param[in]     ClumpingEnables   the unit id clumping enables
+ * @param[in]     Nb                this northbridge
+ */
+VOID
+SetLinkUnitIdClumping (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       UINT32      ClumpingEnables,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR Reg;
+
+  // Host Unit Ids are not clumped.
+  ASSERT ((ClumpingEnables & 0x3) == 0);
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_CLUMPING0_0X110 + (4 * Link));
+
+  LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure for link frequency.
+ *
+ * @HtNbMethod{::F_SET_LINK_FREQUENCY}
+ *
+ * Handle extended frequencies.  For HT3 frequencies, ensure Retry and Scrambling are
+ * set. For HT1, clear them.
+ *
+ * @param[in]     Node        the node on which to set frequency for a link
+ * @param[in]     Link        the link to set frequency
+ * @param[in]     Frequency   the frequency to set
+ * @param[in]     Nb          this northbridge
+ */
+VOID
+SetLinkFrequency (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  ASSERT ((Frequency >= HT_FREQUENCY_600M && Frequency <= HT_FREQUENCY_3200M)
+          || (Frequency == HT_FREQUENCY_200M) || (Frequency == HT_FREQUENCY_400M));
+
+  // Handle extended frequencies, 2800 MHz and above.  31 > Frequency > 16 in this case.
+  if (Frequency > HT_FREQUENCY_2600M) {
+    Temp = 1;
+  } else {
+    // Clear it if not extended.
+    Temp = 0;
+  }
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register += HTHOST_FREQ_EXTENSION;
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register += HTHOST_FREQ_REV_REG;
+  Temp = (Frequency & 0x0F);
+  LibAmdPciWriteBits (Reg, 11, 8, &Temp, Nb->ConfigHandle);
+  //  Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
+  if (Frequency > HT_FREQUENCY_1000M) {
+    // Enable  for Gen3 frequencies
+    Temp = 1;
+  } else {
+    // Disable  for Gen1 frequencies
+    Temp = 0;
+  }
+  // HT3 retry mode enable / disable
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_RETRY0_0X130 + (4 * Link));
+  LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
+  // and Scrambling enable / disable
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
+  LibAmdPciWriteBits (Reg, 3, 3, &Temp, Nb->ConfigHandle);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.h
new file mode 100755
index 0000000000..eb7d1503ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbOptimization.h
@@ -0,0 +1,89 @@
+/**
+ * @file
+ *
+ * Link optimization generic support.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Get Link features into system data structure.
+ *
+ */
+VOID
+GatherLinkFeatures (
+  IN OUT   PORT_DESCRIPTOR  *ThisPort,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE      *Nb
+  );
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ */
+VOID
+SetLinkRegang (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Set the link's Unit Id Clumping enable.
+ *
+ */
+VOID
+SetLinkUnitIdClumping (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       UINT32      ClumpingEnables,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ */
+VOID
+SetLinkFrequency (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
new file mode 100755
index 0000000000..1c2e8af0a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.c
@@ -0,0 +1,331 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * These routines are needed for support of more than one feature area.
+ * Collect them in this file so build options don't remove them.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNotify.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "htNbUtilities.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ * @HtNbMethod{::F_MAKE_LINK_BASE}
+ *
+ * @param[in]     Node    the Node this Link is on
+ * @param[in]     Link    the Link
+ * @param[in]     Nb      this northbridge
+ *
+ * @return  the pci config address
+ */
+PCI_ADDR
+MakeLinkBase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR LinkBase;
+
+  ASSERT (Nb != NULL);
+  if (Link < 4) {
+    LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                        MakePciBusFromNode (Node),
+                                        MakePciDeviceFromNode (Node),
+                                        CPU_HTNB_FUNC_00,
+                                        REG_HT_CAP_BASE_0X80 + Link*HT_HOST_CAP_SIZE);
+  } else {
+    LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                        MakePciBusFromNode (Node),
+                                        MakePciDeviceFromNode (Node),
+                                        CPU_HTNB_FUNC_04,
+                                        REG_HT_CAP_BASE_0X80 + (Link - 4)*HT_HOST_CAP_SIZE);
+  }
+  return LinkBase;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ * @HtNbMethod{::F_READ_TRUE_LINK_FAIL_STATUS}
+ *
+ * Dependency!:  HT_FEATURES::SetHtControlRegisterBits
+ *
+ * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot.
+ *
+ * The table below summarizes correct responses of this routine.
+ * <TABLE>
+ *   <TR><TD> Family </TD> <TD> before </TD> <TD> after </TD> <TD> unconnected </TD> <TD> Notify? </TD> <TD> return </TD></TR>
+ *   <TR><TD>  10    </TD> <TD>   0    </TD> <TD>   0   </TD> <TD>     0       </TD> <TD>   No    </TD> <TD> FALSE  </TD></TR>
+ *   <TR><TD>  10    </TD> <TD>   1    </TD> <TD>   0   </TD> <TD>     0       </TD> <TD>   Yes   </TD> <TD> FALSE  </TD></TR>
+ *   <TR><TD>  10    </TD> <TD>   1    </TD> <TD>   0   </TD> <TD>     3       </TD> <TD>   No    </TD> <TD> TRUE   </TD></TR>
+ * </TABLE>
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Link   the Link on that Node to examine
+ * @param[in]     State  access to call back routine
+ * @param[in]     Nb     this northbridge
+ *
+ * @retval        TRUE   the Link is not connected or has hard error
+ * @retval        FALSE  the Link is connected
+ */
+BOOLEAN
+ReadTrueLinkFailStatus (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32    Before;
+  UINT32    After;
+  UINT32    Unconnected;
+  UINT32    Crc;
+  PCI_ADDR  Reg;
+
+  ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
+
+  Reg = Nb->MakeLinkBase (Node, Link, Nb);
+  Reg.Address.Register +=  HTHOST_LINK_CONTROL_REG;
+
+  // Save the CRC status before doing anything else.
+  // Read, Clear, re-read the error bits in the Link Control Register
+  // (FN0_84/A4/C4[4] = LinkFail bit),
+  // and check the connection status, TransOff and EndOfChain.
+  //
+  LibAmdPciReadBits (Reg, 9, 8, &Crc, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 4, 4, &Before, Nb->ConfigHandle);
+  State->HtFeatures->SetHtControlRegisterBits (Reg, 4, 4, &Before, State);
+  LibAmdPciReadBits (Reg, 4, 4, &After, Nb->ConfigHandle);
+  LibAmdPciReadBits (Reg, 7, 6, &Unconnected, Nb->ConfigHandle);
+
+  if (Before != After) {
+    if (Unconnected == 0) {
+      if (Crc != 0) {
+        // A sync flood occurred due to HT CRC
+        // Pass the Node and Link on which the generic sync flood event occurred.
+        NotifyAlertHwHtCrc (Node, Link, (UINT8)Crc, State);
+      } else {
+        // Some sync flood occurred
+        // Pass the Node and Link on which the generic sync flood event occurred.
+        NotifyAlertHwSyncFlood (Node, Link, State);
+      }
+    }
+  }
+  return (BOOLEAN) ((After != 0) || (Unconnected != 0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ * @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES}
+ *
+ * @param[in]     Node         the Node that will be examined
+ * @param[in]     TotalNodes   the total number of Nodes
+ * @param[in]     TotalCores   the total number of cores
+ * @param[in]     Nb           this northbridge
+ */
+VOID
+SetTotalNodesAndCores (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR NodeIDReg;
+  UINT32 Temp;
+
+  ASSERT ((Node < MAX_NODES) && (TotalNodes <= MAX_NODES));
+  NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                       MakePciBusFromNode (Node),
+                                       MakePciDeviceFromNode (Node),
+                                       CPU_HTNB_FUNC_00,
+                                       REG_NODE_ID_0X60);
+
+  Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0);
+  LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
+  Temp = TotalNodes - 1;
+  LibAmdPciWriteBits (NodeIDReg,  6,  4, &Temp, Nb->ConfigHandle);
+
+  NodeIDReg.Address.Register = REG_HT_EXTENDED_NODE_ID_F0X160;
+
+  Temp = (((TotalCores - 1) & HTREG_EXTNODE_CPUCNT_7_5) >> 5);
+  LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Count (1 based) of Nodes in the system.
+ *
+ * @HtNbMethod{::F_GET_NODE_COUNT}
+ *
+ * This is intended to support AP Core HT init, since the Discovery State data is not
+ * available (State->NodesDiscovered), there needs to be this way to find the number
+ * of Nodes.  The Node count can be read from the BSP.
+ *
+ * @param[in]     Nb           this northbridge
+ *
+ * @return        The number of nodes
+ */
+UINT8
+GetNodeCount (
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  PCI_ADDR NodeIDReg;
+  UINT32 Temp;
+
+  NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
+                                       MakePciBusFromNode (0),
+                                       MakePciDeviceFromNode (0),
+                                       CPU_HTNB_FUNC_00,
+                                       REG_NODE_ID_0X60);
+  LibAmdPciReadBits (NodeIDReg,  6,  4, &Temp, Nb->ConfigHandle);
+  return ((UINT8) (++Temp));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ * @HtNbMethod{::F_LIMIT_NODES}
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ */
+VOID
+LimitNodes (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT32 Temp;
+  PCI_ADDR Reg;
+
+  Temp = 1;
+  ASSERT ((Node < MAX_NODES));
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_HTNB_FUNC_00,
+                                 REG_LINK_TRANS_CONTROL_0X68);
+  LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ * @HtNbMethod{::F_GET_PACKAGE_LINK}
+ *
+ * Based on the link to package link mapping from BKDG, look up package link for
+ * the input link on the internal node number corresponding to Node id.
+ *
+ * @param[in]   Node       the node which has this link
+ * @param[in]   Link       the link on that node
+ * @param[in]   Nb         this northbridge
+ *
+ * @return      the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
+ *
+ */
+UINT8
+GetPackageLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  UINT8 ModuleType;
+  UINT8 Module;
+  UINTN PackageLinkMapItem;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
+  PackageLink = HT_LIST_TERMINAL;
+
+  Nb->GetModuleInfo (Node, &ModuleType, &Module, Nb);
+
+  if (ModuleType != 0) {
+    ASSERT (Nb->PackageLinkMap != NULL);
+    // Use table to find this module's package link
+    PackageLinkMapItem = 0;
+    while ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
+      if (((*Nb->PackageLinkMap)[PackageLinkMapItem].Module == Module) &&
+          ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
+        PackageLink = (*Nb->PackageLinkMap)[PackageLinkMapItem].PackageLink;
+        break;
+      }
+      PackageLinkMapItem++;
+    }
+  } else {
+    PackageLink = Link;
+  }
+  return PackageLink;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h
new file mode 100755
index 0000000000..de8ab35758
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/NbCommon/htNbUtilities.h
@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * Northbridge utility routines.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ */
+PCI_ADDR
+MakeLinkBase (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ */
+BOOLEAN
+ReadTrueLinkFailStatus (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ */
+VOID
+SetTotalNodesAndCores (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the Count (1 based) of Nodes in the system.
+ *
+ */
+UINT8
+GetNodeCount (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ */
+VOID
+LimitNodes (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ */
+UINT8
+GetPackageLink (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
new file mode 100755
index 0000000000..2e555dd235
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.c
@@ -0,0 +1,108 @@
+/**
+ * @file
+ *
+ * HyperTransport features constructor.
+ *
+ * Initialize the set of available features.
+ * This file implements build options using conditional compilation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTFEAT_FILECODE
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/**
+ * A no features Initializer.
+ */
+CONST HT_FEATURES ROMDATA HtFeaturesNone =
+{
+  (PF_COHERENT_DISCOVERY)CommonVoid,
+  (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
+  (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
+  (PF_PROCESS_LINK)CommonVoid,
+  (PF_GATHER_LINK_DATA)CommonVoid,
+  (PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY)CommonVoid,
+  (PF_REGANG_LINKS)CommonVoid,
+  (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
+  (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
+  (PF_SET_LINK_DATA)CommonVoid,
+  (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_SET_HT_CONTROL_REGISTER_BITS)CommonVoid,
+  (PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Provide the current Feature set implementation.
+ *
+ * Initialize using the installed initializer.
+ *
+ * @param[in]   HtFeatures      A feature object to initialize
+ * @param[in]   StdHeader       Opaque handle to standard config header
+*/
+VOID
+NewHtFeatures (
+     OUT   HT_FEATURES         *HtFeatures,
+  IN       AMD_CONFIG_PARAMS   *StdHeader
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) HtFeatures,
+    (VOID *) OptionHtConfiguration.HtOptionInternalFeatures ,
+    (UINT32) (sizeof (HT_FEATURES)),
+    StdHeader
+    );
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h
new file mode 100755
index 0000000000..aefdbda303
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htFeat.h
@@ -0,0 +1,559 @@
+/**
+ * @file
+ *
+ * HT Features.
+ *
+ * This file provides definitions used in common by HT internal modules.  The
+ * data is private and not for external client access.
+ * Definitions include the HT global internal state data structures, and
+ * access to the available HT features from the main HT entry point.
+ *
+ * This file includes the feature constructor and feature support which is not
+ * removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_FEAT_H_
+#define _HT_FEAT_H_
+
+/**
+ * @page htimplfeat HT Features Implementation Guide
+ *
+ * HT Features provides access to the HT Feature set, in a manner that isolates
+ * calling code from knowledge about the Feature set implementation or which
+ * features are supported in the current build.  In the case of feature sets, this
+ * is mostly used for build options to reduce code size by removing unneeded features.
+ *
+ * @par Adding a Method to HT Features
+ *
+ * To add a new method to the HT Features, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
+ *   </ul>
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtFeatInstances.
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::HT_FEATURES struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an HT Features Instance of the method.
+ *
+ * To implement an instance of a method for a specific feature follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the method typedef.
+ *
+ * - Name the function MethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtFeatMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other Ht feature routines or data as part of the method implementation, the function
+ *   must use HtFeatures->OtherMethod().  Do not directly access other HT feature
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple configurations.
+ *
+ * - Add the instance to the ::HT_FEATURES instances.
+ *
+ * - If a configuration does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking HT Features Methods.
+ *
+ * The first step is carried out only once by the top level HT entry point.
+ * @n @code
+ * HT_FEATURES HtFeatures;
+ *   // Get the current HT Feature Set
+ *   NewHtFeatures (&HtFeatures);
+ *   State->HtFeatures = &HtFeatures;
+ * @endcode
+ *
+ * The following example shows how to invoke a HT Features method.
+ * @n @code
+ *    State->HtFeatures->MethodName ();
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define MAX_PLATFORM_LINKS 64
+#define MAX_LINK_PAIRS 4
+
+/* These following are internal definitions */
+#define ROUTE_TO_SELF 0x0F
+#define INVALID_LINK 0xCC     /* Used in port list data structure to mark unused data entries.
+                                 Can also be used for no Link found in a port list search */
+
+/* definitions for working with the port list structure */
+#define PORTLIST_TYPE_CPU 0
+#define PORTLIST_TYPE_IO  1
+
+/*
+ * Hypertransport Capability definitions and macros
+ *
+ */
+
+#define HT_INTERFACE_CAP_SUBTYPE_MASK        ((UINT32)0xE00000FF)
+#define HT_CAP_SUBTYPE_MASK                  ((UINT32)0xF80000FF)
+
+/* HT Host Capability */
+#define HT_HOST_CAPABILITY                    1
+#define HT_HOST_CAP_SIZE                      0x20
+
+/* Host CapabilityRegisters */
+#define HTHOST_LINK_CAPABILITY_REG            0x00
+#define HTHOST_LINK_CONTROL_REG               0x04
+#define HTHOST_FREQ_REV_REG                   0x08
+#define HTHOST_REV_REV3                       0x60
+#define HTHOST_FEATURE_CAP_REG                0x0C
+#define HTHOST_BUFFER_COUNT_REG               0x10
+#define HTHOST_ISOC_REG                       0x14
+#define HTHOST_LINK_TYPE_REG                  0x18
+#define HTHOST_FREQ_EXTENSION                 0x1C
+#define HTHOST_TYPE_COHERENT                  3
+#define HTHOST_TYPE_NONCOHERENT               7
+#define HTHOST_TYPE_MASK                      0x1F
+
+/* HT Slave Capability (HT1 compat) */
+#define HT_SLAVE_CAPABILITY                   0
+#define HTSLAVE_LINK01_OFFSET                 4
+#define HTSLAVE_LINK_CONTROL_0_REG            4
+#define HTSLAVE_FREQ_REV_0_REG                0xC
+#define HTSLAVE_FEATURECAP_REG                0x10
+#define HT_CONTROL_CLEAR_CRC                  (~(3 << 8))
+#define HT_FREQUENCY_CLEAR_LINK_ERRORS        (~(0x7 << 12))
+#define MAX_BUID                              31
+
+/* HT3 gen Capability */
+#define HT_GEN3_CAPABILITY                    (0xD << 1)
+#define HTGEN3_LINK01_OFFSET                  0x10
+#define HTGEN3_LINK_TRAINING_0_REG            0x10
+
+/* HT3 Retry Capability */
+#define HT_RETRY_CAPABILITY                   (0xC << 1)
+#define HTRETRY_CONTROL_REG                   4
+
+/* Unit ID Clumping Capability */
+#define HT_UNITID_CAPABILITY                  (0x9 << 1)
+#define HTUNIT_SUPPORT_REG                    4
+#define HTUNIT_ENABLE_REG                     8
+#define HT_CLUMPING_PASSIVE                   1
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// Forward declarations.
+/// Used for forward reference.
+typedef struct _NORTHBRIDGE NORTHBRIDGE;
+typedef struct _HT_FEATURES HT_FEATURES;
+typedef struct _HT_INTERFACE HT_INTERFACE;
+
+/**
+ * Coherent Init Data.
+ *
+ * Metrics representing the coherent fabric which was discovered:  Degree of nodes, adjacency,
+ * node numbering permutations, and the topology which it matched.
+ */
+typedef struct {
+  /** The number of coherent Links connected on each Node (the 'Degree' of the Node) */
+  UINT8 SysDegree[MAX_NODES];
+  /** The systems adjacency (sysMatrix[i][j] is true if Node_i has a Link to Node_j) */
+  BOOLEAN SysMatrix[MAX_NODES][MAX_NODES];
+
+  UINT8 DbDegree[MAX_NODES];               /**< Like sysDegree, but for the current database topology */
+  BOOLEAN DbMatrix[MAX_NODES][MAX_NODES];  /**< Like sysMatrix, but for the current database topology */
+
+  UINT8 Perm[MAX_NODES];           /**< The Node mapping from the system to the database */
+  UINT8 ReversePerm[MAX_NODES];    /**< The Node mapping from the database to the system */
+  UINT8 *MatchedTopology;          /**< The topology that matched the current system or NULL */
+} COHERENT_FABRIC;
+
+/**
+ * Represent the system as Links of matched port pairs.
+ * A pair consists of a source Node, a Link to the destination Node, the
+ * destination Node, and its Link back to source Node.  The even indices are
+ * the source Nodes and Links, and the odd indices are for the destination
+ * Nodes and Links.
+ * @note The Port pair 2*N and 2*N+1 are connected together to form a Link
+ * (e.g. 0,1 and 8,9 are ports on either end of an HT Link) The lower number
+ * port (2*N) is the source port.  The device that owns the source port is
+ * always the device closer to the BSP. (i.e. nearer the CPU in a
+ * non-coherent chain, or the CPU with the lower NodeID).
+ */
+typedef struct {
+  /* This section is where the Link is in the system and how to find it */
+  UINT8 Type;              /**< 0 = CPU, 1 = Device, all others reserved */
+  UINT8 Link;              /**< 0-1 for devices, 0-7 for CPUs */
+  UINT8 NodeID;            /**< The Node, or a pointer to the devices parent Node */
+  UINT8 HostLink;          /**< For Devices, the root CPU's Link to the chain */
+  UINT8 HostDepth;         /**< Link Depth in chain, only used by devices */
+  PCI_ADDR Pointer;        /**< A pointer to the device's slave HT capability, so we don't have to keep searching */
+
+  /* This section is for the final settings, which are written to hardware */
+  BOOLEAN SelRegang;          /**< Indicates to software regang Link, only used for CPU->CPU Links */
+  UINT8 SelWidthIn;           /**< Width in setting */
+  UINT8 SelWidthOut;          /**< Width out setting */
+  UINT8 SelFrequency;         /**< Frequency setting */
+
+  /* This section is for keeping track of capabilities and possible configurations */
+  BOOLEAN RegangCap;            /**< Is the port capable of reganging? CPUs only */
+  UINT32 PrvFrequencyCap;       /**< Possible frequency settings */
+  UINT8 PrvWidthInCap;          /**< Possible Width setting */
+  UINT8 PrvWidthOutCap;         /**< Possible Width setting */
+  UINT32 CompositeFrequencyCap; /**< Possible Link frequency setting */
+  UINT32 ClumpingSupport;       /**< Unit ID Clumping value (bit 0 = passive support) */
+} PORT_DESCRIPTOR;
+
+/// Reference to a set of PORT_DESCRIPTORs.
+typedef PORT_DESCRIPTOR (*PORT_LIST)[MAX_PLATFORM_LINKS*2];
+
+/**
+ * Our global state data structure
+ */
+typedef struct {
+  AMD_HT_INTERFACE *HtBlock;  /**< The input data structure. */
+
+  UINT8 NodesDiscovered;      /**< One less than the number of Nodes found in the system */
+  UINT8 TotalLinks;           /**< How many HT Links have we discovered so far. */
+  UINT8 SysMpCap;             /**< The maximum number of Nodes that all processors are capable of */
+  AGESA_STATUS MaxEventClass; /**< The event class of the highest severity event generated */
+
+  PORT_LIST PortList;         /**< Represent the system as a set of Links, each two Ports. */
+  COHERENT_FABRIC *Fabric;                        /**< Describe metrics about the coherent fabric.
+                                                   * Limited scope to CoherentInit().  */
+  /* Data interface to other Agesa Modules */
+  SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap;      /**< For each Socket, Die the Node ids */
+  NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap;      /**< For each Node id, Socket and Die */
+  HOP_COUNT_TABLE *HopCountTable;                 /**< Table of hops between nodes */
+
+  /* Data for non-coherent initialization */
+  UINT8 AutoBusCurrent;                      /**< The next bus number available */
+  UINT8 UsedCfgMapEntries;                   /**< The next Config address Map set available, Limit 4 (F1X[EC:E0]) */
+  BOOLEAN IsUsingRecoveryHt;                 /**< Manual BUID Swap List processing should assume that HT Recovery was used */
+  BOOLEAN IsSetHtCrcFlood;                   /**< Enable setting of HT CRC Flood */
+  BOOLEAN IsUsingUnitIdClumping;             /**< Enable automatic Unit Id Clumping configuration. */
+
+  HT_INTERFACE *HtInterface;   /**< Interface for feature code to external parameters */
+  HT_FEATURES *HtFeatures;     /**< The current feature implementations */
+  NORTHBRIDGE *Nb;             /**< The current northbridge */
+
+  PLATFORM_CONFIGURATION *PlatformConfiguration;     /**< The platform specific configuration customizations */
+  VOID *ConfigHandle;          /**< Config Pointer, opaque handle for passing to lib */
+} STATE_DATA;
+
+//
+// Feature Method types
+//
+
+/**
+ * Discover all coherent devices in the system.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out] State     our global state
+ *
+ */
+typedef VOID F_COHERENT_DISCOVERY (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_COHERENT_DISCOVERY *PF_COHERENT_DISCOVERY;
+
+/**
+ * Using the description of the fabric topology we discovered, try to find a match
+ * among the supported topologies.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]    State    the discovered fabric, degree matrix, permutation
+ *
+ */
+typedef VOID F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES *PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES;
+
+/**
+ * Make a Hop Count Table for the installed topology.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]   State    access topology, permutation, update hop table
+ *
+ */
+typedef VOID F_MAKE_HOP_COUNT_TABLE (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_MAKE_HOP_COUNT_TABLE *PF_MAKE_HOP_COUNT_TABLE;
+
+/**
+ * Process a non-coherent Link.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Node          Node on which to process nc init
+ * @param[in]     Link          The non-coherent Link on that Node
+ * @param[in]     IsCompatChain Is this the chain with the southbridge? TRUE if yes.
+ * @param[in,out] State         our global state
+ */
+typedef VOID F_PROCESS_LINK (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       BOOLEAN       IsCompatChain,
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_PROCESS_LINK *PF_PROCESS_LINK;
+
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     State our global state, port list
+ */
+typedef VOID F_GATHER_LINK_DATA (
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GATHER_LINK_DATA *PF_GATHER_LINK_DATA;
+
+/**
+ * Optimize Links.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]    State         Process and update portlist
+ */
+typedef VOID F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY (
+  IN OUT   STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY *PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     State   our global state, port list
+ */
+typedef VOID F_SET_LINK_DATA (
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_SET_LINK_DATA *PF_SET_LINK_DATA;
+
+/**
+ * Retry must be enabled on all coherent links if it is enabled on any coherent links.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]   State       global state, port frequency settings.
+ *
+ * @retval          TRUE        Fixup occurred, all coherent links HT1
+ * @retval          FALSE       No changes
+ */
+typedef BOOLEAN F_IS_COHERENT_RETRY_FIXUP (
+  IN       STATE_DATA       *State
+  );
+/// Reference to a method.
+typedef F_IS_COHERENT_RETRY_FIXUP *PF_IS_COHERENT_RETRY_FIXUP;
+
+
+/**
+ * Test the subLinks of a Link to see if they qualify to be reganged.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out] State          Our global state
+ */
+typedef VOID F_REGANG_LINKS (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_REGANG_LINKS *PF_REGANG_LINKS;
+
+/**
+ * Iterate through all Links, checking the frequency of each subLink pair.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in,out]     State     Link state and port list
+ *
+ */
+typedef VOID F_SUBLINK_RATIO_FIXUP (
+  IN OUT   STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_SUBLINK_RATIO_FIXUP *PF_SUBLINK_RATIO_FIXUP;
+
+/**
+ * Identify Links which can have traffic distribution.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]   State   port list data
+ */
+typedef VOID F_TRAFFIC_DISTRIBUTION (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_TRAFFIC_DISTRIBUTION *PF_TRAFFIC_DISTRIBUTION;
+
+/**
+ * Access HT Link Control Register.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Reg      the PCI config address the control register
+ * @param[in]     HiBit    the high bit number
+ * @param[in]     LoBit    the low bit number
+ * @param[in]     Value    the value to write to that bit range. Bit 0 => loBit.
+ * @param[in]     State    Our state, config handle for lib
+ */
+typedef VOID F_SET_HT_CONTROL_REGISTER_BITS (
+  IN       PCI_ADDR    Reg,
+  IN       UINT8       HiBit,
+  IN       UINT8       LoBit,
+  IN       UINT32      *Value,
+  IN       STATE_DATA  *State
+  );
+/// Reference to a method.
+typedef F_SET_HT_CONTROL_REGISTER_BITS *PF_SET_HT_CONTROL_REGISTER_BITS;
+
+/**
+ * Translate a desired width setting to the bits to set in the register field.
+ *
+ * @HtFeatInstances.
+ *
+ * @param[in]     Value   the width Value
+ *
+ * @return The bits for the register
+ */
+typedef UINT8 F_CONVERT_WIDTH_TO_BITS (
+  IN       UINT8       Value
+  );
+/// Reference to a method.
+typedef F_CONVERT_WIDTH_TO_BITS *PF_CONVERT_WIDTH_TO_BITS;
+
+/**
+ * HT Feature Methods.
+ *
+ * Provides abstract methods which are bound to specific feature implementations.
+ */
+struct _HT_FEATURES {
+  PF_COHERENT_DISCOVERY CoherentDiscovery;    /**< Method: Coherent Discovery. */
+  PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES LookupComputeAndLoadRoutingTables;
+                                              /**< Method: Route the discovered system */
+  PF_MAKE_HOP_COUNT_TABLE MakeHopCountTable;  /**< Method: Compute slit hop counts */
+  PF_PROCESS_LINK ProcessLink;                /**< Method: Process a non-coherent Link. */
+  PF_GATHER_LINK_DATA GatherLinkData;         /**< Method: Gather Link Capabilities and data. */
+  PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY SelectOptimalWidthAndFrequency;
+                                              /**< Method: Optimize link features. */
+  PF_REGANG_LINKS RegangLinks;                /**< Method: Regang Sublinks. */
+  PF_SUBLINK_RATIO_FIXUP SubLinkRatioFixup;   /**< Method: Fix Sublink Frequency ratios */
+  PF_IS_COHERENT_RETRY_FIXUP IsCoherentRetryFixup;
+                                              /**< Method: Fix Retry mixed on coherent links. */
+  PF_SET_LINK_DATA SetLinkData;               /**< Method: Set optimized values. */
+  PF_TRAFFIC_DISTRIBUTION TrafficDistribution; /**< Method: Detect and Initialize Traffic Distribution */
+  PF_SET_HT_CONTROL_REGISTER_BITS SetHtControlRegisterBits; /**< Method: Access HT Link Control Reg. */
+  PF_CONVERT_WIDTH_TO_BITS ConvertWidthToBits; /**< Method: Convert a bit width to the value used for register setting. */
+};
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Provide the current Feature set implementation.
+ *
+ * Add an implementation reference for the constructor, just to make sure the page is created.
+ * @HtFeatMethod{::HT_FEATURES}.
+ *
+ */
+VOID
+NewHtFeatures (
+     OUT   HT_FEATURES          *HtFeatures,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+
+#endif  /* _HT_FEAT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
new file mode 100755
index 0000000000..e9aee6cbe7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph.h
@@ -0,0 +1,143 @@
+/**
+ * @file
+ *
+ * Topology Interface.
+ *
+ * Contains interface to the topology data.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _HT_GRAPH_H_
+#define _HT_GRAPH_H_
+
+/**
+ * @page htgraphdesign Graph Support routines
+ *
+ * These routines provide support for dealing with the graph representation
+ * of the topologies, along with the routing table information for that topology.
+ * The routing information is compressed and these routines currently decompress
+ * 'on the fly'.  A graph is represented as a set of routes. All the edges in the
+ * graph are routes; a direct route from Node i to Node j exists in the graph IFF
+ * there is an edge directly connecting Node i to Node j.  All other routes designate
+ * the edge which the route to that Node initially takes, by designating a Node
+ * to which a direct connection exists.  That is, the route to non-adjacent Node j
+ * from Node i specifies Node k where Node i directly connects to Node k.
+ *
+ *@code
+ * pseudo definition of compressed graph:
+ * typedef struct
+ * {
+ *     // First byte
+ *     UINT8 broadcast[8]:1;   // that is, 8 1-bit values
+ *     // Second byte
+ *     UINT8 requestRoute:4;   // [3:0]
+ *     UINT8 responseRoute:4;  // [7:4]
+ * } sRoute;
+ * typedef struct
+ * {
+ *     UINT8 size;
+ *     sRoute graph[size][size];
+ * } sGraph;
+ *@endcode
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+VOID
+GetAmdTopolist (
+  OUT   UINT8    ***List
+  );
+
+UINT8
+GraphHowManyNodes (
+  IN       UINT8    *Graph
+  );
+
+BOOLEAN
+GraphIsAdjacent (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetRsp (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetReq (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+UINT8
+GraphGetBc (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  );
+
+#endif  /* _HT_GRAPH_H_ */
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
new file mode 100755
index 0000000000..34215af04d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph.c
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * Routines to deal with topology data.
+ *
+ * Access the topologies and information about a topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "htGraph.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTGRAPH_HTGRAPH_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the AGESA built in topology list
+ *
+ * @param[out]    List    a pointer to the built in topology list
+ */
+VOID
+GetAmdTopolist (
+  OUT   UINT8    ***List
+  )
+{
+  // Cast below to hush CONST warning. The built in list must be CONST to be in ROM statically.
+  // The caller of this routine may get a topolist pointer from the interface, however, and
+  // that is not CONST, since it could be on the stack.
+  //
+  *List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the number of Nodes in the compressed graph
+ *
+ * @param[in]     Graph   a compressed graph
+ *
+ * @return the number of Nodes in the graph
+ */
+UINT8
+GraphHowManyNodes (
+  IN       UINT8    *Graph
+  )
+{
+  return Graph[0];
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns true if NodeA is directly connected to NodeB, false otherwise
+ *
+ * if NodeA == NodeB also returns false.
+ * Relies on rule that directly connected Nodes always route requests directly.
+ *
+ * @param[in]     Graph   the graph to examine
+ * @param[in]     NodeA   the Node number of the first Node
+ * @param[in]     NodeB   the Node number of the second Node
+ *
+ * @retval        TRUE    NodeA connects to NodeB
+ * @retval        FALSE   NodeA does not connect to NodeB
+ */
+BOOLEAN
+GraphIsAdjacent (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the graph Node used by NodeA to route responses targeted at NodeB.
+ *
+ *     This will be a Node directly connected to NodeA (possibly NodeB itself),
+ *     or "Route to Self" if NodeA and NodeB are the same Node.
+ *     Note that all Node numbers are abstract Node numbers of the topology graph,
+ *     it is the responsibility of the caller to apply any permutation needed.
+ *
+ * @param[in]     Graph the graph to examine
+ * @param[in]     NodeA the Node number of the first Node
+ * @param[in]     NodeB  the Node number of the second Node
+ *
+ * @return The response route Node
+ */
+UINT8
+GraphGetRsp (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns the graph Node used by NodeA to route requests targeted at NodeB.
+ *
+ *     This will be a Node directly connected to NodeA (possibly NodeB itself),
+ *     or "Route to Self" if NodeA and NodeB are the same Node.
+ *     Note that all Node numbers are abstract Node numbers of the topology graph,
+ *     it is the responsibility of the caller to apply any permutation needed.
+ *
+ * @param[in]     Graph the graph to examine
+ * @param[in]     NodeA the Node number of the first Node
+ * @param[in]     NodeB the Node number of the second Node
+ *
+ * @return The request route Node
+ */
+UINT8
+GraphGetReq (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Returns a bit vector of Nodes that NodeA should forward a broadcast from
+ * NodeB towards
+ *
+ * @param[in]     Graph the graph to examine
+ * @param[in]     NodeA the Node number of the first Node
+ * @param[in]     NodeB the Node number of the second Node
+ *
+ * @return the broadcast routes for NodeA from NodeB
+ */
+UINT8
+GraphGetBc (
+  IN       UINT8    *Graph,
+  IN       UINT8    NodeA,
+  IN       UINT8    NodeB
+  )
+{
+  UINT8 size;
+  size = Graph[0];
+  ASSERT ((NodeA < size) && (NodeB < size));
+  return Graph[1 + (NodeA*size + NodeB)*2];
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph1.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph1.c
new file mode 100755
index 0000000000..b6eac6210f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph1.c
@@ -0,0 +1,66 @@
+/**
+ * @file
+ *
+ * Single node topology
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   0
+ */
+/**
+ * single node
+ */
+/**
+ * @dot
+ strict graph one {
+     node [shape="plaintext"];
+     0;
+     }
+     @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySingleNode[] =
+{
+  0x01,
+  0x00, 0xFF  // Node 0
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph2.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph2.c
new file mode 100755
index 0000000000..32f952c1e2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph2.c
@@ -0,0 +1,67 @@
+/**
+ * @file
+ *
+ * Two nodes.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *    0---1
+ */
+/**
+ * Two Nodes.
+ */
+/**
+ * @dot
+ strict graph two {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     }
+     @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyDualNode[] =
+{
+  0x02,
+  0x02, 0xFF,   0x00, 0x11,  // Node 0
+  0x00, 0x00,   0x01, 0xFF   // Node 1
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c
new file mode 100755
index 0000000000..68e8207c16
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Line.c
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * Three Line.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2
+ *   |
+ *   |
+ *   0---1
+ */
+/**
+ * Three Line
+ */
+/**
+ * @dot
+ strict graph three {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     0 -- 2 ;
+     }
+     @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyThreeLine[] =
+{
+  0x03,
+  0x06, 0xFF,  0x04, 0x11,  0x02, 0x22,  // Node 0
+  0x00, 0x00,  0x01, 0xFF,  0x00, 0x00,  // Node 1
+  0x00, 0x00,  0x00, 0x00,  0x01, 0xFF   // Node 2
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c
new file mode 100755
index 0000000000..97a7285f97
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph3Triangle.c
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * Three Triangle Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2
+ *   |\
+ *   |  \
+ *   0---1
+ */
+/**
+ * Three triangle
+ */
+/**
+ * @dot
+ strict graph triangle {
+ node [shape="plaintext"];
+ 0 -- 1 ;
+ 0 -- 2 ;
+ 1 -- 2 ;
+ }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyTriangle[] =
+{
+  0x03,
+  0x06, 0xFF,  0x00, 0x11,  0x00, 0x22,  // Node 0
+  0x00, 0x00,  0x05, 0xFF,  0x00, 0x22,  // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x03, 0xFF   // Node 2
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c
new file mode 100755
index 0000000000..193fa8f6ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Degenerate.c
@@ -0,0 +1,77 @@
+/**
+ * @file
+ *
+ * Four node degenerate.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2   3
+ *   |\  |
+ *   |  \|
+ *   0---1
+ */
+/**
+ * Four Node degenerate
+ */
+/**
+ * @dot
+   strict graph degen4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 2 ;
+     1 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[] =
+{
+  0x04,
+  0x06, 0xFF,   0x00, 0x11,   0x00, 0x22,   0x00, 0x11,  // Node 0
+  0x08, 0x00,   0x0D, 0xFF,   0x08, 0x22,   0x05, 0x33,  // Node 1
+  0x00, 0x00,   0x00, 0x11,   0x03, 0xFF,   0x00, 0x11,  // Node 2
+  0x00, 0x11,   0x00, 0x11,   0x00, 0x11,   0x02, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4FullyConnected.c
new file mode 100755
index 0000000000..4cb69084ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4FullyConnected.c
@@ -0,0 +1,79 @@
+/**
+ * @file
+ *
+ * Four node fully connected.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |\ /|
+ *   |/ \|
+ *   0---1
+ */
+/**
+ * Four Node Fully
+ */
+/**
+ * @dot
+   strict graph full4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     0 -- 3 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourFully[] =
+{
+  0x04,
+  0x0E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  // Node 0
+  0x00, 0x00,  0x0D, 0xFF,  0x00, 0x22,  0x00, 0x33,  // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x0B, 0xFF,  0x00, 0x33,  // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x07, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c
new file mode 100755
index 0000000000..3b10b876ad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Kite.c
@@ -0,0 +1,78 @@
+/**
+ * @file
+ *
+ * Four node kite Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |\  |
+ *   |  \|
+ *   0---1
+ */
+/**
+ * Four Node kite
+ */
+/**
+ * @dot
+   strict graph kite4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourKite[] =
+{
+  0x04,
+  0x06, 0xFF,   0x00, 0x11,   0x00, 0x22,   0x00, 0x11,  // Node 0
+  0x08, 0x00,   0x0D, 0xFF,   0x00, 0x22,   0x00, 0x33,  // Node 1
+  0x00, 0x00,   0x00, 0x11,   0x0B, 0xFF,   0x01, 0x33,  // Node 2
+  0x00, 0x22,   0x00, 0x11,   0x00, 0x22,   0x06, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c
new file mode 100755
index 0000000000..013bac1fe7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Line.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Four node Line Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2   3
+ *   |   |
+ *   |   |
+ *   0---1
+ */
+/**
+ * Four Node line
+ */
+/**
+ * @dot
+   strict graph line4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourLine[] =
+{
+  0x04,
+  0x06, 0xFF,   0x04, 0x11,   0x02, 0x22,   0x04, 0x11,  // Node 0
+  0x08, 0x00,   0x09, 0xFF,   0x08, 0x00,   0x01, 0x33,  // Node 1
+  0x00, 0x00,   0x00, 0x00,   0x01, 0xFF,   0x00, 0x00,  // Node 2
+  0x00, 0x11,   0x00, 0x11,   0x00, 0x11,   0x02, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c
new file mode 100755
index 0000000000..1da11d3a90
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Square.c
@@ -0,0 +1,77 @@
+/**
+ * @file
+ *
+ * Four node Square Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |   |
+ *   |   |
+ *   0---1
+ */
+/**
+ * Four Node square
+ */
+/**
+ * @dot
+   strict graph square4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourSquare[] =
+{
+  0x04,
+  0x06, 0xFF,   0x00, 0x11,   0x02, 0x22,   0x00, 0x22,  // Node 0
+  0x00, 0x00,   0x09, 0xFF,   0x00, 0x33,   0x01, 0x33,  // Node 1
+  0x08, 0x00,   0x00, 0x00,   0x09, 0xFF,   0x00, 0x33,  // Node 2
+  0x00, 0x11,   0x04, 0x11,   0x00, 0x22,   0x06, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c
new file mode 100755
index 0000000000..b3c9a8f366
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph4Star.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Four node Star Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *   2---3
+ *   |\
+ *   |  \
+ *   0   1
+ */
+/**
+ * Four Node Star
+ */
+/**
+ * @dot
+   strict graph star4 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     0 -- 2 ;
+     1 -- 2 ;
+     2 -- 3 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFourStar[] =
+{
+  0x04,
+  0x04, 0xFF,   0x00, 0x22,   0x00, 0x22,   0x00, 0x22,  // Node 0
+  0x00, 0x22,   0x04, 0xFF,   0x00, 0x22,   0x00, 0x22,  // Node 1
+  0x0A, 0x00,   0x09, 0x11,   0x0B, 0xFF,   0x03, 0x33,  // Node 2
+  0x00, 0x22,   0x00, 0x22,   0x00, 0x22,   0x04, 0xFF   // Node 3
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5FullyConnected.c
new file mode 100755
index 0000000000..4910eb6d4a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5FullyConnected.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Five node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * Five node fully connected
+ */
+/**
+ * @dot
+   strict graph full5 {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     0 -- 2 ;
+     0 -- 3 ;
+     0 -- 4 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     1 -- 4 ;
+     2 -- 3 ;
+     2 -- 4 ;
+     3 -- 4 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFiveFully[] =
+{
+  0x05,
+  0x1E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44, // Node 0
+  0x00, 0x00,  0x1D, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x1B, 0xFF,  0x00, 0x33,  0x00, 0x44, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x17, 0xFF,  0x00, 0x44, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x0F, 0xFF  // Node 4
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5TwistedLadder.c
new file mode 100755
index 0000000000..61369f4d23
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph5TwistedLadder.c
@@ -0,0 +1,85 @@
+/**
+ * @file
+ *
+ * Five node pop order twisted ladder Topology.
+ *
+ * The population order fall back to five nodes on a twisted ladder.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *
+ *  4
+ *  |\
+ *  |  \
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * Five node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl5 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     3 -- 4 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[] =
+{
+  0x05,
+  0x06, 0xFF,  0x04, 0x11,  0x02, 0x22,  0x00, 0x11,  0x00, 0x22, // Node0
+  0x08, 0x00,  0x09, 0xFF,  0x08, 0x00,  0x01, 0x33,  0x00, 0x30, // Node1
+  0x10, 0x00,  0x10, 0x00,  0x11, 0xFF,  0x00, 0x40,  0x01, 0x44, // Node2
+  0x00, 0x11,  0x00, 0x11,  0x00, 0x14,  0x12, 0xFF,  0x02, 0x44, // Node3
+  0x00, 0x22,  0x00, 0x23,  0x00, 0x22,  0x04, 0x33,  0x0C, 0xFF  // Node4
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonLower.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonLower.c
new file mode 100755
index 0000000000..592644f52a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonLower.c
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Six node hydra Topology using "Doubloon/Drachma", Lower nodes remain.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 6 node hydra doubloon lower nodes, 3 MCM processors.
+ * For partial populations, note nodes are removed in pairs.
+ */
+/**
+ * @dot
+   strict graph doubloon8lower {
+     node [shape="plaintext"];
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;
+     0 -- 2 ;    1 -- 2 ;   2 -- 4 ;   3 -- 5 ;
+     0 -- 4 ;    1 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[] =
+{
+  0x06,
+  0x16, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44, // Node 0
+  0x00, 0x00,  0x25, 0xFF,  0x00, 0x22,  0x00, 0x22,  0x00, 0x55,  0x01, 0x55, // Node 1
+  0x08, 0x00,  0x08, 0x11,  0x19, 0xFF,  0x03, 0x33,  0x08, 0x44,  0x00, 0x44, // Node 2
+  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0x24, 0xFF,  0x00, 0x55,  0x04, 0x55, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x25, 0xFF,  0x00, 0x55, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x1A, 0xFF, // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c
new file mode 100755
index 0000000000..afadd09c49
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6DoubloonUpper.c
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Six node hydra Topology using "Doubloon/Drachma", Upper nodes remain.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 6 node hydra drachma, upper nodes remain, 3 MCM processors.
+ * For partial population cases, note that nodes are removed in pairs.
+ */
+/**
+ * @dot
+   strict graph doubloon6upper {
+     node [shape="plaintext"];
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;
+     0 -- 2 ;    1 -- 2 ;   2 -- 4 ;   3 -- 5 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 5 ;   3 -- 4 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[] =
+{
+  0x06,
+  0x16, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44, // Node 0
+  0x00, 0x00,  0x25, 0xFF,  0x00, 0x22,  0x00, 0x22,  0x00, 0x55,  0x01, 0x55, // Node 1
+  0x08, 0x00,  0x08, 0x11,  0x3B, 0xFF,  0x03, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 2
+  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0x34, 0xFF,  0x00, 0x44,  0x00, 0x55, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x00, 0x22,  0x00, 0x33,  0x2D, 0xFF,  0x00, 0x55, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x1E, 0xFF, // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6FullyConnected.c
new file mode 100755
index 0000000000..87364db493
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6FullyConnected.c
@@ -0,0 +1,82 @@
+/**
+ * @file
+ *
+ * Six node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 6 node fully connected
+ */
+/**
+ * @dot
+   strict graph full6 {
+     node [shape="plaintext"];
+     0 -- 1 ;
+     0 -- 2 ;
+     0 -- 3 ;
+     0 -- 4 ;
+     0 -- 5 ;
+     1 -- 2 ;
+     1 -- 3 ;
+     1 -- 4 ;
+     1 -- 5 ;
+     2 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+     4 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixFully[] =
+{
+  0x06,
+  0x3E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 0
+  0x00, 0x00,  0x3D, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x3B, 0xFF,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x37, 0xFF,  0x00, 0x44,  0x00, 0x55, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x2F, 0xFF,  0x00, 0x55, // Node 4
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x1F, 0xFF  // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwinTriangles.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwinTriangles.c
new file mode 100755
index 0000000000..5e59d901eb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwinTriangles.c
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * A six node Topology of three MCMs.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/* (2 fully connected three ways connected at the 'corners')
+ *
+ *       5
+ *      /| \
+ *     / 1 - 3
+ *    / /    /
+ *   4 /    /
+ *   | \   /
+ *   0 - 2-
+ */
+/**
+ * Six Node hydra
+ */
+/**
+ * @dot
+   strict graph hmcm6 {
+     node [shape="plaintext"];
+     subgraph even {
+     0 -- 2 ;    2 -- 4 ;
+     0 -- 4 ;
+     }
+     subgraph odd {
+     1 -- 3 ;   3 -- 5
+     1 -- 5 ;
+     }
+     {rank=same; 0; 2; 1; 3}
+     {rank=same; 4; 5}
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[] =
+{
+  0x06,
+  0x16, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44,  // Node 0
+  0x00, 0x00,  0x29, 0xFF,  0x00, 0x33,  0x01, 0x33,  0x00, 0x55,  0x01, 0x55,  // Node 1
+  0x08, 0x00,  0x00, 0x00,  0x19, 0xFF,  0x00, 0x33,  0x08, 0x44,  0x00, 0x44,  // Node 2
+  0x00, 0x11,  0x04, 0x11,  0x00, 0x22,  0x26, 0xFF,  0x00, 0x55,  0x04, 0x55,  // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x25, 0xFF,  0x00, 0x55,  // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x1A, 0xFF,  // Node 5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwistedLadder.c
new file mode 100755
index 0000000000..85e94ce614
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph6TwistedLadder.c
@@ -0,0 +1,88 @@
+/**
+ * @file
+ *
+ * Six node pop order twisted ladder Topology.
+ *
+ * The population order fall back to Six nodes on a twisted ladder.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*
+ *
+ *  4   5
+ *  |\ /|
+ *  |/ \|
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 6 node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl6 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[] =
+{
+  0x06,
+  0x06, 0xFF,  0x04, 0x11,  0x02, 0x22,  0x00, 0x11,  0x02, 0x22,  0x00, 0x12, // Node0
+  0x08, 0x00,  0x09, 0xFF,  0x00, 0x00,  0x01, 0x33,  0x00, 0x03,  0x01, 0x33, // Node1
+  0x30, 0x00,  0x00, 0x00,  0x31, 0xFF,  0x00, 0x54,  0x21, 0x44,  0x00, 0x55, // Node2
+  0x00, 0x11,  0x30, 0x11,  0x00, 0x45,  0x32, 0xFF,  0x00, 0x44,  0x12, 0x55, // Node3
+  0x00, 0x22,  0x00, 0x32,  0x08, 0x22,  0x00, 0x33,  0x0C, 0xFF,  0x00, 0x32, // Node4
+  0x00, 0x23,  0x00, 0x33,  0x00, 0x22,  0x04, 0x33,  0x00, 0x23,  0x0C, 0xFF  // Node5
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7FullyConnected.c
new file mode 100755
index 0000000000..f0039d4239
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7FullyConnected.c
@@ -0,0 +1,74 @@
+/**
+ * @file
+ *
+ * Seven node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 7 node fully connected
+ */
+/**
+ * @dot
+   strict graph full7 {
+     node [shape="plaintext"];
+     0 -- 1 ;    1 -- 2 ;   2 -- 3 ;     3 -- 4 ;   4 -- 5 ; 5 -- 6 ;
+     0 -- 2 ;    1 -- 3 ;   2 -- 4 ;     3 -- 5 ;   4 -- 6 ;
+     0 -- 3 ;    1 -- 4 ;   2 -- 5 ;     3 -- 6 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 6 ;
+     0 -- 5 ;    1 -- 6 ;
+     0 -- 6 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySevenFully[] =
+{
+  0x07,
+  0x7E, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 0
+  0x00, 0x00,  0x7D, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0x7B, 0xFF,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x77, 0xFF,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x6F, 0xFF,  0x00, 0x55,  0x00, 0x66, // Node 4
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x5F, 0xFF,  0x00, 0x66, // Node 5
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x3F, 0xFF  // Node 6
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7TwistedLadder.c
new file mode 100755
index 0000000000..cb25523d33
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph7TwistedLadder.c
@@ -0,0 +1,91 @@
+/**
+ * @file
+ *
+ * Seven node pop order twisted ladder Topology.
+ *
+ * The population order fall back to Seven nodes on a twisted ladder.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*  6
+ *  |
+ *  4   5
+ *  |\ /|
+ *  |/ \|
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 7 node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl7 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     {rank=same; 6}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+     4 -- 6 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[] =
+{
+  0x07,
+  0x06, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x12,  0x00, 0x22,  0x00, 0x22,  0x00, 0x22, // Node0
+  0x00, 0x00,  0x09, 0xFF,  0x00, 0x03,  0x01, 0x33,  0x00, 0x33,  0x00, 0x33,  0x00, 0x33, // Node1
+  0x30, 0x00,  0x00, 0x50,  0x31, 0xFF,  0x00, 0x54,  0x21, 0x44,  0x01, 0x55,  0x21, 0x44, // Node2
+  0x00, 0x41,  0x30, 0x11,  0x00, 0x45,  0x32, 0xFF,  0x02, 0x44,  0x12, 0x55,  0x02, 0x44, // Node3
+  0x48, 0x22,  0x40, 0x33,  0x48, 0x22,  0x40, 0x33,  0x4C, 0xFF,  0x40, 0x32,  0x0C, 0x66, // Node4
+  0x00, 0x22,  0x04, 0x33,  0x00, 0x22,  0x04, 0x33,  0x00, 0x23,  0x0C, 0xFF,  0x00, 0x23, // Node5
+  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x10, 0xFF  // Node6
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c
new file mode 100755
index 0000000000..895ed1b8b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8DoubloonM.c
@@ -0,0 +1,73 @@
+/**
+ * @file
+ *
+ * Eight node hydra Topology using "Doubloon/Drachma".
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 8 node hydra doubloon, 4 MCM processors.
+ */
+/**
+ * @dot
+   strict graph doubloon8 {
+     node [shape="plaintext"];
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;   6 -- 7 ;
+     0 -- 2 ;    1 -- 2 ;   2 -- 4 ;   3 -- 5 ;   4 -- 6 ; 5 -- 6 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 6 ;   3 -- 7 ;
+     0 -- 6 ;    1 -- 7 ;   2 -- 7 ;   3 -- 6
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[] =
+{
+  0x08,
+  0x56, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44,  0x02, 0x66,  0x00, 0x66, // Node 0
+  0x00, 0x00,  0xA5, 0xFF,  0x00, 0x22,  0x00, 0x22,  0x00, 0x55,  0x01, 0x55,  0x00, 0x77,  0x01, 0x77, // Node 1
+  0x08, 0x00,  0x08, 0x11,  0xDB, 0xFF,  0x03, 0x33,  0x08, 0x44,  0x00, 0x44,  0x00, 0x66,  0x00, 0x77, // Node 2
+  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0xE4, 0xFF,  0x00, 0x55,  0x04, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x65, 0xFF,  0x00, 0x55,  0x00, 0x66,  0x00, 0x66, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x5A, 0xFF,  0x00, 0x66,  0x00, 0x66, // Node 5
+  0x80, 0x00,  0x00, 0x00,  0x00, 0x22,  0x00, 0x33,  0x80, 0x44,  0x80, 0x55,  0xBD, 0xFF,  0x30, 0x77, // Node 6
+  0x00, 0x11,  0x40, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x66,  0x00, 0x66,  0x00, 0x66,  0x4E, 0xFF  // Node 7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8FullyConnected.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8FullyConnected.c
new file mode 100755
index 0000000000..edde208b89
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8FullyConnected.c
@@ -0,0 +1,76 @@
+/**
+ * @file
+ *
+ * Eight node Fully Connected Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/**
+ * 8 node fully connected
+ */
+/**
+ * @dot
+   strict graph full8 {
+     node [shape="plaintext"];
+     0 -- 1 ;    1 -- 2 ;   2 -- 3 ;   3 -- 4 ;   4 -- 5 ; 5 -- 6 ;  6 -- 7 ;
+     0 -- 2 ;    1 -- 3 ;   2 -- 4 ;   3 -- 5 ;   4 -- 6 ; 5 -- 7 ;
+     0 -- 3 ;    1 -- 4 ;   2 -- 5 ;   3 -- 6 ;   4 -- 7 ;
+     0 -- 4 ;    1 -- 5 ;   2 -- 6 ;   3 -- 7 ;
+     0 -- 5 ;    1 -- 6 ;   2 -- 7 ;
+     0 -- 6 ;    1 -- 7 ;
+     0 -- 7 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightFully[] =
+{
+  0x08,
+  0xFE, 0xFF,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 0
+  0x00, 0x00,  0xFD, 0xFF,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 1
+  0x00, 0x00,  0x00, 0x11,  0xFB, 0xFF,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 2
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0xF7, 0xFF,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 3
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0xEF, 0xFF,  0x00, 0x55,  0x00, 0x66,  0x00, 0x77, // Node 4
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0xDF, 0xFF,  0x00, 0x66,  0x00, 0x77, // Node 5
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0xBF, 0xFF,  0x00, 0x77, // Node 6
+  0x00, 0x00,  0x00, 0x11,  0x00, 0x22,  0x00, 0x33,  0x00, 0x44,  0x00, 0x55,  0x00, 0x66,  0x7F, 0xFF  // Node 7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
new file mode 100755
index 0000000000..2b0e98b7bb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8Ladder.c
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Eight node Ladder Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*  6---7
+ *  |   |
+ *  4---5
+ *  |   |
+ *  2---3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 8 node ladder
+ */
+/**
+ * @dot
+   strict graph ladder8 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     {rank=same; 6; 7}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 3 ;
+     3 -- 5 ;
+     4 -- 5 ;
+     4 -- 6 ;
+     5 -- 7 ;
+     6 -- 7 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
+{
+  0x08,
+  0x06, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x22,  0x00, 0x22,  0x02, 0x22,  0x00, 0x22, // Node0
+  0x00, 0x00,  0x09, 0xFF,  0x00, 0x33,  0x01, 0x33,  0x00, 0x33,  0x01, 0x33,  0x00, 0x33,  0x01, 0x33, // Node1
+  0x18, 0x00,  0x00, 0x00,  0x19, 0xFF,  0x00, 0x33,  0x09, 0x44,  0x00, 0x44,  0x09, 0x44,  0x00, 0x44, // Node2
+  0x00, 0x11,  0x24, 0x11,  0x00, 0x22,  0x26, 0xFF,  0x00, 0x55,  0x06, 0x55,  0x00, 0x55,  0x06, 0x55, // Node3
+  0x60, 0x22,  0x00, 0x22,  0x60, 0x22,  0x00, 0x22,  0x64, 0xFF,  0x00, 0x55,  0x24, 0x66,  0x00, 0x66, // Node4
+  0x00, 0x33,  0x90, 0x33,  0x00, 0x33,  0x90, 0x33,  0x00, 0x44,  0x98, 0xFF,  0x00, 0x77,  0x18, 0x77, // Node5
+  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x44,  0x90, 0xFF,  0x00, 0x77, // Node6
+  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
+};
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
new file mode 100755
index 0000000000..57f7d599d2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Eight node Topology of two fully connected four ways.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/* (2 fully connected four ways connected at the 'corners')
+ *
+ *       5 - 7
+ *      /| X |
+ *     / 1 - 3
+ *    / / /  /
+ *   4 - 6  /
+ *   | X | /
+ *   0 - 2-
+ */
+/**
+ * 8 node twin fully connected four ways, connected by the MCM internal links.
+ */
+/**
+ * @dot
+   strict graph hydra8 {
+     node [shape="plaintext"];
+     subgraph even {
+     0 -- 2 ;    2 -- 4 ;   4 -- 6 ;
+     0 -- 4 ;    2 -- 6 ;
+     0 -- 6 ;
+     }
+     subgraph odd {
+     1 -- 3 ;   3 -- 5 ;   5 -- 7 ;
+     1 -- 5 ;   3 -- 7 ;
+     1 -- 7 ;
+     }
+     {rank=same; 0; 2; 1; 3}
+     {rank=same; 4; 6; 5; 7}
+     0 -- 1 ;    2 -- 3 ;   4 -- 5 ;   6 -- 7 ;
+     }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[] =
+{
+  0x08,
+  0x56, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x22,  0x02, 0x44,  0x00, 0x44,  0x02, 0x66,  0x00, 0x66, // Node 0
+  0x00, 0x00,  0xA9, 0xFF,  0x00, 0x33,  0x01, 0x33,  0x00, 0x55,  0x01, 0x55,  0x00, 0x77,  0x01, 0x77, // Node 1
+  0x08, 0x00,  0x00, 0x00,  0x59, 0xFF,  0x00, 0x33,  0x08, 0x44,  0x00, 0x44,  0x08, 0x66,  0x00, 0x66, // Node 2
+  0x00, 0x11,  0x04, 0x11,  0x00, 0x22,  0xA6, 0xFF,  0x00, 0x55,  0x04, 0x55,  0x00, 0x77,  0x04, 0x77, // Node 3
+  0x20, 0x00,  0x00, 0x00,  0x20, 0x22,  0x00, 0x22,  0x65, 0xFF,  0x00, 0x55,  0x20, 0x66,  0x00, 0x66, // Node 4
+  0x00, 0x11,  0x10, 0x11,  0x00, 0x33,  0x10, 0x33,  0x00, 0x44,  0x9A, 0xFF,  0x00, 0x77,  0x10, 0x77, // Node 5
+  0x80, 0x00,  0x00, 0x00,  0x80, 0x22,  0x00, 0x22,  0x80, 0x44,  0x00, 0x44,  0x95, 0xFF,  0x00, 0x77, // Node 6
+  0x00, 0x11,  0x40, 0x11,  0x00, 0x33,  0x40, 0x33,  0x00, 0x55,  0x40, 0x55,  0x00, 0x66,  0x6A, 0xFF  // Node 7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwistedLadder.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwistedLadder.c
new file mode 100755
index 0000000000..5b19c721b0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htGraph/htGraph8TwistedLadder.c
@@ -0,0 +1,92 @@
+/**
+ * @file
+ *
+ * Eight node twisted ladder Topology.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+#include "Porting.h"
+#include "htTopologies.h"
+
+/*  6---7
+ *  |   |
+ *  4   5
+ *  |\ /|
+ *  |/ \|
+ *  2   3
+ *  |   |
+ *  0---1
+ */
+/**
+ * 8 node twisted ladder
+ */
+/**
+ * @dot
+   strict graph twl8 {
+     node [shape="plaintext"];
+     {rank=same; 0; 1}
+     {rank=same; 2; 3}
+     {rank=same; 4; 5}
+     {rank=same; 6; 7}
+     0 -- 1 ;
+     0 -- 2 ;
+     1 -- 3 ;
+     2 -- 4 ;
+     2 -- 5 ;
+     3 -- 4 ;
+     3 -- 5 ;
+     4 -- 6 ;
+     5 -- 7 ;
+     6 -- 7 ;
+   }
+ @enddot
+ *
+ */
+CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[] =
+{
+  0x08,
+  0x06, 0xFF,  0x00, 0x11,  0x02, 0x22,  0x00, 0x12,  0x00, 0x22,  0x00, 0x22,  0x00, 0x22,  0x00, 0x22, // Node0
+  0x00, 0x00,  0x09, 0xFF,  0x00, 0x03,  0x01, 0x33,  0x00, 0x33,  0x00, 0x33,  0x00, 0x33,  0x00, 0x33, // Node1
+  0x30, 0x00,  0x00, 0x50,  0x31, 0xFF,  0x00, 0x54,  0x21, 0x44,  0x01, 0x55,  0x21, 0x44,  0x01, 0x55, // Node2
+  0x00, 0x41,  0x30, 0x11,  0x00, 0x45,  0x32, 0xFF,  0x02, 0x44,  0x12, 0x55,  0x02, 0x44,  0x12, 0x55, // Node3
+  0x48, 0x22,  0x40, 0x33,  0x48, 0x22,  0x40, 0x33,  0x4C, 0xFF,  0x00, 0x32,  0x0C, 0x66,  0x00, 0x36, // Node4
+  0x80, 0x22,  0x84, 0x33,  0x80, 0x22,  0x84, 0x33,  0x00, 0x23,  0x8C, 0xFF,  0x00, 0x27,  0x0C, 0x77, // Node5
+  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x00, 0x44,  0x80, 0x44,  0x00, 0x74,  0x90, 0xFF,  0x00, 0x77, // Node6
+  0x00, 0x55,  0x00, 0x55,  0x00, 0x55,  0x00, 0x55,  0x00, 0x65,  0x40, 0x55,  0x00, 0x66,  0x60, 0xFF  // Node7
+};
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
new file mode 100755
index 0000000000..1639a22735
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.c
@@ -0,0 +1,238 @@
+/**
+ * @file
+ *
+ * External Interface implementation.
+ *
+ * Contains routines for implementing the interface to the client BIOS.
+ * This file includes the interface access constructor.
+ * This file implements build options using conditional compilation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "CommonReturns.h"
+#include "htInterfaceGeneral.h"
+#include "htInterfaceCoherent.h"
+#include "htInterfaceNonCoherent.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACE_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * The default initializer for the HT internal interface, full features.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceDefault =
+{
+  GetCpu2CpuPcbLimits,
+  GetSkipRegang,
+  NewHopCountTable,
+  GetOverrideBusNumbers,
+  GetManualBuidSwapList,
+  GetDeviceCapOverride,
+  GetIoPcbLimits,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  CleanMapsAfterError,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * The non-coherent only build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceNonCoherentOnly =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  GetOverrideBusNumbers,
+  GetManualBuidSwapList,
+  GetDeviceCapOverride,
+  GetIoPcbLimits,
+  GetSocketFromMap,
+  GetIgnoreLink,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  SetNodeToSocketMap,
+  GetMinNbCoreFreq
+};
+
+/**
+ * Topology Maps only feature build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceMapsOnly =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
+  (PF_GET_IGNORE_LINK)CommonReturnFalse,
+  PostMapToAp,
+  NewNodeAndSocketTables,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  SetNodeToSocketMap,
+  (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
+};
+
+/**
+ * No features build option initializer for the HT internal interface.
+ */
+CONST HT_INTERFACE ROMDATA HtInterfaceNone =
+{
+  (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
+  (PF_GET_SKIP_REGANG)CommonReturnFalse,
+  (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
+  (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
+  (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
+  (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
+  (PF_GET_IO_PCB_LIMITS)CommonVoid,
+  (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
+  (PF_GET_IGNORE_LINK)CommonReturnFalse,
+  (PF_POST_MAP_TO_AP)CommonVoid,
+  (PF_NEW_NODE_AND_SOCKET_TABLES)CommonVoid,
+  (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
+  (PF_SET_NODE_TO_SOCKET_MAP)CommonVoid,
+  (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
+};
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * A constructor for the internal Ht Interface.
+ *
+ * The install has a reference to the initializer appropriate to the user selected build
+ * options.  Use the selected initializer to construct the internal interface.
+ *
+ * @param[in,out]   HtInterface    Contains pointer to HT Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header
+ *
+*/
+VOID
+NewHtInterface (
+     OUT   HT_INTERFACE         *HtInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) HtInterface,
+    (VOID *) OptionHtConfiguration.HtOptionInternalInterface,
+    (sizeof (HT_INTERFACE)),
+    StdHeader
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * A "constructor" for the HyperTransport external interface.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * Copy the initial default values from the build options tables to the interface struct.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  )
+{
+  LibAmdMemCopy (
+    (VOID *) AmdHtInterface,
+    (VOID *) OptionHtConfiguration.HtOptionPlatformDefaults,
+    (UINT32) (sizeof (AMD_HT_INTERFACE)),
+    StdHeader
+    );
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h
new file mode 100755
index 0000000000..84d1b59987
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterface.h
@@ -0,0 +1,487 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * This file includes the interface access constructor and interface
+ * support which is not removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_H_
+#define _HT_INTERFACE_H_
+
+/**
+ * @page htimplintf HT Internal Interface Implementation Guide
+ *
+ * HT Internal Interface provides access to the HT Component external interface (see AGESA.h),
+ * in a manner that isolates calling code from knowledge about the external interface or which
+ * interfaces are supported in the current build.
+ *
+ * @par Adding a Method to HT Internal Interface
+ *
+ * To add a new method to the HT Internal Interface, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
+ *     but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME  </tt> @n
+ *   </ul>
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtInterfaceInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::HT_INTERFACE struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an HT Internal Interface Instance of the method.
+ *
+ * To implement an instance of a method for a specific interface  follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the method typedef.
+ *
+ * - Name the function MethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtInterfaceMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other Ht internal interface routines or data as part of the method implementation, the function
+ *   must use HtInterface->OtherMethod().  Do not directly access other HT internal interface
+ *   routines, because in the table there may be overrides or this routine may be shared by multiple families.
+ *
+ * - Add the instance to the ::HT_INTERFACE instances.
+ *
+ * - If a configuration does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Invoking HT Internal Interface Methods.
+ *
+ * The first step is carried out only once by the top level HT entry point.
+ * @n @code
+ *   HT_INTERFACE HtInterface;
+ *   // Get the current HT internal interface (to HtBlock data)
+ *   NewHtInterface (&HtInterface);
+ *   State->HtInterface = &HtInterface;
+ * @endcode
+ *
+ * The following example shows how to invoke a HT Internal Interface method.
+ * @n @code
+ *    State->HtInterface->MethodName ();
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     NodeA            One Node on which this Link is located
+ * @param[in]     LinkA            The Link on this Node
+ * @param[in]     NodeB            The other Node on which this Link is located
+ * @param[in]     LinkB            The Link on that Node
+ * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
+ * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap       modify to change the Link's frequency capability
+ * @param[in]     State            the input data
+ *
+ */
+typedef VOID F_GET_CPU_2_CPU_PCB_LIMITS (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_CPU_2_CPU_PCB_LIMITS *PF_GET_CPU_2_CPU_PCB_LIMITS;
+
+/**
+ * Skip reganging of subLinks.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     NodeA    One Node on which this Link is located
+ * @param[in]     LinkA    The Link on this Node
+ * @param[in]     NodeB    The other Node on which this Link is located
+ * @param[in]     LinkB    The Link on that Node
+ * @param[in]     State    the input data
+ *
+ * @retval        MATCHED      leave Link unganged
+ * @retval        POWERED_OFF  leave link unganged and power off the paired sublink
+ * @retval        UNMATCHED    regang Link automatically
+ */
+typedef FINAL_LINK_STATE F_GET_SKIP_REGANG (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_SKIP_REGANG *PF_GET_SKIP_REGANG;
+
+/**
+ * Manually control bus number assignment.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node      The Node on which this chain is located
+ * @param[in]     Link      The Link on the host for this chain
+ * @param[out]    SecBus    Secondary Bus number for this non-coherent chain
+ * @param[out]    SubBus    Subordinate Bus number
+ * @param[in]     State     the input data
+ *
+ * @retval        TRUE      this routine is supplying the bus numbers
+ * @retval        FALSE     use auto Bus numbering
+ */
+typedef BOOLEAN F_GET_OVERRIDE_BUS_NUMBERS (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_OVERRIDE_BUS_NUMBERS *PF_GET_OVERRIDE_BUS_NUMBERS;
+
+/**
+ * Get Manual BUID assignment list.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]    Node    The Node on which this chain is located
+ * @param[in]    Link    The Link on the host for this chain
+ * @param[out]   List    a pointer to a list, if returns TRUE
+ * @param[in]    State   the input data
+ *
+ * @retval      TRUE     use manual List
+ * @retval      FALSE    initialize the Link automatically. List not valid.
+ */
+typedef BOOLEAN F_GET_MANUAL_BUID_SWAP_LIST (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  );
+/// Reference to a method.
+typedef F_GET_MANUAL_BUID_SWAP_LIST *PF_GET_MANUAL_BUID_SWAP_LIST;
+
+/**
+ * Override capabilities of a device.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     HostNode      The Node on which this chain is located
+ * @param[in]     HostLink      The Link on the host for this chain
+ * @param[in]     Depth         The Depth in the I/O chain from the Host
+ * @param[in]     PciAddress    The Device's PCI config address (for callout)
+ * @param[in]     DevVenId      The Device's PCI Vendor + Device ID (offset 0x00)
+ * @param[in]     Revision      The Device's PCI Revision
+ * @param[in]     Link          The Device's Link number (0 or 1)
+ * @param[in,out] LinkWidthIn   modify to change the Link Width In
+ * @param[in,out] LinkWidthOut  modify to change the Link Width Out
+ * @param[in,out] FreqCap       modify to change the Link's frequency capability
+ * @param[in,out] Clumping      modify to change unit id clumping capability
+ * @param[in]     State         the input data
+ *
+ */
+typedef VOID F_GET_DEVICE_CAP_OVERRIDE (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  );
+/// Reference to a method.
+typedef F_GET_DEVICE_CAP_OVERRIDE *PF_GET_DEVICE_CAP_OVERRIDE;
+
+/**
+ * Get limits for non-coherent Links.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     HostNode                   The Node on which this Link is located
+ * @param[in]     HostLink                   The Link about to be initialized
+ * @param[in]     Depth                      The Depth in the I/O chain from the Host
+ * @param[in,out] DownstreamLinkWidthLimit   modify to change the Link Width In
+ * @param[in,out] UpstreamLinkWidthLimit     modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap                 modify to change the Link's frequency capability
+ * @param[in]     State                      the input data
+ */
+typedef VOID F_GET_IO_PCB_LIMITS (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_IO_PCB_LIMITS *PF_GET_IO_PCB_LIMITS;
+
+/**
+ * Get the Socket number for a given Node number.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node    Node discovered event data.
+ * @param[in]     State   reference to Node to socket map
+ *
+ * @return the socket id
+ *
+ */
+typedef UINT8 F_GET_SOCKET_FROM_MAP (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  );
+/// Reference to a method.
+typedef F_GET_SOCKET_FROM_MAP *PF_GET_SOCKET_FROM_MAP;
+
+/**
+ * Ignore a Link.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in]     Node   The Node on which this Link is located
+ * @param[in]     Link   The Link about to be initialized
+ * @param[in]     NbList The northbridge default ignore link list
+ * @param[in]     State   the input data
+ *
+ * @retval        MATCHED     ignore this Link and skip it
+ * @retval        POWERED_OFF ignore this link and power it off.
+ * @retval        UNMATCHED   initialize the Link normally
+ */
+typedef FINAL_LINK_STATE F_GET_IGNORE_LINK (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       IGNORE_LINK  *NbIgnoreLinkList,
+  IN       STATE_DATA   *State
+  );
+/// Reference to a method.
+typedef F_GET_IGNORE_LINK *PF_GET_IGNORE_LINK;
+
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] State Our state
+ */
+typedef VOID F_POST_MAP_TO_AP (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_POST_MAP_TO_AP *PF_POST_MAP_TO_AP;
+
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] State Our state
+ */
+typedef VOID F_CLEAN_MAPS_AFTER_ERROR (
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_CLEAN_MAPS_AFTER_ERROR *PF_CLEAN_MAPS_AFTER_ERROR;
+
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in,out] State global state
+ */
+typedef VOID F_NEW_NODE_AND_SOCKET_TABLES (
+  IN OUT   STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_NEW_NODE_AND_SOCKET_TABLES *PF_NEW_NODE_AND_SOCKET_TABLES;
+
+/**
+ * Fill in the socket's Node id when a processor is discovered in that socket.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in] Node                Node from which a new node was discovered
+ * @param[in] CurrentNodeModule   The current node's module id in it's processor.
+ * @param[in] PackageLink         The package level link from Node to NewNode.
+ * @param[in] NewNode             The new node's id
+ * @param[in] HardwareSocket      If we use the hardware method (preferred), this is the socket of new node.
+ * @param[in] Module              The new node's module id in it's processor.
+ * @param[in] State               our State
+ */
+typedef VOID F_SET_NODE_TO_SOCKET_MAP (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  );
+/// Reference to a method.
+typedef F_SET_NODE_TO_SOCKET_MAP *PF_SET_NODE_TO_SOCKET_MAP;
+
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ * @HtInterfaceInstances.
+ *
+ * @param[in,out]   State    Keep our buffer handle.
+ *
+ */
+typedef VOID F_NEW_HOP_COUNT_TABLE (
+  IN OUT   STATE_DATA     *State
+  );
+/// Reference to a method.
+typedef F_NEW_HOP_COUNT_TABLE *PF_NEW_HOP_COUNT_TABLE;
+
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ * @HtInterfaceInstances.
+ *
+ * Invoke the CPU component power mgt interface.
+ *
+ * @param[in]    StdHeader    Config for library and services.
+ *
+ * @return Frequency in MHz.
+ *
+ */
+typedef UINT32 F_GET_MIN_NB_CORE_FREQ (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+/// Reference to a Method.
+typedef F_GET_MIN_NB_CORE_FREQ *PF_GET_MIN_NB_CORE_FREQ;
+
+/**
+ * The HT Interface, feature code uses these methods to get interface parameters.
+ */
+struct _HT_INTERFACE {
+  PF_GET_CPU_2_CPU_PCB_LIMITS GetCpu2CpuPcbLimits;    /**< Method: Get link limits for coherent links. */
+  PF_GET_SKIP_REGANG GetSkipRegang;                   /**< Method: Skip reganging for coherent links. */
+  PF_NEW_HOP_COUNT_TABLE NewHopCountTable;            /**< Method: Get a new hop count table. */
+  PF_GET_OVERRIDE_BUS_NUMBERS GetOverrideBusNumbers;  /**< Method: Control Bus number assignment. */
+  PF_GET_MANUAL_BUID_SWAP_LIST GetManualBuidSwapList; /**< Method: Assign device IDs. */
+  PF_GET_DEVICE_CAP_OVERRIDE GetDeviceCapOverride;    /**< Method: Override Device capabilities. */
+  PF_GET_IO_PCB_LIMITS GetIoPcbLimits;                /**< Method: Get link limits for noncoherent links. */
+  PF_GET_SOCKET_FROM_MAP GetSocketFromMap;            /**< Method: Get the Socket for a node id. */
+  PF_GET_IGNORE_LINK GetIgnoreLink;                   /**< Method: Ignore a link. */
+  PF_POST_MAP_TO_AP PostMapToAp;                      /**< Method: Post Socket and other info to AP cores. */
+  PF_NEW_NODE_AND_SOCKET_TABLES NewNodeAndSocketTables; /**< Method: Get new socket and node maps. */
+  PF_CLEAN_MAPS_AFTER_ERROR CleanMapsAfterError;       /**< Method: Clean up maps for forced 1P on error fall back. */
+  PF_SET_NODE_TO_SOCKET_MAP SetNodeToSocketMap;       /**< Method: Associate a node id with a socket. */
+  PF_GET_MIN_NB_CORE_FREQ GetMinNbCoreFreq;           /**< Method: Get the minimum northbridge frequency */
+};
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the internal Ht Interface.
+ *
+*/
+VOID
+NewHtInterface (
+     OUT   HT_INTERFACE         *HtInterface,
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#endif  /* _HT_INTERFACE_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
new file mode 100755
index 0000000000..35119addc1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.c
@@ -0,0 +1,260 @@
+/**
+ * @file
+ *
+ * External Interface implementation for coherent features.
+ *
+ * Contains routines for accessing the interface to the client BIOS,
+ * for support only required for coherent features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htInterfaceCoherent.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS}
+ *
+ * For each coherent connection this routine is called once.  Update the frequency
+ * and width if needed for this Link (usually based on board restriction).  This is
+ * used with CPU device capabilities and northbridge limits to compute the default
+ * settings.  The input width and frequency are valid, but do not necessarily reflect
+ * the minimum setting that will be chosen.
+ *
+ * @param[in]     NodeA One Node on which this Link is located
+ * @param[in]     LinkA The Link on this Node
+ * @param[in]     NodeB The other Node on which this Link is located
+ * @param[in]     LinkB The Link on that Node
+ * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
+ * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
+ * @param[in]     State the input data
+ *
+ */
+VOID
+GetCpu2CpuPcbLimits (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  )
+{
+  CPU_TO_CPU_PCB_LIMITS *p;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+
+  ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
+  ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
+
+  SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
+  PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
+  SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
+  PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
+
+  if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) {
+    p = State->HtBlock->CpuToCpuPcbLimitsList;
+
+    while (p->SocketA != HT_LIST_TERMINAL) {
+      if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+           ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
+          ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
+           ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
+        // Found a match, update width and frequency
+        *ABLinkWidthLimit = p->ABLinkWidthLimit;
+        *BALinkWidthLimit = p->BALinkWidthLimit;
+        *PcbFreqCap = p->PcbFreqCap;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Skip reganging of subLinks.
+ *
+ * @HtInterfaceMethod{::F_GET_SKIP_REGANG}
+ *
+ * This routine is called whenever two subLinks are both connected to the same CPUs.
+ * Normally, unganged sublinks between the same two CPUs are reganged.  Return true
+ * from this routine to leave the Links unganged.
+ *
+ * @param[in]     NodeA    One Node on which this Link is located
+ * @param[in]     LinkA    The Link on this Node
+ * @param[in]     NodeB    The other Node on which this Link is located
+ * @param[in]     LinkB    The Link on that Node
+ * @param[in]     State     the input data
+ *
+ * @retval        MATCHED      leave Link unganged
+ * @retval        POWERED_OFF  leave link unganged and power off the paired sublink
+ * @retval        UNMATCHED    regang Link automatically
+ */
+FINAL_LINK_STATE
+GetSkipRegang (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  )
+{
+  SKIP_REGANG *p;
+  FINAL_LINK_STATE Result;
+  UINT8 SocketA;
+  UINT8 SocketB;
+  UINT8 PackageLinkA;
+  UINT8 PackageLinkB;
+
+  ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
+  ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
+
+  Result = UNMATCHED;
+  SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
+  PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
+  SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
+  PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
+
+  if (State->HtBlock->SkipRegangList != NULL) {
+    p = State->HtBlock->SkipRegangList;
+
+    while (p->SocketA != HT_LIST_TERMINAL) {
+      if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
+            ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
+          ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
+          ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
+            ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
+        // Found a match return final link state
+        Result = p->LinkState;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE}
+ *
+ * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a
+ * known signature.
+ *
+ * @param[in,out]   State    Keep our buffer handle.
+ *
+ */
+VOID
+NewHopCountTable (
+  IN OUT   STATE_DATA     *State
+  )
+{
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE);
+  AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr;
+  } else {
+    State->HopCountTable = NULL;
+  }
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.h
new file mode 100755
index 0000000000..3e3875bba7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceCoherent.h
@@ -0,0 +1,114 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface for coherent features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_COHERENT_H_
+#define _HT_INTERFACE_COHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Get limits for CPU to CPU Links.
+ *
+ */
+VOID
+GetCpu2CpuPcbLimits (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN OUT   UINT8        *ABLinkWidthLimit,
+  IN OUT   UINT8        *BALinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Skip reganging of subLinks.
+ *
+ */
+FINAL_LINK_STATE
+GetSkipRegang (
+  IN       UINT8        NodeA,
+  IN       UINT8        LinkA,
+  IN       UINT8        NodeB,
+  IN       UINT8        LinkB,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get a new, empty Hop Count Table, to make one for the installed topology.
+ *
+ */
+VOID
+NewHopCountTable (
+  IN OUT   STATE_DATA     *State
+  );
+
+#endif  /* _HT_INTERFACE_COHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
new file mode 100755
index 0000000000..3da3550828
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.c
@@ -0,0 +1,529 @@
+/**
+ * @file
+ *
+ * External Interface implementation, general purpose features.
+ *
+ * Contains routines for implementing the interface to the client BIOS.  This file
+ * includes the interface support which is not removed with various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionMultiSocket.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceGeneral.h"
+#include "htNb.h"
+#include "cpuServices.h"
+#include "cpuFeatures.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACEGENERAL_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is PackageLink an Internal Link?
+ *
+ * This is a test for the logical link match codes in the user interface, not a test for
+ * the actual northbridge links.
+ *
+ * @param[in]    PackageLink   The link
+ *
+ * @retval       TRUE          This is an internal link
+ * @retval       FALSE         This is not an internal link
+ */
+BOOLEAN
+IsPackageLinkInternal (
+  IN       UINT8  PackageLink
+  )
+{
+  return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Ignore a Link.
+ *
+ * @HtInterfaceMethod{::F_GET_IGNORE_LINK}
+ *
+ * This routine is called every time a coherent Link is found and then every time a
+ * non-coherent Link from a CPU is found.  Any coherent or non-coherent Link from a
+ * CPU can be ignored and not used for discovery or initialization.  Useful for
+ * connection based systems.
+ *
+ * @note not called for IO device to IO Device Links.
+ *
+ * @param[in]     Node             The Node on which this Link is located
+ * @param[in]     Link             The Link about to be initialized
+ * @param[in]     NbIgnoreLinkList The northbridge default ignore link list
+ * @param[in]     State            the input data
+ *
+ * @retval        MATCHED     ignore this Link and skip it
+ * @retval        POWERED_OFF ignore this link and power it off.
+ * @retval        UNMATCHED   initialize the Link normally
+ */
+FINAL_LINK_STATE
+GetIgnoreLink (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+  IN       IGNORE_LINK     *NbIgnoreLinkList,
+  IN       STATE_DATA      *State
+  )
+{
+  IGNORE_LINK *p;
+  FINAL_LINK_STATE Result;
+  BOOLEAN IsFound;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  Result = UNMATCHED;
+  IsFound = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->IgnoreLinkList != NULL) {
+    p = State->HtBlock->IgnoreLinkList;
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
+        // Found a match return the desired link state.
+        ASSERT (Result < MaxFinalLinkState);
+        Result = p->LinkState;
+        IsFound = TRUE;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // If there wasn't a match in the user interface, see if the northbridge provides one.
+  if (!IsFound && (NbIgnoreLinkList != NULL)) {
+    p = NbIgnoreLinkList;
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) ||
+           ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
+           ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
+        // Found a match return the desired link state.
+        ASSERT (Result < MaxFinalLinkState);
+        Result = p->LinkState;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the Socket number for a given Node number.
+ *
+ * @HtInterfaceMethod{::F_GET_SOCKET_FROM_MAP}
+ *
+ * Return the id.
+ *
+ * @param[in]     Node    The Node to translate
+ * @param[in]     State   reference to Node to socket map
+ *
+ * @return the socket id
+ *
+ */
+UINT8
+GetSocketFromMap (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  )
+{
+  UINT8 Socket;
+
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  Socket = (*State->NodeToSocketDieMap)[Node].Socket;
+  return Socket;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ * @HtInterfaceMethod{::F_NEW_NODE_AND_SOCKET_TABLES}
+ *
+ * Put the Socket Die Table in heap with a known handle.  Content will be generated as
+ * each node is discovered.
+ *
+ * @param[in,out] State global state
+ */
+VOID
+NewNodeAndSocketTables (
+  IN OUT   STATE_DATA *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  // Allocate heap for the table
+  State->SocketDieToNodeMap = NULL;
+  AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM));
+  AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr;
+    // Initialize shared data structures
+    for (i = 0; i < MAX_SOCKETS; i++) {
+      for (j = 0; j < MAX_DIES; j++) {
+        (*State->SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Allocate heap for the table
+  State->NodeToSocketDieMap = NULL;
+  AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM));
+  AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE;
+  AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
+  if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
+    State->NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr;
+    // Initialize shared data structures
+    for (i = 0; i < MAX_NODES; i++) {
+      (*State->NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL;
+      (*State->NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ * @HtInterfaceMethod{::F_GET_MIN_NB_CORE_FREQ}
+ *
+ * Invoke the CPU component power mgt interface.
+ *
+ * @param[in]    StdHeader    Config for library and services.
+ *
+ * @return Frequency in MHz.
+ *
+ */
+UINT32
+GetMinNbCoreFreq (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  )
+{
+  BOOLEAN Temp;
+  UINT32 Result;
+
+  OptionMultiSocketConfiguration.GetSystemNbCof (&Result, &Temp, StdHeader);
+  return Result;
+}
+
+/**
+ * @page physicalsockethowto Physical Socket Map, How To Create
+ *
+ *  To create a physical system socket map for a platform:
+ *
+ *  - Start at the Node which will be the BSP.
+ *
+ *  - Begin a breadth first enumeration of all the coherent Links between sockets
+ *  by creating a socket structure for each socket connection from the BSP.
+ *  For example, if the BSP is in socket zero and Link one connects to socket two,
+ *  create socket {0, 1, 2}.
+ *
+ *  - When all Links from the BSP are described, go to the first socket connected
+ *  to the BSP and continue the breadth first enumeration.
+ *
+ *  - It should not be necessary to describe the back Links; in the example above, there
+ *  should be no need to create {2, 1, 0} (assuming socket two connects back to
+ *  socket zero on its Link one).
+ *
+ *  - When completed:
+ *
+ *     - Every socket except the BSP's (usually zero) must be listed as a targetSocket,
+ *     at least once.  Some sockets may be listed more than once.
+ *
+ *     - There usually should be at least as many entries as Links. An exception is a
+ *     fully connected system, only the Links from the BSP are needed.
+ *
+ *     - Every socket but the last one in the breadth first order should usually have one
+ *     or more entries listing it as a currentSocket. (The last one has only back Links.)
+ *
+ *  There are no strict assumptions about the ordering of the socket structures.
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update maps between Sockets and Nodes for a specific newly discovered node.
+ *
+ * @HtInterfaceMethod{::F_SET_NODE_TO_SOCKET_MAP}
+ *
+ * There are two methods for providing socket naming of nodes.
+ *
+ * Hardware Method (preferred):  A value strapped in hardware by the board is read and
+ * passed to this routine.
+ *
+ * Software Method:  The current node's socket is looked up, since it was
+ * previously a new node and went through this process. The link is converted to
+ * a package level link.  A user data structure describing the package level
+ * layout of the system is searched for the current node's socket and package link,
+ * and now we know the new node's socket.
+ *
+ * In either case, the Socket, Module to Node map and the Node to Socket, Module
+ * map are updated with the new node, socket, and module.
+ *
+ * Data needed to do this is passed in to the routine as arguments rather than read by this routine,
+ * so that it is not necessary to know a valid temporary route to either node at the time this code runs.
+ *
+ * @param[in] Node           Node from which a new node was discovered
+ * @param[in] CurrentNodeModule  The current node's module id in it's processor.
+ * @param[in] PackageLink    The package link for the current node's link.
+ * @param[in] NewNode        The new node's id
+ * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node.
+ * @param[in] Module         The new node's module id in it's processor.
+ * @param[in] State          our State
+ */
+VOID
+SetNodeToSocketMap (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 SourceSocket;
+  UINT8 TargetSocket;
+  SYSTEM_PHYSICAL_SOCKET_MAP *Map;
+
+  // While this code could be written to recover from a NULL socket map, AGESA cannot function without one.
+  ASSERT (State->SocketDieToNodeMap != NULL);
+
+  if (State->HtBlock->SystemPhysicalSocketMap != NULL) {
+    if (NewNode != 0) {
+      // Find the logical Node from which a new Node was discovered in the Node field of
+      // some socket.  It must already be there, Nodes are assigned ascending.
+      //
+      for (SourceSocket = 0; SourceSocket < MAX_SOCKETS; SourceSocket++) {
+        if ((*State->SocketDieToNodeMap)[SourceSocket][CurrentNodeModule].Node == Node) {
+          break;
+        }
+      }
+      // This ASSERT should be understood as "the Node did not have a match", not as a limit check on SourceSocket.
+      ASSERT (SourceSocket != MAX_SOCKETS);
+
+      // Find the sourceSocket in the CurrentSocket field, for the Link on which a new Node
+      // was discovered.  When we find an entry with that socket and Link number, update the
+      // Node for that socket.
+      //
+      if (IsPackageLinkInternal (PackageLink)) {
+        // Internal Nodes are in the same socket, don't search the physical system map.
+        TargetSocket = SourceSocket;
+      } else {
+        // Find the target socket in the physical system map.
+        Map = State->HtBlock->SystemPhysicalSocketMap;
+        while ((Map->CurrentSocket != 0xFF) &&
+               ((Map->CurrentSocket != SourceSocket) || (Map->CurrentLink != PackageLink))) {
+          Map++;
+        }
+        ASSERT (Map->CurrentSocket != 0xFF);
+        TargetSocket = Map->TargetSocket;
+      }
+    } else {
+      // The BSP (BSN, if you will) has no predecessor node from which it is discovered.
+      TargetSocket = 0;
+    }
+  } else {
+    // Use the hardware method
+    // The hardware strapped socket id is passed to us in this case.
+    TargetSocket = HardwareSocket;
+  }
+  // If the target socket, module is already mapped to something, that's not good.  Socket labeling conflict.
+    // Check that the board is strapped correctly. If not you need a SystemPhysicalSocketMap.  If you have one,
+    // check it for correctness.
+  ASSERT ((*State->SocketDieToNodeMap)[TargetSocket][Module].Node == 0xFF);
+  // Update the map for the rest of agesa
+  (*State->SocketDieToNodeMap)[TargetSocket][Module].Node = NewNode;
+  // and the node to socket map
+  ASSERT (State->NodeToSocketDieMap != NULL);
+  (*State->NodeToSocketDieMap)[NewNode].Socket = TargetSocket;
+  (*State->NodeToSocketDieMap)[NewNode].Die = Module;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ * @HtInterfaceMethod{::F_CLEAN_MAPS_AFTER_ERROR}
+ *
+ * @param[in] State Our state, access to socket, node maps
+ *
+ */
+VOID
+CleanMapsAfterError (
+  IN       STATE_DATA *State
+  )
+{
+  UINTN  Socket;
+  UINTN  Module;
+  UINTN  Node;
+
+  ASSERT (State->NodeToSocketDieMap != NULL);
+  ASSERT (State->SocketDieToNodeMap != NULL);
+
+  // Clear all the socket, module items except for the socket and module containing node zero.
+  for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
+    for (Module = 0; Module < MAX_DIES; Module++) {
+      if (((*State->NodeToSocketDieMap)[0].Socket != Socket) || ((*State->NodeToSocketDieMap)[0].Die != Module)) {
+        (*State->SocketDieToNodeMap)[Socket][Module].Node = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[Socket][Module].LowCore = HT_LIST_TERMINAL;
+        (*State->SocketDieToNodeMap)[Socket][Module].HighCore = HT_LIST_TERMINAL;
+      }
+    }
+  }
+  // Clear all the node items except for node zero.
+  for (Node = 1; Node < MAX_NODES; Node++) {
+    (*State->NodeToSocketDieMap)[Node].Socket = HT_LIST_TERMINAL;
+    (*State->NodeToSocketDieMap)[Node].Die = HT_LIST_TERMINAL;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ * @HtInterfaceMethod{::F_POST_MAP_TO_AP}
+ *
+ * Since Ap's can not view map until after mp communication is established,
+ * provide them with initial context info via a mailbox register. A mailbox
+ * register is one that can be written in PCI space and read in MSR space.
+ *
+ * @param[in] State Our state, access to socket, node maps
+ */
+VOID
+PostMapToAp (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 ModuleType;
+  UINT8 Module;
+  AP_MAILBOXES ApMailboxes;
+  UINT8 Node;
+  UINT32 Degree;
+  AGESA_STATUS CalledStatus;
+
+  // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed.
+  CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle);
+
+  ASSERT (State->Fabric != NULL);
+  Degree = 0;
+  // Compute the degree of the system by finding the maximum degree of any node.
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    if (State->Fabric->SysDegree[Node] > Degree) {
+      Degree = State->Fabric->SysDegree[Node];
+    }
+  }
+  // Post the information on all nodes.
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    ModuleType = 0;
+    Module = 0;
+    State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb);
+    ApMailboxes.ApMailInfo.Info = 0;
+    ApMailboxes.ApMailInfo.Fields.Node = Node;
+    ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State);
+    ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType;
+    ApMailboxes.ApMailInfo.Fields.Module = Module;
+    ApMailboxes.ApMailExtInfo.Info = 0;
+    ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree;
+    // other fields of the extended info are used during ap init, and will be initialized at that time.
+    State->Nb->PostMailbox (Node, ApMailboxes, State->Nb);
+  }
+  // Now that the mailboxes have been initialized, cache the info on the BSC.  The APs
+  // will cache during heap initialization.
+  CacheApMailbox (State->ConfigHandle);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.h
new file mode 100755
index 0000000000..f13dc545ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceGeneral.h
@@ -0,0 +1,160 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface, general purpose features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * external interface.
+ *
+ * This file includes the interface support which is not removed with
+ * various build options.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_GENERAL_H_
+#define _HT_INTERFACE_GENERAL_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Is PackageLink an Internal Link?
+ */
+BOOLEAN
+IsPackageLinkInternal (
+  IN       UINT8  PackageLink
+  );
+
+/**
+ * Get the Socket number for a given Node number.
+ *
+ */
+UINT8
+GetSocketFromMap (
+  IN       UINT8         Node,
+  IN       STATE_DATA    *State
+  );
+
+/**
+ * Ignore a Link.
+ *
+ */
+FINAL_LINK_STATE
+GetIgnoreLink (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       IGNORE_LINK  *NbIgnoreLinkList,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get a new Socket Die to Node Map.
+ *
+ */
+VOID
+NewNodeAndSocketTables (
+  IN OUT   STATE_DATA *State
+  );
+
+/**
+ * Get the minimum Northbridge frequency for the system.
+ *
+ */
+UINT32
+GetMinNbCoreFreq (
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+/**
+ * Fill in the socket's Node id when a processor is discovered in that socket.
+ *
+ */
+VOID
+SetNodeToSocketMap (
+  IN       UINT8 Node,
+  IN       UINT8 CurrentNodeModule,
+  IN       UINT8 PackageLink,
+  IN       UINT8 NewNode,
+  IN       UINT8 HardwareSocket,
+  IN       UINT8 Module,
+  IN       STATE_DATA *State
+  );
+
+/**
+ * Clean up the map structures after severe event has caused a fall back to 1 node.
+ *
+ */
+VOID
+CleanMapsAfterError (
+  IN       STATE_DATA *State
+  );
+
+/**
+ * Post Node id and other context info to AP cores via mailbox.
+ *
+ */
+VOID
+PostMapToAp (
+  IN       STATE_DATA *State
+  );
+
+#endif  /* _HT_INTERFACE_GENERAL_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
new file mode 100755
index 0000000000..07909bef8b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.c
@@ -0,0 +1,390 @@
+/**
+ * @file
+ *
+ * External Interface implementation for non-coherent features.
+ *
+ * Contains routines for accessing the interface to the client BIOS,
+ * for non-coherent features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htInterfaceNonCoherent.h"
+#include "htNb.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTINTERFACENONCOHERENT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+#define UNUSED_ZERO_32 ((UINT32)0)
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Manual BUID assignment list.
+ *
+ * @HtInterfaceMethod{::F_GET_MANUAL_BUID_SWAP_LIST}
+ *
+ * This routine is called every time a non-coherent chain is processed.  BUID
+ * assignment may be controlled explicitly on a non-coherent chain. Swaps controls
+ * the BUID assignment and FinalIds provides the device to device Linking.  Device
+ * orientation can be detected automatically, or explicitly.  See documentation for
+ * more details.
+ *
+ * If a manual swap list is not supplied, automatic non-coherent init assigns BUIDs
+ * starting at 1 and incrementing sequentially based on each device's unit count.
+ *
+ * @param[in]    Node    The Node on which this chain is located
+ * @param[in]    Link    The Link on the host for this chain
+ * @param[out]   List    supply a pointer to a list.
+ *                       List is NOT valid unless routine returns TRUE.
+ * @param[in]    State   the input data
+ *
+ * @retval      TRUE     use a manual list
+ * @retval      FALSE    initialize the Link automatically
+ */
+BOOLEAN
+GetManualBuidSwapList (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  )
+{
+  MANUAL_BUID_SWAP_LIST *p;
+  BOOLEAN result;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (List != NULL));
+
+  result = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->ManualBuidSwapList != NULL) {
+    p = State->HtBlock->ManualBuidSwapList;
+
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
+        // Found a match implies TRUE, ignore the Link
+        result = TRUE;
+        *List = &(p->SwapList);
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // List is not valid if Result is FALSE.
+  return result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Override capabilities of a device.
+ *
+ * @HtInterfaceMethod{::F_GET_DEVICE_CAP_OVERRIDE}
+ *
+ * This routine is called once for every Link on every IO device.  Update the width
+ * and frequency capability if needed for this device.  This is used along with
+ * device capabilities, the limit call backs, and northbridge limits to compute the
+ * default settings.  The components of the device's PCI config address are provided,
+ * so its settings can be consulted if need be. The input width and frequency are the
+ * reported device capabilities.
+ *
+ * @param[in]     HostNode      The Node on which this chain is located
+ * @param[in]     HostLink      The Link on the host for this chain
+ * @param[in]     Depth         The Depth in the I/O chain from the Host
+ * @param[in]     PciAddress    The Device's PCI config address (for callout)
+ * @param[in]     DevVenId      The Device's PCI Vendor + Device ID (offset 0x00)
+ * @param[in]     Revision      The Device's PCI Revision
+ * @param[in]     Link          The Device's Link number (0 or 1)
+ * @param[in,out] LinkWidthIn   modify to change the Link Width In
+ * @param[in,out] LinkWidthOut  modify to change the Link Width Out
+ * @param[in,out] FreqCap       modify to change the Link's frequency capability
+ * @param[in,out] Clumping      modify to change unit id clumping capability
+ * @param[in]     State         the input data and config header
+ *
+ */
+VOID
+GetDeviceCapOverride (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  )
+{
+  DEVICE_CAP_OVERRIDE *p;
+  UINT8 HostSocket;
+  UINT8 PackageLink;
+  DEVICE_CAP_CALLOUT_PARAMS CalloutParams;
+  AGESA_STATUS CalloutStatus;
+
+  ASSERT ((HostNode < MAX_NODES) && (Depth < 32) && ((Link == 0) || (Link == 1)));
+
+  HostSocket = State->HtInterface->GetSocketFromMap (HostNode, State);
+  PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
+
+  if (State->HtBlock->DeviceCapOverrideList != NULL) {
+    p = State->HtBlock->DeviceCapOverrideList;
+
+    while (p->HostSocket != HT_LIST_TERMINAL) {
+      if (((p->HostSocket == HostSocket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
+          ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
+          ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == Link) || (p->Link == HT_LIST_MATCH_ANY)) &&
+          // Found a potential match. Check the additional optional matches.
+          ((p->Options.IsCheckDevVenId == 0) || (p->DevVenId == DevVenId)) &&
+          ((p->Options.IsCheckRevision == 0) || (p->Revision == Revision))) {
+        //
+        // Found a match.  Check what override actions are desired.
+        // Unlike the PCB limit routines, which handle the info returned,
+        // deviceCapOverride is actually overriding the settings, so we need
+        // to check that the field actually has an update.
+        // The Callout is a catch all for situations the data is not up to handling.
+        // It is expected, but not enforced, that either the data overrides are used,
+        // or the callout is used, rather than both.
+        //
+        if (p->Options.IsOverrideWidthIn != 0) {
+          *LinkWidthIn = p->LinkWidthIn;
+        }
+        if (p->Options.IsOverrideWidthOut != 0) {
+          *LinkWidthOut = p->LinkWidthOut;
+        }
+        if (p->Options.IsOverrideFreq != 0) {
+          *FreqCap = p->FreqCap;
+        }
+        if (p->Options.IsOverrideClumping != 0) {
+          *Clumping = p->Clumping;
+        }
+        if (p->Options.IsDoCallout != 0) {
+          //
+          // Pass the actual info being matched, not the matched struct data.
+          // This callout is expected to be built in as part of the options file, and does not use the
+          // callout interface, even though we use the consistent interface declaration for the routine.
+          // So, the first two int parameters have no meaning in this case.
+          // It is not meaningful for the callout to have any status but Success.
+          //
+          CalloutParams.HostSocket = HostSocket;
+          CalloutParams.HostLink = PackageLink;
+          CalloutParams.Depth = Depth;
+          CalloutParams.DevVenId = DevVenId;
+          CalloutParams.Revision = Revision;
+          CalloutParams.Link = Link;
+          CalloutParams.PciAddress = PciAddress;
+          CalloutParams.LinkWidthIn = LinkWidthIn;
+          CalloutParams.LinkWidthOut = LinkWidthOut;
+          CalloutParams.FreqCap = FreqCap;
+          CalloutParams.Clumping = Clumping;
+          CalloutParams.StdHeader = *((AMD_CONFIG_PARAMS *) (State->ConfigHandle));
+          CalloutStatus = p->Callout (UNUSED_ZERO_32, UNUSED_ZERO_32, (VOID *) &CalloutParams);
+          ASSERT (CalloutStatus == AGESA_SUCCESS);
+        }
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get limits for non-coherent Links.
+ *
+ * @HtInterfaceMethod{::F_GET_IO_PCB_LIMITS}
+ *
+ * For each non-coherent connection this routine is called once.  Update the
+ * frequency and width if needed for this Link (usually based on board restriction).
+ * This is used with device capabilities, device overrides, and northbridge limits to
+ * compute the default settings. The input width and frequency are valid, but do not
+ * necessarily reflect the minimum setting that will be chosen.
+ *
+ * @param[in]     HostNode                   The Node on which this Link is located
+ * @param[in]     HostLink                   The Link about to be initialized
+ * @param[in]     Depth                      The Depth in the I/O chain from the Host
+ * @param[in,out] DownstreamLinkWidthLimit   modify to change the Link Width In
+ * @param[in,out] UpstreamLinkWidthLimit     modify to change the Link Width Out
+ * @param[in,out] PcbFreqCap                 modify to change the Link's frequency capability
+ * @param[in]     State                      the input data
+ */
+VOID
+GetIoPcbLimits (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  )
+{
+  IO_PCB_LIMITS *p;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((HostNode < MAX_NODES) && (HostLink < MAX_NODES));
+
+  Socket = State->HtInterface->GetSocketFromMap (HostNode, State);
+  PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
+
+  if (State->HtBlock->IoPcbLimitsList != NULL) {
+    p = State->HtBlock->IoPcbLimitsList;
+
+    while (p->HostSocket != HT_LIST_TERMINAL) {
+      if (((p->HostSocket == Socket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
+          ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
+          ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY))) {
+        // Found a match, return the override info
+        *DownstreamLinkWidthLimit = p->DownstreamLinkWidthLimit;
+        *UpstreamLinkWidthLimit = p->UpstreamLinkWidthLimit;
+        *PcbFreqCap = p->PcbFreqCap;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Manually control bus number assignment.
+ *
+ * @HtInterfaceMethod{::F_GET_OVERRIDE_BUS_NUMBERS}
+ *
+ * This routine is called every time a non-coherent chain is processed.  If a system
+ * can not use the auto Bus numbering feature for non-coherent chain bus assignments,
+ * this routine can provide explicit control.  For each chain, provide the bus number
+ * range to use.
+ *
+ * The outputs SecBus and SubBus are not valid unless this routine returns TRUE
+ *
+ * @param[in]     Node      The Node on which this chain is located
+ * @param[in]     Link      The Link on the host for this chain
+ * @param[out]    SecBus    Secondary Bus number for this non-coherent chain
+ * @param[out]    SubBus    Subordinate Bus number
+ * @param[in]     State     the input data
+ *
+ * @retval        TRUE      this routine is supplying the bus numbers.
+ * @retval        FALSE     use auto Bus numbering, bus outputs not valid.
+ */
+BOOLEAN
+GetOverrideBusNumbers (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  )
+{
+  OVERRIDE_BUS_NUMBERS *p;
+  BOOLEAN result;
+  UINT8 Socket;
+  UINT8 PackageLink;
+
+  ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
+
+  result = FALSE;
+  Socket = State->HtInterface->GetSocketFromMap (Node, State);
+  PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
+
+  if (State->HtBlock->OverrideBusNumbersList != NULL) {
+    p = State->HtBlock->OverrideBusNumbersList;
+
+    while (p->Socket != HT_LIST_TERMINAL) {
+      if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
+          ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
+        // Found a match, return the bus overrides
+        *SecBus = p->SecBus;
+        *SubBus = p->SubBus;
+        ASSERT (*SubBus > *SecBus);
+        result = TRUE;
+        break;
+      } else {
+        p++;
+      }
+    }
+  }
+  // SecBus, SubBus are not valid if Result is FALSE.
+  return result;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h
new file mode 100755
index 0000000000..822f4c56ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htInterfaceNonCoherent.h
@@ -0,0 +1,137 @@
+/**
+ * @file
+ *
+ * Internal access to HT Interface, for non-coherent features.
+ *
+ * This file provides definitions used by HT internal modules.  The
+ * external HT interface (in agesa.h) is accessed using these methods.
+ * This keeps the HT Feature implementations abstracted from the HT
+ * interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_INTERFACE_NONCOHERENT_H_
+#define _HT_INTERFACE_NONCOHERENT_H_
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                         Prototypes to Interface from Feature Code
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * Manually control bus number assignment.
+ *
+ */
+BOOLEAN
+GetOverrideBusNumbers (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+     OUT   UINT8        *SecBus,
+     OUT   UINT8        *SubBus,
+  IN       STATE_DATA   *State
+  );
+
+/**
+ * Get Manual BUID assignment list.
+ *
+ */
+BOOLEAN
+GetManualBuidSwapList (
+  IN       UINT8            Node,
+  IN       UINT8            Link,
+     OUT   BUID_SWAP_LIST   **List,
+  IN       STATE_DATA       *State
+  );
+
+/**
+ * Override capabilities of a device.
+ *
+ */
+
+VOID
+GetDeviceCapOverride (
+  IN       UINT8       HostNode,
+  IN       UINT8       HostLink,
+  IN       UINT8       Depth,
+  IN       PCI_ADDR    PciAddress,
+  IN       UINT32      DevVenId,
+  IN       UINT8       Revision,
+  IN       UINT8       Link,
+  IN OUT   UINT8       *LinkWidthIn,
+  IN OUT   UINT8       *LinkWidthOut,
+  IN OUT   UINT32      *FreqCap,
+  IN OUT   UINT32      *Clumping,
+  IN       STATE_DATA  *State
+  );
+
+/**
+ * Get limits for non-coherent Links.
+ *
+ */
+VOID
+GetIoPcbLimits (
+  IN       UINT8        HostNode,
+  IN       UINT8        HostLink,
+  IN       UINT8        Depth,
+  IN OUT   UINT8        *DownstreamLinkWidthLimit,
+  IN OUT   UINT8        *UpstreamLinkWidthLimit,
+  IN OUT   UINT32       *PcbFreqCap,
+  IN       STATE_DATA   *State
+  );
+
+#endif  /* _HT_INTERFACE_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
new file mode 100755
index 0000000000..47aff2084f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htMain.c
@@ -0,0 +1,536 @@
+/**
+ * @file
+ *
+ * HyperTransport features and sequence implementation.
+ *
+ * Implements the external AmdHtInitialize entry point.
+ * Contains routines for directing the sequence of available features.
+ * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
+ * contained in this file, and not in the feature code.
+ *
+ * From a build option perspective, it may be that a few lines could be removed
+ * from compilation in this file for certain options.  It is considered that
+ * the code savings from this are too small to be of concern and this file
+ * should not have any explicit build option implementation.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "AdvancedApi.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "heapManager.h"
+#include "cpuServices.h"
+#include "OptionsHt.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTMAIN_FILECODE
+#define APIC_Base_BSP    8
+#define APIC_Base        0x1b
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update maps with the core range for each module.
+ *
+ * Cores are numbered relative to a Processor, but sometimes there is a need to know the
+ * starting and ending core ids on a particular node.  This same info is also useful for
+ * supporting the Core count on a node other than the one currently executing.
+ *
+ * For each Processor, get the core count of each node using the family specific PCI core count
+ * interface. The order of cores in a processor, and whether it is special for the BSP is family
+ * specific.  But whether the processor orders core ids by module or node, iterate in the right
+ * order and use the counts to determine each start and end range.
+ *
+ * @param[in]   State    number of Nodes discovered.
+*/
+VOID
+STATIC
+UpdateCoreRanges (
+  IN       STATE_DATA    *State
+    )
+{
+  UINT8 Node;
+  UINT8 ProcessorCores;
+  UINT8 ModuleCoreCount[MAX_DIES];
+  UINT8 Socket;
+  UINT8 Module;
+
+  ASSERT (State->SocketDieToNodeMap != NULL);
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
+    // Is a Processor present in Socket?
+    if ((*State->SocketDieToNodeMap)[Socket][0].Node != HT_LIST_TERMINAL) {
+      // Get all the Module core counts for this processor
+      // Note that the core counts are 1 based counts.
+      for (Module = 0; Module < MAX_DIES; Module++) {
+        if ((*State->SocketDieToNodeMap)[Socket][Module].Node != HT_LIST_TERMINAL) {
+          ModuleCoreCount[Module] = State->Nb->GetNumCoresOnNode ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
+        } else {
+          ModuleCoreCount[Module] = 0;
+        }
+      }
+      // Determine the core ordering rule for this processor.
+      if ((((*State->NodeToSocketDieMap)[0].Socket == Socket) && State->Nb->IsOrderBSPCoresByNode) ||
+          (!State->Nb->IsOrderCoresByModule)) {
+        // Order core ranges on this processor by Node Id.
+        ProcessorCores = 0;
+        for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
+          // Is this node a module in this processor?
+          if ((*State->NodeToSocketDieMap)[Node].Socket == Socket) {
+            Module = (*State->NodeToSocketDieMap)[Node].Die;
+            if (ModuleCoreCount[Module] != 0) {
+              (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
+              (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
+              ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
+            }
+          }
+        }
+      } else {
+        // Order core ranges in this processor by Module Id.
+        ProcessorCores = 0;
+        for (Module = 0; Module < MAX_DIES; Module++) {
+          if (ModuleCoreCount[Module] != 0) {
+            (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
+            (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
+            ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
+          }
+        }
+      }
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Complete the coherent init with any system level initialization.
+ *
+ * Find the total number of cores and update the number of Nodes and cores in all cpus.
+ * Limit cpu config access to installed cpus.
+ *
+ * @param[in]   State    number of Nodes discovered.
+*/
+VOID
+STATIC
+FinalizeCoherentInit (
+  IN       STATE_DATA    *State
+    )
+{
+  UINT8 Node;
+  UINT8 TotalCores;
+
+  TotalCores = 0;
+
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    TotalCores = TotalCores + State->Nb->GetNumCoresOnNode (Node, State->Nb);
+  }
+
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->SetTotalNodesAndCores (Node, State->NodesDiscovered + 1, TotalCores, State->Nb);
+  }
+
+  // Set all nodes to limit config space based on node count, after all nodes have a valid count.
+  // (just being cautious, probably we could combine the loops.)
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->LimitNodes (Node, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the coherent fabric.
+ *
+ * Perform discovery and initialization of the coherent fabric, for builds including
+ * support for multiple coherent nodes.
+ *
+ * @param[in]   State   global state
+ */
+VOID
+STATIC
+CoherentInit (
+  IN OUT   STATE_DATA    *State
+  )
+{
+  UINT8 i;
+  UINT8 j;
+  UINT8 ModuleType;
+  UINT8 Module;
+  UINT8 HardwareSocket;
+  COHERENT_FABRIC Fabric;
+
+  // Because Node 0, the BSP, is not discovered, initialize info about it specially here.
+  // Allocate Socket Die Map.
+  // While the BSP is always capable of being the only processor in the system, call the
+  // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system
+  // capability. We don't care to check the return value.
+  //
+  State->Fabric = &Fabric;
+  State->NodesDiscovered = 0;
+  State->TotalLinks = 0;
+  State->SysMpCap = MAX_NODES;
+  State->Nb->IsExceededCapable (0, State, State->Nb);
+  HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
+  ModuleType = 0;
+  Module = 0;
+  State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb);
+  // No predecessor info for BSP, so pass 0xFF for those parameters.
+  State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State);
+
+  // Initialize system state data structures
+  for (i = 0; i < MAX_NODES; i++) {
+    State->Fabric->SysDegree[i] = 0;
+    for (j = 0; j < MAX_NODES; j++) {
+      State->Fabric->SysMatrix[i][j] = 0;
+    }
+  }
+
+  //
+  // Call the coherent init features
+  //
+
+  // Discovery
+  State->HtFeatures->CoherentDiscovery (State);
+  State->HtInterface->PostMapToAp (State);
+  // Topology matching and Routing
+  AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle);
+  State->HtFeatures->LookupComputeAndLoadRoutingTables (State);
+  State->HtFeatures->MakeHopCountTable (State);
+
+  // UpdateCoreRanges requires the other maps to be initialized, and the node count set.
+  FinalizeCoherentInit (State);
+  UpdateCoreRanges (State);
+  State->Fabric = NULL;
+}
+
+/***************************************************************************
+ ***                       Non-coherent init code                        ***
+ ***                             Algorithms                              ***
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the non-coherent fabric.
+ *
+ * Begin with the Compat Link on the BSP, then find and initialize all other
+ * non-coherent chains.
+ *
+ * @param[in]   State    our global state
+ */
+VOID
+STATIC
+NcInit (
+  IN       STATE_DATA    *State
+  )
+{
+  UINT8 Node;
+  UINT8 Link;
+  UINT8 CompatLink;
+  FINAL_LINK_STATE FinalLinkState;
+
+  // Initialize the southbridge chain.
+  State->AutoBusCurrent = State->HtBlock->AutoBusStart;
+  State->UsedCfgMapEntries = 0;
+  CompatLink = State->Nb->ReadSouthbridgeLink (State->Nb);
+  State->HtFeatures->ProcessLink (0, CompatLink, TRUE, State);
+
+  // Find and initialize all other non-coherent chains.
+  for (Node = 0; Node <= State->NodesDiscovered; Node++) {
+    for (Link = 0; Link < State->Nb->MaxLinks; Link++) {
+      // Skip the Link, if any of these tests indicate
+      FinalLinkState = State->HtInterface->GetIgnoreLink (Node, Link, State->Nb->DefaultIgnoreLinkList, State);
+      if (FinalLinkState == UNMATCHED) {
+        if ( !((Node == 0) && (Link == CompatLink))) {
+          if ( !(State->Nb->ReadTrueLinkFailStatus (Node, Link, State, State->Nb))) {
+            if (State->Nb->VerifyLinkIsNonCoherent (Node, Link, State->Nb)) {
+              State->HtFeatures->ProcessLink (Node, Link, FALSE, State);
+            }
+          }
+        }
+      }
+    }
+  }
+}
+
+/***************************************************************************
+ ***                            Link Optimization                        ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Optimize Link Features.
+ *
+ * Based on Link capabilities, apply optimization rules to come up with the best
+ * settings, including several external limit decision from the interface. This includes
+ * handling of subLinks.  Finally, after the port list data is updated, set the hardware
+ * state for all Links.
+ *
+ * @param[in] State our global state
+ */
+VOID
+STATIC
+LinkOptimization (
+  IN       STATE_DATA *State
+  )
+{
+  AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle);
+  State->HtFeatures->GatherLinkData (State);
+
+  AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle);
+  State->HtFeatures->RegangLinks (State);
+
+  AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle);
+  State->HtFeatures->SelectOptimalWidthAndFrequency (State);
+
+  // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing
+  // so check this after doing the sublinks.
+  AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle);
+  State->HtFeatures->SubLinkRatioFixup (State);
+  if (State->HtFeatures->IsCoherentRetryFixup (State)) {
+    // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again.
+    State->HtFeatures->SubLinkRatioFixup (State);
+  }
+
+  AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle);
+  State->HtFeatures->SetLinkData (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Handle system and performance tunings.
+ *
+ * Including traffic distribution, fifo and
+ * buffer tuning that can't be placed in the register table,
+ * and special config tunings.
+ *
+ * @param[in] State    Total Nodes, port list data
+ */
+VOID
+STATIC
+Tuning (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 Node;
+
+  // See if traffic distribution can be done and do it if so.
+  //
+  AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle);
+  State->HtFeatures->TrafficDistribution (State);
+
+  // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table.
+  //
+  AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle);
+  for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
+    State->Nb->BufferOptimizations (Node, State, State->Nb);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map.
+ * The mapping is filled in by reading the AP Mailboxes from PCI config on each node.
+ *
+ * @param[in]    State    global state, input data
+ *
+ */
+VOID
+STATIC
+InitApMaps (
+  IN       STATE_DATA *State
+  )
+{
+  UINT8 Node;
+  AP_MAIL_INFO NodeApMailBox;
+
+  // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug.
+  ASSERT (State->SocketDieToNodeMap != NULL);
+  ASSERT (State->NodeToSocketDieMap != NULL);
+
+  for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
+    NodeApMailBox = State->Nb->RetrieveMailbox (Node, State->Nb);
+    (*State->SocketDieToNodeMap)[NodeApMailBox.Fields.Socket][NodeApMailBox.Fields.Module].Node = Node;
+    (*State->NodeToSocketDieMap)[Node].Socket = (UINT8)NodeApMailBox.Fields.Socket;
+    (*State->NodeToSocketDieMap)[Node].Die = (UINT8)NodeApMailBox.Fields.Module;
+  }
+  // This requires the other maps to be initialized.
+  UpdateCoreRanges (State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Is the currently running core the BSC?
+ *
+ * Determine whether the init steps for BSC or AP core should be run.
+ *
+ * @param[in]    State    global state, input data
+ *
+ * @retval       TRUE    This is the boot core.
+ * @retval       FALSE   This is not the boot core.
+ */
+BOOLEAN
+STATIC
+IsBootCore (
+  IN       STATE_DATA    *State
+  )
+{
+  UINT64 Value;
+
+  LibAmdMsrRead (APIC_Base, &Value, State->ConfigHandle);
+
+  return ((BOOLEAN) (((UINT32) (Value & 0xFFFFFFFF) & ((UINT32)1 << APIC_Base_BSP)) != 0));
+}
+
+/***************************************************************************
+ ***                            HT Initialize                             ***
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  )
+{
+  STATE_DATA State;
+  NORTHBRIDGE Nb;
+  HT_FEATURES HtFeatures;
+  HT_INTERFACE HtInterface;
+  AGESA_STATUS DeallocateStatus;
+  AP_MAIL_INFO ApMailboxInfo;
+  UINT8 ApNode;
+
+  ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+  State.HtBlock = AmdHtInterface;
+  State.ConfigHandle = StdHeader;
+  State.PlatformConfiguration = PlatformConfiguration;
+
+  // Get the current HT internal interface (to HtBlock data)
+  NewHtInterface (&HtInterface, State.ConfigHandle);
+  State.HtInterface = &HtInterface;
+
+  // Get the current HT Feature Set
+  NewHtFeatures (&HtFeatures, State.ConfigHandle);
+  State.HtFeatures = &HtFeatures;
+
+  // Initialize from static options
+  State.IsUsingRecoveryHt = OptionHtConfiguration.IsUsingRecoveryHt;
+  State.IsSetHtCrcFlood = OptionHtConfiguration.IsSetHtCrcFlood;
+  State.IsUsingUnitIdClumping = OptionHtConfiguration.IsUsingUnitIdClumping;
+
+  // Initialize for status and event output
+  State.MaxEventClass = AGESA_SUCCESS;
+
+  // Allocate permanent heap structs that are interfaces to other AGESA services.
+  State.HtInterface->NewNodeAndSocketTables (&State);
+
+  if (IsBootCore (&State)) {
+    AGESA_TESTPOINT (TpProcHtEntry, State.ConfigHandle);
+    // Allocate Bsp only interface heap structs.
+    State.HtInterface->NewHopCountTable (&State);
+    // Allocate heap for our temporary working space.
+    AllocHeapParams.RequestedBufferSize = (sizeof (PORT_DESCRIPTOR) * (MAX_PLATFORM_LINKS * 2));
+    AllocHeapParams.BufferHandle = HT_STATE_DATA_HANDLE;
+    AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+    if (HeapAllocateBuffer (&AllocHeapParams, State.ConfigHandle) == AGESA_SUCCESS) {
+      State.PortList = (PORT_LIST)AllocHeapParams.BufferPtr;
+      // Create the BSP's northbridge.
+      NewNorthBridge (0, &State, &Nb);
+      State.Nb = &Nb;
+
+      CoherentInit (&State);
+      NcInit (&State);
+      LinkOptimization (&State);
+      Tuning (&State);
+
+      DeallocateStatus = HeapDeallocateBuffer (HT_STATE_DATA_HANDLE, State.ConfigHandle);
+      ASSERT (DeallocateStatus == AGESA_SUCCESS);
+      AGESA_TESTPOINT (TpProcHtDone, State.ConfigHandle);
+    } else {
+      ASSERT (FALSE);
+      State.MaxEventClass = AGESA_ERROR;
+      // Cannot Log entry due to heap allocate failed.
+    }
+  } else {
+    // Do the AP HT Init, which produces Node and Socket Maps for the AP's use.
+    AGESA_TESTPOINT (TpProcHtApMapEntry, State.ConfigHandle);
+    GetApMailbox (&ApMailboxInfo.Info, State.ConfigHandle);
+    ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
+    ApNode = (UINT8)ApMailboxInfo.Fields.Node;
+    NewNorthBridge (ApNode, &State, &Nb);
+    State.Nb = &Nb;
+    InitApMaps (&State);
+    AGESA_TESTPOINT (TpProcHtApMapDone, State.ConfigHandle);
+  }
+  return State.MaxEventClass;
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
new file mode 100755
index 0000000000..85fda1a11e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.c
@@ -0,0 +1,240 @@
+/**
+ * @file
+ *
+ * Construct a northbridge interface for a Node.
+ *
+ * Handle build options and run-time detection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "OptionsHt.h"
+#include "Ids.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNb.h"
+#include "htNbHardwareFam10.h"
+#include "CommonReturns.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFamRegisters.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_HT_HTNB_FILECODE
+
+extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/***************************************************************************
+ ***               FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS                 ***
+ ***************************************************************************/
+
+
+/**
+ * Initial construction data for no HT Northbridge.
+ */
+CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
+{
+  1,
+  (PF_WRITE_ROUTING_TABLE)CommonVoid,
+  (PF_WRITE_NODEID)CommonVoid,
+  (PF_READ_DEFAULT_LINK)CommonReturnZero8,
+  (PF_ENABLE_ROUTING_TABLES)CommonVoid,
+  (PF_DISABLE_ROUTING_TABLES)CommonVoid,
+  (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
+  (PF_READ_TOKEN)CommonReturnZero8,
+  (PF_WRITE_TOKEN)CommonVoid,
+  (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
+  (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
+  (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
+  (PF_STOP_LINK)CommonVoid,
+  (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
+  (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
+  (PF_READ_SB_LINK)CommonReturnZero8,
+  (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse,
+  (PF_SET_CONFIG_ADDR_MAP)CommonVoid,
+  (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32,
+  (PF_GATHER_LINK_FEATURES)CommonVoid,
+  (PF_SET_LINK_REGANG)CommonVoid,
+  (PF_SET_LINK_FREQUENCY)CommonVoid,
+  (PF_SET_LINK_UNITID_CLUMPING)CommonVoid,
+  (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
+  (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
+  (PF_BUFFER_OPTIMIZATIONS)CommonVoid,
+  (PF_GET_NUM_CORES_ON_NODE)CommonReturnZero8,
+  (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid,
+  (PF_GET_NODE_COUNT)CommonReturnZero8,
+  (PF_LIMIT_NODES)CommonVoid,
+  (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse,
+  (PF_GET_NEXT_LINK)CommonReturnZero32,
+  (PF_GET_PACKAGE_LINK)CommonReturnZero8,
+  (PF_MAKE_LINK_BASE)CommonReturnZero32,
+  (PF_GET_MODULE_INFO)CommonVoid,
+  (PF_POST_MAILBOX)CommonVoid,
+  (PF_RETRIEVE_MAILBOX)CommonReturnZero32,
+  (PF_GET_SOCKET)CommonReturnZero8,
+  0,
+  0,
+  0,
+  TRUE,
+  TRUE,
+  0,
+  NULL,
+  0,
+  NULL,
+  (PF_MAKE_KEY)CommonReturnZero64,
+  NULL
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Make a compatibility key.
+ *
+ * @HtNbMethod{::F_MAKE_KEY}
+ *
+ * Private routine to northbridge code.
+ * Create a key which can be used to determine whether a Node is compatible with
+ * the discovered configuration so far.  Currently, that means the family,
+ * extended family of the new Node are the same as the BSP's.  Family specific
+ * implementations can add whatever else is necessary.
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @return the key
+ */
+UINT64
+MakeKey (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+  UINT32 RawCpuId;
+  PCI_ADDR Reg;
+
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CPUID_3XFC);
+
+  LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, Nb->ConfigHandle);
+  GetLogicalIdFromCpuid (RawCpuId, &LogicalId, Nb->ConfigHandle);
+  return LogicalId.Family;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Construct a new northbridge.
+ *
+ * This routine encapsulates knowledge of how to tell significant differences between
+ * families of supported northbridges and what routines can be used in common and
+ * which are unique.  A fully populated northbridge interface is provided by Nb.
+ *
+ * @param[in]     Node    create a northbridge interface for this Node.
+ * @param[in]     State   global state
+ * @param[out]    Nb      the caller's northbridge structure to initialize.
+ */
+VOID
+NewNorthBridge (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+     OUT   NORTHBRIDGE *Nb
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+  UINT64  Match;
+  UINT32 RawCpuId;
+  PCI_ADDR Reg;
+  NORTHBRIDGE **InitializerInstance;
+
+  // Start with enough of the key to identify the northbridge interface
+  Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
+                                 MakePciBusFromNode (Node),
+                                 MakePciDeviceFromNode (Node),
+                                 CPU_NB_FUNC_03,
+                                 REG_NB_CPUID_3XFC);
+  LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle);
+  GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle);
+  Match = LogicalId.Family;
+
+  // Test each Northbridge interface in turn looking for a match.
+  // Use it to Init the Nb struct if a match is found.
+  //
+  ASSERT (OptionHtConfiguration.HtOptionFamilyNorthbridgeList != NULL);
+  InitializerInstance = (NORTHBRIDGE **) (OptionHtConfiguration.HtOptionFamilyNorthbridgeList);
+  while (*InitializerInstance != NULL) {
+    if ((Match & (*InitializerInstance)->CompatibleKey) != 0) {
+      LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle);
+      break;
+    }
+    InitializerInstance++;
+  }
+  // There must be an available northbridge implementation.
+  ASSERT (*InitializerInstance != NULL);
+
+  // Set the config handle for passing to the library.
+  Nb->ConfigHandle = State->ConfigHandle;
+}
+
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h
new file mode 100755
index 0000000000..1e0b29b738
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNb.h
@@ -0,0 +1,1065 @@
+/**
+ * @file
+ *
+ * HT NorthBridge header
+ *
+ * Defines the interface to the HT NorthBridge module for use by other internal
+ * HT modules.  This is not a wrapper or external interface, "public" in the
+ * comments below is used in the class definition style and refers to HT client
+ * modules only ("private" being for use only by the HT NB module itself).
+ *
+ * It is expected that there will be multiple northbridge implementation files all
+ * conforming to this common interface.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NB_H_
+#define _HT_NB_H_
+
+/**
+ * @page htimplnb HT Northbridge Implementation Guide
+ *
+ * The HT Northbridge provides access to the Northbridge hardware, in a manner that
+ * isolates calling code from knowledge about the hardware implementation or which
+ * features are supported in the current build.  This is the mechanism in the HT code for
+ * supporting new Family or Model northbridges, as well as the means for supporting
+ * multiple northbridges in a single build or mixed revision northbridge sets.
+ *
+ * @par Adding a Method to the Northbridge
+ *
+ * To add a new method to the Northbridge, follow these steps.
+ * <ul>
+ * <li> Create a typedef for the Method with the correct parameters and return type.
+ *
+ *   <ul>
+ *   <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same
+ *     name as the method table item, but with "_"'s and UPPERCASE, rather than mixed case.
+ *     @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
+ *
+ *   <li> Make a reference type for references to a method implementation:
+ *     @n <tt> /// Reference to a Method              </tt>
+ *     @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
+ *   </ul>
+ *
+ * <li> One of the parameters to @b all northbridge Methods is @b required to be a
+ *   reference to its current northbridge object.  By convention, this is the
+ *   last parameter.
+ *
+ * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
+ *   detailed description by providing a reference to the method instances page by including
+ *   the lines below:
+ *   @code
+ *   *
+ *   * @HtNbInstances
+ *   *
+ *   @endcode
+ *   @note It is important to provide documentation for the method type, because the method may not
+ *   have an implementation in any families supported by the current package. @n
+ *
+ * <li> Add to the ::NORTHBRIDGE struct an item for the Method:
+ *   @n <tt>  PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
+ * </ul>
+ *
+ * @par Implementing an Instance of a Northbridge method.
+ *
+ * To implement an instance of a method for a specific feature follow these steps.
+ *
+ * - In appropriate files, implement the method with the return type and parameters
+ * matching the Method typedef.
+ *   - If the Method implementation is common to all families, use the northbridge file
+ *   for the function area, for example, add a new coherent initialization support method to the
+ *   coherent northbridge file.
+ *   - If the Method implementation is unique to each supported northbridge, use the
+ *   family specific file for that function area (create it, if it doesn't already exist).
+ *   The family specific files have the same name as the common one suffixed with "FamNN",
+ *   or "FamNNRevX" if for a model or revision.
+ *
+ * - Name the function MethodName().  If Family specific, FamNNMethodName().
+ *
+ * - Create a doxygen function preamble for the method instance.  Begin the detailed description with
+ *   an Implements command to reference the method type and add this instance to the Method Instances page.
+ *   @code
+ *   *
+ *   *  @HtNbMethod{::F_METHOD_NAME}.
+ *   *
+ *   @endcode
+ *
+ * - To access other northbridge routines or data as part of the method implementation,
+ *   the function must use Nb->OtherMethod().  Do not directly access other northbridge
+ *   routines, because in the table there may be overrides or this routine may be shared by
+ *   multiple configurations.
+ *
+ * - Add the instance, or the correct family specific instance, to the ::NORTHBRIDGE instances
+ *   used by the northbridge constructor.
+ *
+ * - If a northbridge does not need an instance of the method use one of the CommonReturns from
+ *   CommonReturns.h with the same return type.
+ *
+ * @par Making common Northbridge Methods.
+ *
+ * In some cases, Northbridge methods can easily have a common implementation because the hardware
+ * is very compatible or is even standard.  In other cases, where processor family northbridges
+ * differ in their implementation, it may be possible to provide a single, common method
+ * implementation.  This can be accomplished by adding Northbridge data members.
+ *
+ * For example, a bit position or bit field mask can be used to accommodate different bit placement or size.
+ * Another example, a small table can be used to translate index values from a common set
+ * to specific sets.
+ *
+ * The Northbridge Method Instance must use its NORTHBRIDGE reference parameter to access
+ * private data members.
+ *
+ * @par Invoking HT Northbridge Methods.
+ *
+ * Each unique northbridge is constructed based on matching the current northbridge.
+ * @n @code
+ *   NORTHBRIDGE Nb;
+ *   // Create the BSP's northbridge.
+ *   NewNorthBridge (0, State, &Nb);
+ *   State->Nb = &Nb;
+ * @endcode
+ *
+ * The following example shows how to invoke a Northbridge method.
+ * @n @code
+ *   State->Nb->MethodName (State->Nb);
+ * @endcode
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *   Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ *                         DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+/** Use a macro to convert a Node number to a PCI device.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 makePCIDeviceFromNode(UINT8 Node);
+ */
+#define MakePciDeviceFromNode(Node)             \
+  ((UINT8) (24 + (Node)))
+
+/** Use a macro to convert a Node number to a PCI bus.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 MakePciBusFromNode(UINT8 Node);
+ */
+#define MakePciBusFromNode(Node)                \
+  ((UINT8) (0))
+
+/** Use a macro to convert a Node number to a PCI Segment.  If some future port of
+ * this code needs to, this can easily be replaced by the function declaration:
+ * UINT8 MakePciSegmentFromNode(UINT8 Node);
+ */
+#define MakePciSegmentFromNode(Node)            \
+  ((UINT8) (0))
+
+/*----------------------------------------------------------------------------
+ *                         TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Status for iterating through internal (if supported) and external links.
+ */
+typedef enum {
+  LinkIteratorEnd,         ///< This is the end of all links, no valid link.
+  LinkIteratorExternal,    ///< The next link (the one we got on this call) is an external link.
+  LinkIteratorInternal,    ///< The next link (the one we got on this call) is an internal link.
+  LinkIteratorMax          ///< For bounds checking and limit only.
+} LINK_ITERATOR_STATUS;
+
+#define LINK_ITERATOR_BEGIN 0xFF
+
+/**
+ * Write a temporary Route.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node The node on which to set a temporary route
+ * @param[in] Target A route to this node, which route table entry is to be set
+ * @param[in] Link The link which routes to the target node
+ * @param[in] Nb This northbridge
+ */
+typedef VOID F_WRITE_ROUTING_TABLE (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_ROUTING_TABLE *PF_WRITE_ROUTING_TABLE;
+
+/**
+ * Modifies the NodeID register on the target Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     NodeID the new value for NodeID
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_WRITE_NODEID (
+  IN       UINT8       Node,
+  IN       UINT8       NodeID,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_NODEID *PF_WRITE_NODEID;
+
+/**
+ * Read the Default Link
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will have its NodeID altered.
+ * @param[in]     Nb     this northbridge
+ *
+ * @return The HyperTransport Link where the request to
+ *        read the default Link came from.  Since this code is running on the BSP,
+ *        this should be the Link pointing back towards the BSP.
+ */
+typedef UINT8 F_READ_DEFAULT_LINK (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_DEFAULT_LINK *PF_READ_DEFAULT_LINK;
+
+/**
+ * Turns routing tables on for a given Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node that will have it's routing tables enabled
+ * @param[in] Nb this northbridge
+ */
+typedef VOID F_ENABLE_ROUTING_TABLES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_ENABLE_ROUTING_TABLES *PF_ENABLE_ROUTING_TABLES;
+
+/**
+ * Turns routing tables off for a given Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node that will have it's routing tables disabled
+ * @param[in] Nb this northbridge
+ */
+typedef VOID F_DISABLE_ROUTING_TABLES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_DISABLE_ROUTING_TABLES *PF_DISABLE_ROUTING_TABLES;
+
+/**
+ * Verify that the Link is coherent, connected, and ready
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link is coherent
+ *  @retval       FALSE   The Link has some other status
+*/
+typedef BOOLEAN F_VERIFY_LINK_IS_COHERENT (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_VERIFY_LINK_IS_COHERENT *PF_VERIFY_LINK_IS_COHERENT;
+
+/**
+ * Read the token stored in the scratchpad register field.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ *
+ * @return        the Token read from the Node
+ */
+typedef UINT8 F_READ_TOKEN (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_TOKEN *PF_READ_TOKEN;
+
+/**
+ * Write the token stored in the scratchpad register
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node the Node that marked with token
+ * @param[in]     Value the token Value
+ * @param[in]     Nb this northbridge
+ */
+typedef VOID F_WRITE_TOKEN (
+  IN       UINT8       Node,
+  IN       UINT8       Value,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_TOKEN *PF_WRITE_TOKEN;
+
+/**
+ * Full Routing Table Register initialization
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node            the Node that will be examined
+ * @param[in]     Target          the Target Node for these routes
+ * @param[in]     ReqLink         the Link for requests to Target
+ * @param[in]     RspLink         the Link for responses to Target
+ * @param[in]     BroadcastLinks  the broadcast Links
+ * @param[in]     Nb              this northbridge
+ */
+typedef VOID F_WRITE_FULL_ROUTING_TABLE (
+  IN       UINT8       Node,
+  IN       UINT8       Target,
+  IN       UINT8       ReqLink,
+  IN       UINT8       RspLink,
+  IN       UINT32      BroadcastLinks,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_FULL_ROUTING_TABLE *PF_WRITE_FULL_ROUTING_TABLE;
+
+/**
+ * Determine whether a Node is compatible with the discovered configuration so far.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb this northbridge
+ *
+ * @retval   TRUE    the node is not compatible
+ * @retval   FALSE   the node is compatible
+ */
+typedef BOOLEAN F_IS_ILLEGAL_TYPE_MIX (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_IS_ILLEGAL_TYPE_MIX *PF_IS_ILLEGAL_TYPE_MIX;
+
+/**
+ * Return whether the current configuration exceeds the capability
+ * of the nodes detected.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node
+ * @param[in]     State    sysMpCap (updated) and NodesDiscovered
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE     system is not capable of current config.
+ * @retval        FALSE    system is capable of current config.
+ */
+typedef BOOLEAN F_IS_EXCEEDED_CAPABLE (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_IS_EXCEEDED_CAPABLE *PF_IS_EXCEEDED_CAPABLE;
+
+/**
+ * Stop a link, so that it is isolated from a connected device.
+ *
+ * @HtNbInstances
+ *
+ * Use is for fatal incompatible configurations.
+ * While XMIT and RCV off are HT standard, the use of these bits
+ * is generally family specific.
+ *
+ * @param[in] Node   the node to stop a link on.
+ * @param[in] Link   the link to stop.
+ * @param[in] State  access to special routine for writing link control register
+ * @param[in] Nb     this northbridge.
+ */
+typedef VOID F_STOP_LINK (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_STOP_LINK *PF_STOP_LINK;
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbInstances
+ *
+ * This routine is expected to be unimplemented for most families.
+ * Some configurations may require that links be processed specially to prevent
+ * serious problems, like hangs.  Check for that condition in this routine,
+ * handle the link both for hardware and for adding to port list, if appropriate.
+ * If this routine adds the link to port list or the link should not be added, return TRUE.
+ *
+ * @param[in] Node  The Node which has this link
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This link received special handling.
+ * @retval    FALSE This link was not handled specially, handle it normally.
+ *
+ */
+typedef BOOLEAN F_HANDLE_SPECIAL_LINK_CASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_HANDLE_SPECIAL_LINK_CASE *PF_HANDLE_SPECIAL_LINK_CASE;
+
+/**
+ * Fix (hopefully) exceptional conditions.
+ *
+ * @HtNbInstances
+ *
+ * This routine is expected to be unimplemented for most families.
+ * Some configurations may require that nodes be processed specially to prevent
+ * serious problems, like hangs.  Check for that condition in this routine,
+ * handle the node both for hardware and for adding to port list, if appropriate.
+ * If this routine adds the node to port list or the node should not be added, return TRUE.
+ *
+ * @param[in] Node  The Node which need to be checked.
+ * @param[in] Link  The link to check for special conditions.
+ * @param[in] State our global state.
+ * @param[in] Nb    this northbridge.
+ *
+ * @retval    TRUE  This node received special handling.
+ * @retval    FALSE This node was not handled specially, handle it normally.
+ *
+ */
+typedef BOOLEAN F_HANDLE_SPECIAL_NODE_CASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_HANDLE_SPECIAL_NODE_CASE *PF_HANDLE_SPECIAL_NODE_CASE;
+
+/**
+ * Get Info about Module Type of this northbridge
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node                the Node
+ * @param[out]    ModuleType          0 for Single, 1 for Multi
+ * @param[out]    Module              The module number of this node (0 if Single)
+ * @param[in]     Nb                  this northbridge
+ *
+ */
+typedef VOID F_GET_MODULE_INFO (
+  IN       UINT8       Node,
+     OUT   UINT8       *ModuleType,
+     OUT   UINT8       *Module,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_GET_MODULE_INFO *PF_GET_MODULE_INFO;
+
+/**
+ * Post info to AP cores via a mailbox.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailInfo    The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+typedef VOID F_POST_MAILBOX (
+  IN       UINT8        Node,
+  IN       AP_MAILBOXES ApMailInfo,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_POST_MAILBOX *PF_POST_MAILBOX;
+
+/**
+ * Retrieve info from a node's AP mailbox.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node          the Node
+ * @param[in]     ApMailInfo    The info to post
+ * @param[in]     Nb            this northbridge
+ *
+ */
+typedef AP_MAIL_INFO F_RETRIEVE_MAILBOX (
+  IN       UINT8        Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_RETRIEVE_MAILBOX *PF_RETRIEVE_MAILBOX;
+
+/**
+ * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node     The node for which we want the socket id.
+ * @param[in]   TempNode The temporary node id route where the node can be accessed.
+ * @param[in]   Nb       Our Northbridge.
+ *
+ * @return      The Socket Id
+ */
+typedef UINT8 F_GET_SOCKET (
+  IN       UINT8       Node,
+  IN       UINT8       TempNode,
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_SOCKET *PF_GET_SOCKET;
+
+/**
+ * Return the Link to the Southbridge
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Nb this northbridge
+ *
+ * @return the Link to the southbridge
+ */
+typedef UINT8 F_READ_SB_LINK (
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_SB_LINK *PF_READ_SB_LINK;
+
+/**
+ * Verify that the Link is non-coherent, connected, and ready
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Link    the Link on that Node to examine
+ * @param[in]     Nb      this northbridge
+ *
+ * @retval        TRUE    The Link is non-coherent.
+ * @retval        FALSE   The Link has some other status
+ */
+typedef BOOLEAN F_VERIFY_LINK_IS_NON_COHERENT (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_VERIFY_LINK_IS_NON_COHERENT *PF_VERIFY_LINK_IS_NON_COHERENT;
+
+/**
+ * Enable config access to a non-coherent chain for the given bus range.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     ConfigMapIndex the map entry to set
+ * @param[in]     SecBus         The secondary bus number to use
+ * @param[in]     SubBus         The subordinate bus number to use
+ * @param[in]     TargetNode     The Node  that shall be the recipient of the traffic
+ * @param[in]     TargetLink     The Link that shall be the recipient of the traffic
+ * @param[in]     State          our global state
+ * @param[in]     Nb             this northbridge
+ */
+typedef VOID F_SET_CONFIG_ADDR_MAP (
+  IN       UINT8       ConfigMapIndex,
+  IN       UINT8       SecBus,
+  IN       UINT8       SubBus,
+  IN       UINT8       TargetNode,
+  IN       UINT8       TargetLink,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_CONFIG_ADDR_MAP *PF_SET_CONFIG_ADDR_MAP;
+
+/**
+ * Northbridge specific Frequency limit.
+ *
+ * @HtNbInstances
+ *
+ * Return a mask that eliminates HT frequencies that cannot be used due to a slow
+ * northbridge frequency.
+ *
+ * @param[in]     Node       Result could (later) be for a specific Node
+ * @param[in]     Interface  Access to non-HT support functions.
+ * @param[in]     Nb         this northbridge
+ *
+ * @return Frequency mask
+ */
+typedef UINT32 F_NORTH_BRIDGE_FREQ_MASK (
+  IN       UINT8       Node,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_NORTH_BRIDGE_FREQ_MASK *PF_NORTH_BRIDGE_FREQ_MASK;
+
+/**
+ * Get Link features into system data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in,out] ThisPort   The PortList structure entry for this link's port
+ * @param[in]     Interface  Access to non-HT support functions.
+ * @param[in]     Nb         this northbridge
+ */
+typedef VOID F_GATHER_LINK_FEATURES (
+  IN OUT   PORT_DESCRIPTOR *ThisPort,
+  IN       HT_INTERFACE     *Interface,
+  IN       NORTHBRIDGE     *Nb
+  );
+/// Reference to a method.
+typedef F_GATHER_LINK_FEATURES *PF_GATHER_LINK_FEATURES;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the node on which to regang a link
+ * @param[in]     Link   the sublink 0 of the sublink pair to regang
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_SET_LINK_REGANG (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_REGANG *PF_SET_LINK_REGANG;
+
+/**
+ * Change the hardware state for all Links according to the now optimized data in the
+ * port list data structure.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node        the node on which to set frequency for a link
+ * @param[in]     Link        the link to set frequency
+ * @param[in]     Frequency   the frequency to set
+ * @param[in]     Nb          this northbridge
+ */
+typedef VOID F_SET_LINK_FREQUENCY (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT8          Frequency,
+  IN       NORTHBRIDGE    *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_FREQUENCY *PF_SET_LINK_FREQUENCY;
+
+/**
+ * Set the link's Unit Id Clumping enable.
+ *
+ * @HtNbInstances
+ *
+ * This applies to the host root of a non-coherent chain.
+ *
+ * @param[in]     Node              the node on which to set frequency for a link
+ * @param[in]     Link              the link to set frequency
+ * @param[in]     ClumpingEnables   the unit id clumping enables to set
+ * @param[in]     Nb                this northbridge
+ */
+typedef VOID F_SET_LINK_UNITID_CLUMPING (
+  IN       UINT8          Node,
+  IN       UINT8          Link,
+  IN       UINT32         ClumpingEnables,
+  IN       NORTHBRIDGE    *Nb
+  );
+/// Reference to a method.
+typedef F_SET_LINK_UNITID_CLUMPING *PF_SET_LINK_UNITID_CLUMPING;
+
+/**
+ * Set the traffic distribution register for the Links provided.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Links01   coherent Links from Node 0 to 1
+ * @param[in]     Links10   coherent Links from Node 1 to 0
+ * @param[in]     Nb        this northbridge
+ */
+typedef VOID F_WRITE_TRAFFIC_DISTRIBUTION (
+  IN       UINT32       Links01,
+  IN       UINT32       Links10,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Reference to a method.
+typedef F_WRITE_TRAFFIC_DISTRIBUTION *PF_WRITE_TRAFFIC_DISTRIBUTION;
+
+/**
+ * Write a link pair to the link pair distribution and fixups.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]    Node           Set the pair on this node
+ * @param[in]    ConnectedNode  The Node to which this link pair directly connects.
+ * @param[in]    Pair           Using this pair set in the register
+ * @param[in]    Asymmetric     True if different widths
+ * @param[in]    MasterLink     Set this as the master link and in the route
+ * @param[in]    AlternateLink  Set this as the alternate link
+ * @param[in]    Nb             this northbridge
+ *
+ */
+typedef VOID F_WRITE_LINK_PAIR_DISTRIBUTION (
+  IN       UINT8        Node,
+  IN       UINT8        ConnectedNode,
+  IN       UINT8        Pair,
+  IN       BOOLEAN      Asymmetric,
+  IN       UINT8        MasterLink,
+  IN       UINT8        AlternateLink,
+  IN       NORTHBRIDGE  *Nb
+  );
+/// Pointer to method WriteLinkPairDistribution
+typedef F_WRITE_LINK_PAIR_DISTRIBUTION *PF_WRITE_LINK_PAIR_DISTRIBUTION;
+
+/**
+ * Family specific tunings.
+ *
+ * @HtNbInstances
+ *
+ * Buffer tunings are inherently northbridge specific. Check for specific configs
+ * which require adjustments and apply any standard workarounds to this Node.
+ *
+ * @param[in]     Node   the Node to tune
+ * @param[in]     State   global state
+ * @param[in]     Nb     this northbridge
+ */
+typedef VOID F_BUFFER_OPTIMIZATIONS (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_BUFFER_OPTIMIZATIONS *PF_BUFFER_OPTIMIZATIONS;
+
+/**
+ * Return the number of cores (1 based count) on Node.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node   the Node that will be examined
+ * @param[in]     Nb     this northbridge
+ *
+ * @return        the number of cores
+ */
+typedef UINT8 F_GET_NUM_CORES_ON_NODE (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_GET_NUM_CORES_ON_NODE *PF_GET_NUM_CORES_ON_NODE;
+
+/**
+ * Write the total number of cores and Nodes to the Node
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node         the Node that will be examined
+ * @param[in]     TotalNodes   the total number of Nodes
+ * @param[in]     TotalCores   the total number of cores
+ * @param[in]     Nb           this northbridge
+ */
+typedef VOID F_SET_TOTAL_NODES_AND_CORES (
+  IN       UINT8       Node,
+  IN       UINT8       TotalNodes,
+  IN       UINT8       TotalCores,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_SET_TOTAL_NODES_AND_CORES *PF_SET_TOTAL_NODES_AND_CORES;
+
+/**
+ * Get the Count of Nodes in the system.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Nb    This Northbridge.
+ *
+ * @return    The Count (1 based) of Nodes in the system.
+ */
+typedef UINT8 F_GET_NODE_COUNT (
+  IN       NORTHBRIDGE *Nb
+  );
+
+/// Reference to a method.
+typedef F_GET_NODE_COUNT *PF_GET_NODE_COUNT;
+
+/**
+ * Limit coherent config accesses to cpus as indicated by Nodecnt.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node that will be examined
+ * @param[in]     Nb      this northbridge
+ */
+typedef VOID F_LIMIT_NODES (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_LIMIT_NODES *PF_LIMIT_NODES;
+
+/**
+ * Return the LinkFailed status AFTER an attempt is made to clear the bit.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node  the Node that will be examined
+ * @param[in]     Link  the Link on that Node to examine
+ * @param[in]     State  access to call back routine
+ * @param[in]     Nb    this northbridge
+ *
+ * @retval        TRUE   the Link is not connected or has hard error
+ * @retval        FALSE  the Link is connected
+ */
+typedef BOOLEAN F_READ_TRUE_LINK_FAIL_STATUS (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       STATE_DATA  *State,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_READ_TRUE_LINK_FAIL_STATUS *PF_READ_TRUE_LINK_FAIL_STATUS;
+
+/**
+ * Get the next link for iterating over the links on a node in the correct order.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node The node on which to iterate links.
+ * @param[in,out] Link IN: the current iteration context, OUT: the next link.
+ * @param[in]     Nb   This Northbridge, access to config pointer.
+ *
+ * @retval LinkIteratorEnd         There is no next link (Link is back to BEGIN).
+ * @retval LinkIteratorExternal    The next Link is an external link.
+ * @retval LinkIteratorInternal    The next Link is an internal link.
+ */
+typedef LINK_ITERATOR_STATUS F_GET_NEXT_LINK (
+  IN       UINT8       Node,
+  IN OUT   UINT8       *Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Pointer to method GetNextLink
+typedef F_GET_NEXT_LINK *PF_GET_NEXT_LINK;
+
+/**
+ * Get the Package Link number, given the node and real link number.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]   Node       the node which has this link
+ * @param[in]   Link       the link on that node
+ * @param[in]   Nb         this northbridge
+ *
+ * @return                 the Package Link
+ *
+ */
+typedef UINT8 F_GET_PACKAGE_LINK (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method
+typedef F_GET_PACKAGE_LINK *PF_GET_PACKAGE_LINK;
+
+/**
+ * Return the HT Host capability base PCI config address for a Link.
+ *
+ * @HtNbInstances
+ *
+ * @param[in]     Node    the Node this Link is on
+ * @param[in]     Link    the Link
+ * @param[in]     Nb      this northbridge
+ *
+ * @return  the pci config address
+ */
+typedef PCI_ADDR F_MAKE_LINK_BASE (
+  IN       UINT8       Node,
+  IN       UINT8       Link,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_MAKE_LINK_BASE *PF_MAKE_LINK_BASE;
+
+/**
+ * Make a compatibility key.
+ *
+ * @HtNbInstances
+ *
+ * @param[in] Node the Node
+ * @param[in] Nb   this northbridge
+ *
+ * @return the key
+ */
+typedef UINT64 F_MAKE_KEY (
+  IN       UINT8       Node,
+  IN       NORTHBRIDGE *Nb
+  );
+/// Reference to a method.
+typedef F_MAKE_KEY *PF_MAKE_KEY;
+
+/**
+ * The northbridge interface.
+ *
+ * Abstract the hardware implementation of the processor northbridge.  Feature code does
+ * not need to be tailored to specific families.  Also, more than a single family (or
+ * model in some cases) can be supported at once.  Multiple family support can be for
+ * mixed revisions or for incompatible revisions where only one is used at a time.
+ *
+ * The northbridge object contains both HT component public and northbridge private
+ * members.  These sets are grouped together.  Within each group, members are grouped
+ * according to the function area they support.
+ *
+ */
+struct _NORTHBRIDGE {
+  /* Public data, clients of northbridge can access */
+  UINT8 MaxLinks;               /**< The maximum number of Links implemented by the northbridge */
+
+  /* Public Interfaces for northbridge clients, coherent init*/
+  PF_WRITE_ROUTING_TABLE WriteRoutingTable;    /**< Method: Write a Temporary route for discovery */
+  PF_WRITE_NODEID WriteNodeID;    /**< Method: Assign a Node ID*/
+  PF_READ_DEFAULT_LINK ReadDefaultLink;    /**< Method: Which link are we connected to on a remote node? */
+  PF_ENABLE_ROUTING_TABLES EnableRoutingTables;    /**< Method: Make the routing table active */
+  PF_DISABLE_ROUTING_TABLES DisableRoutingTables;    /**< Method: Put a node back in discoverable state (deflnk) */
+  PF_VERIFY_LINK_IS_COHERENT VerifyLinkIsCoherent;    /**< Method: is a link connected and coherent? */
+  PF_READ_TOKEN ReadToken;    /**< Method: Read the enumeration token from a node */
+  PF_WRITE_TOKEN WriteToken;    /**< Method: Assign an enumeration token to a node */
+  PF_WRITE_FULL_ROUTING_TABLE WriteFullRoutingTable;    /**< Method: Set a complete routing table entry on a node */
+  PF_IS_ILLEGAL_TYPE_MIX IsIllegalTypeMix;    /**< Method: Is this node compatible with the system */
+  PF_IS_EXCEEDED_CAPABLE IsExceededCapable;    /**< Method: Is this node capable of working in this system */
+  PF_STOP_LINK StopLink;    /**< Method: stop a link which must be unused */
+  PF_HANDLE_SPECIAL_LINK_CASE HandleSpecialLinkCase;    /**< Method: Fix broken configuration designs */
+  PF_HANDLE_SPECIAL_NODE_CASE HandleSpecialNodeCase;    /**< Method: Fix broken configuration designs */
+
+  /* Public Interfaces for northbridge clients, noncoherent init */
+  PF_READ_SB_LINK ReadSouthbridgeLink;    /**< Method: Which link goes to the southbridge? */
+  PF_VERIFY_LINK_IS_NON_COHERENT VerifyLinkIsNonCoherent;    /**< Method: is a link connected and non-coherent? */
+  PF_SET_CONFIG_ADDR_MAP SetConfigAddrMap;    /**< Method: Add a non-coherent chain to the PCI Config Bus Address Map */
+
+  /* Public Interfaces for northbridge clients, Optimization */
+  PF_NORTH_BRIDGE_FREQ_MASK NorthBridgeFreqMask;    /**< Method: Check for frequency limits other than HT */
+  PF_GATHER_LINK_FEATURES GatherLinkFeatures;        /**< Method: Get frequency and link features */
+  PF_SET_LINK_REGANG SetLinkRegang;              /**< Method: Set a Link to regang */
+  PF_SET_LINK_FREQUENCY SetLinkFrequency;        /**< Method: Set the link Frequency */
+  PF_SET_LINK_UNITID_CLUMPING SetLinkUnitIdClumping;   /**< Method: Set the link's Unit Id Clumping register */
+
+  /* Public Interfaces for northbridge clients, System and performance Tuning. */
+  PF_WRITE_TRAFFIC_DISTRIBUTION WriteTrafficDistribution;    /**< Method: traffic distribution setting */
+  PF_WRITE_LINK_PAIR_DISTRIBUTION WriteLinkPairDistribution;    /**< Method: Link Pair setting and fix up */
+  PF_BUFFER_OPTIMIZATIONS BufferOptimizations;    /**< Method: system tunings which can not be
+                                                   * done using register table */
+
+  /* Public Interfaces for northbridge clients, utility routines */
+  PF_GET_NUM_CORES_ON_NODE GetNumCoresOnNode;    /**< Method: Count cores */
+  PF_SET_TOTAL_NODES_AND_CORES SetTotalNodesAndCores;    /**< Method: Set Node and Core counts */
+  PF_GET_NODE_COUNT GetNodeCount;    /**< Method: Get the Count (1 based) of Nodes in the system. */
+  PF_LIMIT_NODES LimitNodes;    /**< Method: Set the Limit Config Space feature */
+  PF_READ_TRUE_LINK_FAIL_STATUS ReadTrueLinkFailStatus;    /**< Method: Get Fault status and connectivity of a link */
+  PF_GET_NEXT_LINK GetNextLink;    /**< Method: Iterate over a node's Internal, then External links. */
+  PF_GET_PACKAGE_LINK GetPackageLink;    /**< Method: the package link corresponding to a node's link */
+  PF_MAKE_LINK_BASE MakeLinkBase;    /**< Method: Provide the PCI Config Base register offset of a CPU link */
+  PF_GET_MODULE_INFO GetModuleInfo;    /**< Method: Get Module Type and internal Module number */
+  PF_POST_MAILBOX PostMailbox;     /**< Method: Post info to the mailbox register */
+  PF_RETRIEVE_MAILBOX RetrieveMailbox;     /**< Method: Retrieve info from the mailbox register */
+  PF_GET_SOCKET GetSocket;    /**< Method: Get a node's Socket, using the hardware naming method. */
+
+  /* Private Data for northbridge implementation use only */
+  UINT32 SelfRouteRequestMask;  /**< Bit pattern for route request to self in routing table register */
+  UINT32 SelfRouteResponseMask; /**< Bit pattern for route response to self in routing table register */
+  UINT8 BroadcastSelfBit;       /**< Bit offset of broadcast self bit in routing table register */
+  BOOLEAN IsOrderBSPCoresByNode; /**< This processor orders Cores by Node id on the BSP, if TRUE. */
+  BOOLEAN IsOrderCoresByModule;  /**< Processors other than the BSP order Cores by Module, if TRUE. */
+  UINT64 CompatibleKey;         /**< Used for checking compatibility of northbridges in the system */
+  PACKAGE_HTLINK_MAP PackageLinkMap;    /**< Tell GetPackageLink() how to assign link names */
+  UINT32 CoreFrequency;           /**< Cache the northbridge core frequency, so repeated interface calls are avoided.
+                                   *   A value of zero, means no value yet. */
+  IGNORE_LINK *DefaultIgnoreLinkList;   /**< After processing the user interface ignore link, process this list. */
+
+  /* Private Interfaces for northbridge implementation. */
+  PF_MAKE_KEY MakeKey;    /**< Method: make the compatibility key for this node */
+
+  /** Config Pointer, opaque handle for passing to lib */
+  VOID *ConfigHandle;
+};
+
+/*----------------------------------------------------------------------------
+ *                           FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+/**
+ * Make a compatibility key.
+ *
+ */
+UINT64
+MakeKey (
+  IN       UINT8 Node,
+  IN       NORTHBRIDGE *Nb
+  );
+
+VOID
+NewNorthBridge (
+  IN       UINT8       Node,
+  IN       STATE_DATA  *State,
+     OUT   NORTHBRIDGE *Nb
+  );
+
+#endif  /* _HT_NB_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNbHardwareFam10.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNbHardwareFam10.h
new file mode 100755
index 0000000000..66ac12559c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNbHardwareFam10.h
@@ -0,0 +1,117 @@
+/**
+ * @file
+ *
+ * Northbridge hardware definitions for Family 10h.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+#ifndef _HT_NB_HARDWARE_FAM10_H_
+#define _HT_NB_HARDWARE_FAM10_H_
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/* CPU Northbridge Functions */
+#define CPU_HTNB_FUNC_00                  0
+#define CPU_HTNB_FUNC_04                  4
+#define CPU_ADDR_FUNC_01                  1
+#define CPU_NB_FUNC_03                    3
+
+/* Function 0 registers */
+#define REG_ROUTE0_0X40                   0x40
+#define REG_ROUTE1_0X44                   0x44
+#define REG_NODE_ID_0X60                  0x60
+#define REG_UNIT_ID_0X64                  0x64
+#define REG_LINK_TRANS_CONTROL_0X68       0x68
+#define REG_LINK_INIT_CONTROL_0X6C        0x6C
+#define REG_HT_CAP_BASE_0X80              0x80
+#define REG_HT_LINK_CLUMPING0_0X110       0x110
+#define REG_HT_LINK_RETRY0_0X130          0x130
+#define REG_HT_EXTENDED_NODE_ID_F0X160    0x160
+#define HTREG_NODE_CPUCNT_4_0             0x1F
+#define HTREG_EXTNODE_CPUCNT_7_5          0xE0
+#define REG_HT_TRAFFIC_DIST_0X164         0x164
+#define REG_LINK_GLOBAL_EXT_CONTROL_0x16C 0x16C
+#define REG_HT_LINK_EXT_CONTROL0_0X170    0x170
+#define REG_HT_LINK_INITIALIZATION_0X1A0  0x1A0
+#define PAIR_SELECT_OFFSET                8
+#define REG_HT_LINK_PAIR_DIST_0X1E0       0x1E0
+
+/* Function 1 registers */
+#define REG_ADDR_CONFIG_MAP0_1XE0         0xE0
+#define CPU_ADDR_NUM_CONFIG_MAPS          4
+
+/* Function 3 registers */
+#define REG_NB_SRI_XBAR_BUF_3X70          0x70
+#define REG_NB_MCT_XBAR_BUF_3X78          0x78
+#define REG_NB_FIFOPTR_3XDC               0xDC
+#define REG_NB_CAPABILITY_3XE8            0xE8
+#define REG_NB_CPUID_3XFC                 0xFC
+#define REG_NB_LINK_XCS_TOKEN0_3X148      0x148
+#define REG_NB_MCA_LINK_THRESHOLD_3X168   0x168
+#define REG_NB_MCA_L3_THRESHOLD_3X170     0x170
+#define REG_NB_DOWNCORE_3X190             0x190
+#define REG_NB_SBI_CONTROL_3X1E4          0x1E4
+
+/* Function 4 registers */
+
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#endif /* _HT_NB_HARDWARE_FAM10_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
new file mode 100755
index 0000000000..ae06ba254f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.c
@@ -0,0 +1,659 @@
+/**
+ * @file
+ *
+ * Code for detailed notification of events and status.
+ *
+ * Routines for logging and reporting details and summary status.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Topology.h"
+#include "htFeat.h"
+#include "htNotify.h"
+#include "GeneralServices.h"
+#include "Filecode.h"
+#define FILECODE PROC_HT_HTNOTIFY_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Log an event.
+ *
+ * Errors, events, faults, warnings, and useful information are provided by
+ * calling this routine as often as necessary, once for each notification.
+ * @sa AGESA.h for class, and event definitions.
+ * @sa htNotify.h for event data definitions.
+ *
+ * @param[in]     EvtClass      What level event is this
+ * @param[in]     Event         A unique ID of this event
+ * @param[in]     EventData     useful data associated with the event.
+ * @param[in]     State         the log area and remaining free space
+ */
+VOID
+STATIC
+setEventNotify (
+  IN       AGESA_STATUS  EvtClass,
+  IN       UINT32        Event,
+  IN       CONST UINT8  *EventData,
+  IN       STATE_DATA   *State
+  )
+{
+  UINT32 DataParam[NUMBER_OF_EVENT_DATA_PARAMS];
+
+  // Remember the highest event class notified, that becomes our return code.
+  if (State->MaxEventClass < EvtClass) {
+    State->MaxEventClass = EvtClass;
+  }
+
+  // Copy the event data to the log data
+  LibAmdMemCopy (
+    DataParam,
+    (VOID *)EventData,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  // Log the event
+  PutEventLog (
+    EvtClass,
+    Event,
+    DataParam[0],
+    DataParam[1],
+    DataParam[2],
+    DataParam[3],
+    State->ConfigHandle
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_HW_SYNCFLOOD
+ *
+ * @param[in] Node      The node on which the fault is reported
+ * @param[in] Link      The link from that node
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyAlertHwSyncFlood (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       STATE_DATA   *State
+  )
+{
+  HT_EVENT_DATA_HW_SYNCFLOOD Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  setEventNotify (AGESA_ALERT,
+                 HT_EVENT_HW_SYNCFLOOD,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_HW_HTCRC
+ *
+ * @param[in] Node      The node on which the error is reported
+ * @param[in] Link      The link from that node
+ * @param[in] LaneMask  The lanes which had CRC
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyAlertHwHtCrc (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      LaneMask,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_HW_HT_CRC Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.LaneMask = LaneMask;
+  setEventNotify (AGESA_ALERT,
+                 HT_EVENT_HW_HTCRC,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_BUS_MAX_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Bus       The bus number to assign
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohBusMaxExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Bus,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Bus = Bus;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_BUS_MAX_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_CFG_MAP_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohCfgMapExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_CFG_MAP_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_BUID_EXCEED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] Id        The Id which was attempted to assigned
+ * @param[in] Units     The number of units in this device
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohBuidExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       UINT8      Units,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_BUID_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  Evt.CurrentBuid = Id;
+  Evt.UnitCount = Units;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_BUID_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_DEVICE_FAILED
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] Id        The Id which was attempted to assigned
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorNcohDeviceFailed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  Evt.AttemptedBuid = Id;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_NCOH_DEVICE_FAILED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_NCOH_AUTO_DEPTH
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyInfoNcohAutoDepth (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_NCOH_AUTO_DEPTH Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_SUCCESS,
+                 HT_EVENT_NCOH_AUTO_DEPTH,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyWarningOptRequiredCapRetry (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_REQUIRED_CAP_RETRY,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
+ *
+ * @param[in] Node      The node on which the chain is located
+ * @param[in] Link      The link from that node
+ * @param[in] Depth     Position on chain
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyWarningOptRequiredCapGen3 (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Depth,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.Depth = Depth;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_REQUIRED_CAP_GEN3,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_UNUSED_LINKS
+ *
+ * @param[in]  NodeA    One of the nodes connected
+ * @param[in]  NodeB    The other connected node
+ * @param[in]  LinkA    its unusable link
+ * @param[in]  LinkB    its unusable link
+ * @param[in]  State    our State
+ *
+ */
+VOID
+NotifyWarningOptUnusedLinks (
+  IN       UINT32    NodeA,
+  IN       UINT32    LinkA,
+  IN       UINT32    NodeB,
+  IN       UINT32    LinkB,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_UNUSED_LINKS Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.NodeA = NodeA;
+  Evt.LinkA = LinkA;
+  Evt.NodeB = NodeB;
+  Evt.LinkB = LinkB;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_UNUSED_LINKS,
+                 (UINT8 *)&Evt, State);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_OPT_LINK_PAIR_EXCEED
+ *
+ * @param[in]  NodeA      One of the nodes connected
+ * @param[in]  NodeB      The other connected node
+ * @param[in]  MasterLink its unusable Masterlink
+ * @param[in]  AltLink    its unusable Alternate link
+ * @param[in]  State      our State
+ *
+ */
+VOID
+NotifyWarningOptLinkPairExceed (
+  IN       UINT32    NodeA,
+  IN       UINT32    NodeB,
+  IN       UINT32    MasterLink,
+  IN       UINT32    AltLink,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.NodeA = NodeA;
+  Evt.MasterLink = MasterLink;
+  Evt.NodeB = NodeB;
+  Evt.AltLink = AltLink;
+  setEventNotify (AGESA_WARNING,
+                 HT_EVENT_OPT_LINK_PAIR_EXCEED,
+                 (UINT8 *)&Evt, State);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_NO_TOPOLOGY
+ *
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyErrorCohNoTopology (
+  IN       UINT8 Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_NO_TOPOLOGY Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_ERROR,
+                 HT_EVENT_COH_NO_TOPOLOGY,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
+ *
+ * @param[in] Node      The node from which a new node was discovered
+ * @param[in] Link      The link from that node
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyFatalCohProcessorTypeMix (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_CRITICAL,
+                 HT_EVENT_COH_PROCESSOR_TYPE_MIX,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_NODE_DISCOVERED
+ *
+ * @param[in] Node       Node from which a new node was discovered
+ * @param[in] Link       The link to that new node
+ * @param[in] NewNode    The new node's id
+ * @param[in] TempRoute  Temporarily, during discovery, the new node is accessed at this id.
+ * @param[in] State      our State
+ *
+ */
+VOID
+NotifyInfoCohNodeDiscovered (
+  IN       UINT8 Node,
+  IN       UINT8 Link,
+  IN       UINT8 NewNode,
+  IN       UINT8 TempRoute,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_NODE_DISCOVERED Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.NewNode = NewNode;
+  Evt.TempRoute = TempRoute;
+  setEventNotify (AGESA_SUCCESS,
+                 HT_EVENT_COH_NODE_DISCOVERED,
+                 (UINT8 *)&Evt, State);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * For event HT_EVENT_COH_MPCAP_MISMATCH
+ *
+ * @param[in] Node      The node from which a new node was discovered
+ * @param[in] Link      The link from that node
+ * @param[in] Cap       The aggregate system MP Capability
+ * @param[in] Nodes     The total number of nodes found so far
+ * @param[in] State     our State
+ *
+ */
+VOID
+NotifyFatalCohMpCapMismatch (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Cap,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  )
+{
+  HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt;
+  // Zero out the event data
+  LibAmdMemFill (
+    &Evt,
+    0,
+    (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
+    State->ConfigHandle
+    );
+
+  Evt.Node = Node;
+  Evt.Link = Link;
+  Evt.SysMpCap = Cap;
+  Evt.TotalNodes = Nodes;
+  setEventNotify (AGESA_CRITICAL,
+                 HT_EVENT_COH_MPCAP_MISMATCH,
+                 (UINT8 *)&Evt, State);
+}
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
new file mode 100755
index 0000000000..5059dcef2a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htNotify.h
@@ -0,0 +1,297 @@
+/**
+ * @file
+ *
+ * HT Notify interface.
+ *
+ * This file provides internal interface to event and status
+ * notification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $        @e  \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+
+#ifndef _HT_NOTIFY_H_
+#define _HT_NOTIFY_H_
+
+/*----------------------------------------------------------------------------------------*/
+/* Event specific event data definitions.
+ * All structures must be 4 UINT32's in size, no more, no less.
+ */
+
+/// For event ::HT_EVENT_HW_SYNCFLOOD
+typedef struct {
+  UINT32 Node;                   ///< The Node on which observed
+  UINT32 Link;                   ///< The Link on that Node which reported synch flood
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+} HT_EVENT_DATA_HW_SYNCFLOOD;
+
+/// For event ::HT_EVENT_HW_HTCRC
+typedef struct {
+  UINT32 Node;                   ///< The Node on which event is observed
+  UINT32 Link;                   ///< The Link on that Node which reported CRC error
+  UINT32 LaneMask;               ///< The CRC lane mask for the Link
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_HW_HT_CRC;
+
+/// For event ::HT_EVENT_NCOH_BUS_MAX_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Bus;                    ///< the current bus number
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_CFG_MAP_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_BUID_EXCEED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT16 CurrentBuid;            ///< the current available BUID
+  UINT16 UnitCount;              ///< the number of ids which would be consumed by this device
+} HT_EVENT_DATA_NCOH_BUID_EXCEED;
+
+/// For event ::HT_EVENT_NCOH_DEVICE_FAILED
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT32 AttemptedBuid;          ///< the BUID we tried to assign to that device
+} HT_EVENT_DATA_NCOH_DEVICE_FAILED;
+
+/// For event ::HT_EVENT_NCOH_AUTO_DEPTH
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain of the last device, zero is CPU host
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_NCOH_AUTO_DEPTH;
+
+/// For event ::HT_EVENT_OPT_REQUIRED_CAP_RETRY,
+///           ::HT_EVENT_OPT_REQUIRED_CAP_GEN3.
+typedef struct {
+  UINT32 Node;                   ///< the Node with this non-coherent chain
+  UINT32 Link;                   ///< the Link on that Node to this chain
+  UINT32 Depth;                  ///< the position on the chain, zero is CPU host
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_OPT_REQUIRED_CAP;
+
+/// For event ::HT_EVENT_OPT_UNUSED_LINKS
+typedef struct {
+  UINT32 NodeA;                  ///< One of the nodes connected
+  UINT32 LinkA;                  ///< its unusable link
+  UINT32 NodeB;                  ///< The other connected node
+  UINT32 LinkB;                  ///< its unusable link
+} HT_EVENT_DATA_OPT_UNUSED_LINKS;
+
+/// For event ::HT_EVENT_OPT_LINK_PAIR_EXCEED
+typedef struct {
+  UINT32 NodeA;                  ///< One of the nodes connected
+  UINT32 NodeB;                  ///< The other connected node
+  UINT32 MasterLink;             ///< NodeA's unusable Master link
+  UINT32 AltLink;                ///< NodeA's unusable Alternatelink
+} HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED;
+
+/// For event ::HT_EVENT_COH_NO_TOPOLOGY.
+/// There is no routing for this system's topology.
+typedef struct {
+  UINT32 TotalNodes;             ///< the number of Nodes in the unmatched topology
+  UINT32 Reserved1;              ///< Reserved.
+  UINT32 Reserved2;              ///< Reserved.
+  UINT32 Reserved3;              ///< Reserved.
+} HT_EVENT_DATA_COH_NO_TOPOLOGY;
+
+/// For event ::HT_EVENT_COH_PROCESSOR_TYPE_MIX
+typedef struct {
+  UINT32 Node;                   ///< the Node from which the incompatible family was found
+  UINT32 Link;                   ///< the Link to the incompatible Node
+  UINT32 TotalNodes;             ///< the number of Nodes found at that point
+  UINT32 Reserved1;              ///< Reserved.
+} HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX;
+
+/// For event ::HT_EVENT_COH_NODE_DISCOVERED
+typedef struct {
+  UINT32 Node;                   ///< the Node from which the new Node was found
+  UINT32 Link;                   ///< the Link to the new Node
+  UINT32 NewNode;                ///< the Node id of the newly discovered Node
+  UINT32 TempRoute;              ///< the new Node is temporarily at this id
+} HT_EVENT_DATA_COH_NODE_DISCOVERED;
+
+/// For event ::HT_EVENT_COH_MPCAP_MISMATCH
+typedef struct {
+  UINT32 Node;                   ///< the Node from which condition was observed
+  UINT32 Link;                   ///< the Link on the current Node
+  UINT32 SysMpCap;               ///< the current aggregate system capability (the minimum found so far)
+  UINT32 TotalNodes;             ///< the number of Nodes found, before this was observed
+} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
+
+/*----------------------------------------------------------------------------------------*/
+/* Event specific Notify functions.
+ */
+
+VOID
+NotifyAlertHwSyncFlood (
+  IN       UINT8        Node,
+  IN       UINT8        Link,
+  IN       STATE_DATA   *State
+  );
+
+VOID
+NotifyAlertHwHtCrc (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      LaneMask,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohBusMaxExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Bus,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohCfgMapExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohBuidExceed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       UINT8      Units,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorNcohDeviceFailed (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       UINT8      Id,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyInfoNcohAutoDepth (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptRequiredCapRetry (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptRequiredCapGen3 (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Depth,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptUnusedLinks (
+  IN       UINT32    NodeA,
+  IN       UINT32    LinkA,
+  IN       UINT32    NodeB,
+  IN       UINT32    LinkB,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyWarningOptLinkPairExceed (
+  IN       UINT32    NodeA,
+  IN       UINT32    NodeB,
+  IN       UINT32    MasterLink,
+  IN       UINT32    AltLink,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyErrorCohNoTopology (
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyFatalCohProcessorTypeMix (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyInfoCohNodeDiscovered (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      NewNode,
+  IN       UINT8      TempRoute,
+  IN       STATE_DATA *State
+  );
+
+VOID
+NotifyFatalCohMpCapMismatch (
+  IN       UINT8      Node,
+  IN       UINT8      Link,
+  IN       UINT8      Cap,
+  IN       UINT8      Nodes,
+  IN       STATE_DATA *State
+  );
+
+#endif /* _HT_NOTIFY_H_ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h
new file mode 100755
index 0000000000..de71cf47e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htPage.h
@@ -0,0 +1,64 @@
+/**
+ * @file
+ *
+ * Create outline and references for HyperTransport Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ ******************************************************************************
+ */
+
+/**
+ * @page htmain HyperTransport Component Documentation
+ *
+ * Additional documentation for the HyperTransport component consists of
+ *
+ * - Member Cross References
+ *   - @subpage instanceshtnb "HT Northbridge Method Instances"
+ * - Maintenance Guides:
+ *   - @subpage htimplintf "HT Internal Interface Implementation Guide"
+ *   - @subpage htimplfeat "HT Feature Implementation Guide"
+ *   - @subpage htimplnb   "HT Northbridge Implementation Guide"
+ *   - add here >>>
+ * - Design Guides:
+ *   - @subpage htgraphdesign "Graph Support Design"
+ *   - @subpage physicalsockethowto "How to Create a Physical System Socket Map"
+ *   - add here >>>
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f10/Proc/HT/htTopologies.h b/src/vendorcode/amd/agesa/f10/Proc/HT/htTopologies.h
new file mode 100755
index 0000000000..38b13f7ece
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f10/Proc/HT/htTopologies.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * Provide selection of available topologies.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  HyperTransport
+ * @e \$Revision: 44323 $   @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+* 
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+* 
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* 
+* ***************************************************************************
+*
+*/
+#ifndef _HT_TOPOLOGIES_H_
+#define _HT_TOPOLOGIES_H_
+
+extern CONST UINT8 ROMDATA amdHtTopologySingleNode[];
+extern CONST UINT8 ROMDATA amdHtTopologyDualNode[];
+extern CONST UINT8 ROMDATA amdHtTopologyThreeLine[];
+extern CONST UINT8 ROMDATA amdHtTopologyTriangle[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourLine[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourStar[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourSquare[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourKite[];
+extern CONST UINT8 ROMDATA amdHtTopologyFourFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyFiveFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySixFully[];
+extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[];
+extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[];
+extern CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySevenFully[];
+extern CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightFully[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[];
+extern CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[];
+extern CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[];
+
+#endif // _HT_TOPOLOGIES_H_