diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-07-13 16:43:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-07-15 14:17:00 +0200 |
| commit | 229f7cb6d660ad4063c9f65e3fabfff80583f281 (patch) | |
| tree | eaa627ceb717250c38f1bc6ca79868b331d12e23 /src/vendorcode/amd/agesa/f10/Proc/Mem/NB | |
| parent | 25f23f17bcb2bac9fb5af0f5d6d1d8c1c9ea16ff (diff) | |
| download | coreboot-229f7cb6d660ad4063c9f65e3fabfff80583f281.tar.xz | |
Add the AMD Family10 Agesa code
This change officially adds the Agesa code for the AMD Family 10
cpus. This code supports the G34 and C32 sockets.
Change-Id: Idae50417e530ad40a29fb6fff5b427f6b138126c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/95
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f10/Proc/Mem/NB')
64 files changed, 22296 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c new file mode 100755 index 0000000000..05d2272e66 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnParTrainc32.c @@ -0,0 +1,209 @@ +/** + * @file + * + * mnParTrainc32.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the C32 specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +BOOLEAN +STATIC +MemConstructRemoteNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_C32 * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockC32; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataC32 (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c new file mode 100755 index 0000000000..8a32fbcad6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.c @@ -0,0 +1,722 @@ +/** + * @file + * + * mns3c32.c + * + * C32 memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnc32.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3c32.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNS3C32_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstC32 ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegC32 ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncC32[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegC32}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorC32[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefC32 = { + 0, + (sizeof (S3PciPreSelfRefDescriptorC32) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorC32, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorC32[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefC32 = { + 0, + (sizeof (S3CPciPreSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorC32, + PciSpecialCaseFuncC32 +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorC32[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + + // DCT1 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefC32 = { + 0, + (sizeof (S3CPciPostSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorC32, + PciSpecialCaseFuncC32 +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorC32[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefC32 = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorC32) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorC32, + NULL +}; + +VOID *MemS3RegListC32[] = { + (VOID *)&S3PciPreSelfRefC32, + NULL, + (VOID *)&S3CPciPreSelfRefC32, + (VOID *)&S3CPciPostSelfRefC32, + (VOID *)&S3MSRPreSelfRefC32, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemS3ResumeConstructNBBlockC32 ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableC32 (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; + NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for C32 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[PCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_C32 + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CPCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_C32 + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[MSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_C32 + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CMSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_C32 + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstC32 ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListC32) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListC32[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListC32[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegC32 ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_C32); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegC32[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_C32); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegC32[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h new file mode 100755 index 0000000000..a42d0033f3 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnS3c32.h @@ -0,0 +1,83 @@ +/** + * @file + * + * mnS3c32.h + * + * S3 resume memory related function for C32. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _MNS3C32_H_ +#define _MNS3C32_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of C32 +typedef enum { + PCI_LST_ESR_C32, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_C32, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_C32, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_C32, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_C32, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_C32, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_C32, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_C32 ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDC32; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3C32_H_ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c new file mode 100755 index 0000000000..e861ad236b --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.c @@ -0,0 +1,454 @@ +/** + * @file + * + * mnc32.c + * + * Common Northbridge functions for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 13446 $ @e \$Date: 2009-05-12 04:57:49 +0800 (Tue, 12 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataC32 (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableC32 (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_C32; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_256B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0x1FF; + NBPtr->DefDctSelIntLvAddr = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->InitializeMCT = MemNInitializeMctNb; + NBPtr->FinalizeMCT = MemNFinalizeMctC32; + NBPtr->SendMrsCmd = MemNSendMrsCmdC32; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternC32; + NBPtr->ReadPattern = MemNReadPatternC32; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = MemNAutoConfigC32; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = MemNDefFalseNb; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingC32; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingC32; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; + NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitC32; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNInitPhyComp = MemNInitPhyCompC32; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecC32; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitC32; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[CheckODTControls] = TRUE; + NBPtr->IsSupported[CheckDummyCLRead] = TRUE; + NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; + + NBPtr->FamilySpecificHook[ForceLvDimmVoltage] = MemNForceLvDimmVoltageC32; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsC32 ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; + // + + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h new file mode 100755 index 0000000000..803e56a8b4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnc32.h @@ -0,0 +1,195 @@ +/** + * @file + * + * mnc32.h + * + * Northbridge C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNC32_H_ +#define _MNC32_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_C32 2 +#define MAX_DCTS_PER_NODE_C32 2 +#define MAX_CHANNELS_PER_DCT_C32 1 +#define MAX_NODES_SUPPORTED_C32 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemConstructNBBlockC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsC32 ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNFinalizeMctC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAutoConfigC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitPhyCompC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +InitNBRegTableC32 ( + IN OUT TSEFO NBRegTable[] + ); + +UINT8 +MemNGetSocketRelativeChannelC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ); + +BOOLEAN +MemNIsIdSupportedC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +VOID +MemNBeforeDramInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnDLLShutDownC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNBeforePlatformSpecC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforeDQSTrainingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNForceLvDimmVoltageC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *MemMainPtr + ); + +#endif /* _MNC32_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c new file mode 100755 index 0000000000..fad96bc06f --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mndctc32.c @@ -0,0 +1,405 @@ +/** + * @file + * + * mndctc32.c + * + * Northbridge DCT support for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mnc32.h" +#include "merrhdl.h" +#include "cpuFamRegisters.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNDCTC32_FILECODE + +extern BUILD_OPT_CFG UserOptions; +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_ERROR may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +MemNAutoConfigC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 PowerDownMode; + UINT32 Value32; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + //It is recommended that these bits remain in the default state. + //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + //====================================================================== + // Build Dram Config Misc 2 Register Value + //====================================================================== + // + // + // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms + // + if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { + MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); + } + // + // DTaxTxFifpWrDly + // + Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); + if ((Value32 >= 2) && (Value32 <= 5)) { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); + } + + // + // ProgOdtEn + // + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); + } else { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); + } + // + // OdtSwizzle + // + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode == 1) { + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + } + } + + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + //Set PllLockTime and DllLockTime to default. + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Enable DLL Shut down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNEnDLLShutDownC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Force LvDimm voltage to 1.5V for D0 part + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemMainPtr - Pointer to MEM_MAIN_DATA_BLOCK + * + * @return TRUE + */ +BOOLEAN +MemNForceLvDimmVoltageC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *MemMainPtr + ) +{ + MEM_PARAMETER_STRUCT *ParameterPtr; + MEM_SHARED_DATA *mmSharedPtr; + + mmSharedPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->mmSharedPtr; + ParameterPtr = ((MEM_MAIN_DATA_BLOCK *) MemMainPtr)->MemPtr->ParameterListPtr; + + if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D0) != 0) { + IDS_HDT_CONSOLE ("\n\nC32 D0 on socket %d.\n", NBPtr->MCTPtr->SocketId); + if ((1 & mmSharedPtr->VoltageMap) != 0) { + IDS_HDT_CONSOLE ("\nDimms are 1.5V capable. Adjust voltage to 1.5V.\n"); + ParameterPtr->DDR3Voltage = VOLT1_5; + } else { + if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_LVDIMM_VOLT1_5_SUPPORT, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) { + IDS_HDT_CONSOLE ("\nDimms are not 1.5V capable. Adjust voltage to 1.5V based on customer's choice.\n\n"); + ParameterPtr->DDR3Voltage = VOLT1_5; + } else { + IDS_HDT_CONSOLE ("\nDimms are not 1.5V capable. Do not adjust voltage based on customer's choice.\n\n"); + PutEventLog (AGESA_FATAL, MEM_ERROR_VDDIO_UNSUPPORTED, NBPtr->Node, 0, 0, 0, &(NBPtr->MemPtr->StdHeader)); + SetMemError (AGESA_FATAL, NBPtr->MCTPtr); + ASSERT (FALSE); + } + } + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c new file mode 100755 index 0000000000..e56e2ab37c --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnflowc32.c @@ -0,0 +1,131 @@ +/** + * @file + * + * mnflowc32.c + * + * C32 initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnc32.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNFLOWC32_FILECODE +/* features */ + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledC32[f] != NULL); + if (memPlatSpecFFInstalledC32[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c new file mode 100755 index 0000000000..f75ef11389 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnidendimmc32.c @@ -0,0 +1,133 @@ +/** + * @file + * + * mnidendimmc32.c + * + * C32 northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNIdentifyDimmConstructorC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32; + NBPtr->DctCount = MAX_DCTS_PER_NODE_C32; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableC32 (NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c new file mode 100755 index 0000000000..1631cca5da --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnmctc32.c @@ -0,0 +1,150 @@ +/** + * @file + * + * mnmctc32.c + * + * Northbridge C32 MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNMCTC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + UINT16 Speed; + UINT32 ExtMctCfgLoRegVal; + + MemPtr = NBPtr->MemPtr; + Speed = NBPtr->DCTPtr->Timings.Speed; + MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); + + ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); + ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; + + ExtMctCfgLoRegVal &= 0x0FFFFFFF; + if (Speed == DDR667_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x40000000; + } else if (Speed == DDR800_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x50000000; + } else if (Speed == DDR1066_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x60000000; + } else if (Speed == DDR1333_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x80000000; + } else { + ExtMctCfgLoRegVal |= 0x90000000; + } + MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c new file mode 100755 index 0000000000..22e6bab12e --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnotc32.c @@ -0,0 +1,235 @@ +/** + * @file + * + * mnotc32.c + * + * Northbridge Non-SPD timings for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 13435 $ @e \$Date: 2009-05-12 02:26:55 +0800 (Tue, 12 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNOTC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +STATIC +MemNGetODTDelaysC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingC32 (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownC32 (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingC32 (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownC32 (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings in PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the ODT delays + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +UINT32 +STATIC +MemNGetODTDelaysC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Ld; + UINT32 ODTDelays; + // + // On revision D processors, the BIOS must additionally configure the ODT pattern + // and the ODT switching delays. + // + // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. + // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. + // -Value of 2, BL = 4 else assume BL=8. + // -Initialize ODTDelays based on BL value + // -WrOdtOnDuration [14:12] = BL / 2 + 1 + // -WrOdtTrnOnDly [10:8] = 0 + // -RdOdtOnDuration [6:4] = BL / 2 + 1 + // + ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; + + // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) + // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] + Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if (Ld < 0) { + Ld = 0; + } + if (Ld > 7) { + Ld = 7; + } + ODTDelays += Ld; + return ODTDelays; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c new file mode 100755 index 0000000000..d9d2318f51 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnphyc32.c @@ -0,0 +1,217 @@ +/** + * @file + * + * mnphyc32.c + * + * Northbridge Phy support for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mnc32.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNPHYC32_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; + CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; + CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; + CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; + UINT8 i; + UINT8 j; + UINT8 CurrDct; + CurrDct = NBPtr->Dct; + // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp will be cleared after Dram init has completed + // + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + MemUWait10ns (500, NBPtr->MemPtr); + MemNSwitchDCTNb (NBPtr, CurrDct); + + // 3. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the + // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. + // + // 4. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding + // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, + // D3Cmp2PCal]. + // + j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); + i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); + + MemNSwitchDCTNb (NBPtr, 0); + ASSERT (j <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); + + if ((NBPtr->ChannelPtr->Dimms == 3) && + ((NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) || + (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY))) { + // + // Special Case for 3 Dimms @ 800MHz or 1066MHz + // + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 1); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 1); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 1); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 1); + } else { + ASSERT (i <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); + } + MemNSwitchDCTNb (NBPtr, CurrDct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDQSTrainingC32 ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 ChipSel; + UINT32 TestAddrRJ16; + UINT32 RealAddr; + + MemTBeginTraining (NBPtr->TechPtr); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { + + RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); + + MemUDummyCLRead (RealAddr); + + MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); + MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns + MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); + MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us + MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); + break; + } + } + } + if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { + if (!NBPtr->MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); + } + if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { + MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); + } + } + } + + MemTEndTraining (NBPtr->TechPtr); + + MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1); +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c new file mode 100755 index 0000000000..60c5c3f0bf --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnprotoc32.c @@ -0,0 +1,62 @@ +/** + * @file + * + * mnprotoc32.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 7735 $ @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + + +#include "AGESA.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNPROTOC32_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c new file mode 100755 index 0000000000..6469da7cd7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/C32/mnregc32.c @@ -0,0 +1,571 @@ +/** + * @file + * + * mnregc32.c + * + * Common Northbridge register related functions for C32 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/C32) + * @e \$Revision: 13446 $ @e \$Date: 2009-05-12 04:57:49 +0800 (Tue, 12 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnc32.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_C32_MNREGC32_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedC32 + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a C32. + * @return FALSE - This node is not a C32. + * + */ +BOOLEAN +MemNIsIdSupportedC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + if ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*-----------------------------------------------------------------------------*/ +/** + * This function calculates the memory channel index relative to the + * socket, taking the Die number, the Dct, and the channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct + * @param[in] Channel + * + */ +UINT8 +MemNGetSocketRelativeChannelC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ) +{ + return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_C32) + Dct); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldC32 ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldC32 (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldC32 (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableC32 ( + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFF3X188B8); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c new file mode 100755 index 0000000000..0feabbd9ca --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnParTrainDa.c @@ -0,0 +1,210 @@ +/** + * @file + * + * mnParTrainDa.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the Deerhound specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/HCTRN) + * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDA; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataDA (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c new file mode 100755 index 0000000000..1e4e328d32 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.c @@ -0,0 +1,739 @@ +/** + * @file + * + * mns3da.c + * + * DA memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnda.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3da.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNS3DA_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDA ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegDA ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncDA[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDA}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDA[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDA = { + 0, + (sizeof (S3PciPreSelfRefDescriptorDA) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorDA, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDA[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Dll regulator disable + {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDA = { + 0, + (sizeof (S3CPciPreSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorDA, + PciSpecialCaseFuncDA +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDA[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDA = { + 0, + (sizeof (S3CPciPostSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorDA, + PciSpecialCaseFuncDA +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDA[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDA = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorDA) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorDA, + NULL +}; + +VOID *MemS3RegListDA[] = { + (VOID *)&S3PciPreSelfRefDA, + NULL, + (VOID *)&S3CPciPreSelfRefDA, + (VOID *)&S3CPciPostSelfRefDA, + (VOID *)&S3MSRPreSelfRefDA, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockDA ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDA (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for DA + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDA ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListDA) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListDA[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListDA[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegDA ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegDA[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegDA[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h new file mode 100755 index 0000000000..cc65af658f --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnS3da.h @@ -0,0 +1,83 @@ +/** + * @file + * + * mnS3da.h + * + * S3 resume memory related function for DA. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _MNS3DA_H_ +#define _MNS3DA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of DA +typedef enum { + PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDA; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3DA_H_ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c new file mode 100755 index 0000000000..3c6242b502 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.c @@ -0,0 +1,460 @@ +/** + * @file + * + * mnda.c + * + * Common Northbridge functions for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNDA_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; + } + + MemNInitNBDataDA (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDA (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->InitializeMCT = MemNInitializeMctNb; + NBPtr->FinalizeMCT = MemNFinalizeMctDA; + NBPtr->SendMrsCmd = MemNSendMrsCmdDA; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDA; + NBPtr->ReadPattern = MemNReadPatternDA; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDA; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = MemNDefFalseNb; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingDA; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckDllStdBy] = TRUE; + NBPtr->IsSupported[CheckDynamicDramTerm] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[CheckDllRegDis] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsDA ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h new file mode 100755 index 0000000000..3109cdd761 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnda.h @@ -0,0 +1,193 @@ +/** + * @file + * + * mnda.h + * + * Northbridge DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNDA_H_ +#define _MNDA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_DA 2 +#define MAX_DCTS_PER_NODE_DA 2 +#define MAX_CHANNELS_PER_DCT_DA 1 +#define MAX_NODES_SUPPORTED_DA 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsDA ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNFinalizeMctDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNAutoConfigDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemPNodeMemBoundaryDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ); + +VOID +InitNBRegTableDA ( + IN OUT TSEFO NBRegTable[] + ); + +VOID +MemNBeforeDramInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforePlatformSpecDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNIsIdSupportedDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +BOOLEAN +MemNChangeAvgValue3DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNChangeAvgValue8DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnDLLShutDownDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNCapSpeedBatteryLifeDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif /* _MNDA_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c new file mode 100755 index 0000000000..da8ed6c4c6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mndctda.c @@ -0,0 +1,459 @@ +/** + * @file + * + * mndctda.c + * + * Northbridge DA DCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnda.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "Filecode.h" +#include "GeneralServices.h" +#include "cpuFamilyTranslation.h" +#include "cpuRegisters.h" +#include "mport.h" +#include "F10PackageType.h" +#define FILECODE PROC_MEM_NB_DA_MNDCTDA_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + + //Setting the reset value of Phy DLL standby and shutdown registers. + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + //Set PllLockTime and DllLockTime to default. + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + + //Clear PHY PLL Control Register before doing fence training and reset DLL + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0x00002000); + MemNSetBitFieldNb (NBPtr, BFPhyDLLControl, 0); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +memNAutoConfigDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + // For DDR3 Registered Dimms + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Change Average Value of 3 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +BOOLEAN +MemNChangeAvgValue3DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/** + * + * + * Change Average Value of 8 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +BOOLEAN +MemNChangeAvgValue8DA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C1) != 0) { + return TRUE; + } else { + return FALSE; + } +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Enable DLL Shut down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNEnDLLShutDownDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function caps speed based on batter life check. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +VOID +MemNCapSpeedBatteryLifeDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 SupportedFreq[] = { + DDR1600_FREQUENCY, + DDR1333_FREQUENCY, + DDR1066_FREQUENCY, + DDR800_FREQUENCY, + DDR667_FREQUENCY, + DDR533_FREQUENCY, + DDR400_FREQUENCY + }; + UINT32 NBFreq; + UINT8 j; + UINT16 DdrFreq; + UINT32 ProcessorPackageType; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + FamilySpecificServices = NULL; + DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz + GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader)); + if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &(NBPtr->MemPtr->StdHeader))) { + ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader)); + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100; // Calculate the Nb P1 frequency (NbFreq / 2) + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { + // Pick Max MEMCLK that is less than or equal to (NCLK_P1 / 2) + DdrFreq = SupportedFreq[j]; + break; + } + } + if ((ProcessorPackageType != PACKAGE_TYPE_S1G3_S1G4) || + (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife)) { + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + } else { + PutEventLog (AGESA_WARNING, MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; // Calculate the Nb P0 frequency + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { + // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2) + DdrFreq = SupportedFreq[j]; + break; + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + } + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 4); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 1); + } else { + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; // Calculate the Nb P0 frequency + for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) { + if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) { + // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2) + DdrFreq = SupportedFreq[j]; + break; + } + } + if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) { + NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq; + } + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c new file mode 100755 index 0000000000..59b1732e25 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnflowda.c @@ -0,0 +1,135 @@ +/** + * @file + * + * mnflowda.c + * + * Deerhound initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnda.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNFLOWDA_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledDA[f] != NULL); + if (memPlatSpecFFInstalledDA[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c new file mode 100755 index 0000000000..de9fb85196 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnidendimmda.c @@ -0,0 +1,134 @@ +/** + * @file + * + * mnidendimmda.c + * + * DA northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + * + */ + +BOOLEAN +MemNIdentifyDimmConstructorDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableDA (NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c new file mode 100755 index 0000000000..b2009c3b21 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnmctda.c @@ -0,0 +1,154 @@ +/** + * @file + * + * mnmctda.c + * + * Northbridge DA MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNMCTDA_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1); + MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0); + MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0); + MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1); + // Recommended settings for F2x11C + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16); + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0); + MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1); + // For power saving + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + if (NBPtr->ChannelPtr->Dimmx4Present == 0) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80)); + } + if (!NBPtr->MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0830, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0830) | 0x10)); + } + MemNSetBitFieldNb (NBPtr, BFPhy0x0D07812F, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D07812F) | 0x01)); + } + } + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c new file mode 100755 index 0000000000..8b701549a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnotda.c @@ -0,0 +1,195 @@ +/** + * @file + * + * mnotda.c + * + * Northbridge Non-SPD timings for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 10082 $ @e \$Date: 2008-12-17 06:21:26 -0600 (Wed, 17 Dec 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNOTDA_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNPowerDownCtlDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingDA (NBPtr); // Set DA Timings + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownDA (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingDA (NBPtr); // Set DA Timings + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownDA (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings into the PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlDA ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} + + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c new file mode 100755 index 0000000000..9541374188 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnprotoda.c @@ -0,0 +1,81 @@ +/** + * @file + * + * mnprotoda.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes Node memory 1GB boundary alignment. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *NodeSysLimit - Pointer to the NodeSysLimit + * + */ + +VOID +MemPNodeMemBoundaryDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ) +{ + if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) { + // only apply to DDR2. + if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) { + // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node + *NodeSysLimit += 1; + *NodeSysLimit &= 0xFFFFC000; + *NodeSysLimit -= 1; + } + } +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c new file mode 100755 index 0000000000..2ae2b87846 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DA/mnregda.c @@ -0,0 +1,554 @@ +/** + * @file + * + * mnregda.c + * + * Common Northbridge register related functions for DA + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DA) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DA_MNREGDA_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedDA + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a RB. + * @return FALSE - This node is not a RB. + * + */ +BOOLEAN +MemNIsIdSupportedDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + + if ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldDA ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldDA (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldDA (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableDA ( + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFF3X188B8); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 0, 0, BFIntLvRgnSwapEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 9, 3, BFIntLvRgnBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 17, 11, BFIntLvRgnLmtAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 26, 20, BFIntLvRgnSize); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 31, 0, BFPhyDLLControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F0C); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D040F3E); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D042F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D042F3E); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D048F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D048F3E); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D04DF3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D04DF3E); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0F13, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0F13); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0830); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D07812F, _NOT_USED_, _NOT_USED_, BFPhy0x0D07812F); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c new file mode 100755 index 0000000000..6cce298c66 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnParTrainDr.c @@ -0,0 +1,211 @@ +/** + * @file + * + * mnParTrainDr.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the Deerhound specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/HCTRN) + * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE + +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +BOOLEAN +MemFParallelTrainingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_DR * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDR; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataDr (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c new file mode 100755 index 0000000000..ddd4ef38fa --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.c @@ -0,0 +1,707 @@ +/** + * @file + * + * mns3dr.c + * + * DR memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mndr.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3dr.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNS3DR_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDr ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegDr ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncDr[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDr}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDr[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDr = { + 0, + (sizeof (S3PciPreSelfRefDescriptorDr) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorDr, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDr[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDr = { + 0, + (sizeof (S3CPciPreSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorDr, + PciSpecialCaseFuncDr +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDr[] = { + // DCT0 + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + + // DCT1 + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDr = { + 0, + (sizeof (S3CPciPostSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorDr, + PciSpecialCaseFuncDr +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDr[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDr = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorDr) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorDr, + NULL +}; + +VOID *MemS3RegListDr[] = { + (VOID *)&S3PciPreSelfRefDr, + NULL, + (VOID *)&S3CPciPreSelfRefDr, + (VOID *)&S3CPciPostSelfRefDr, + (VOID *)&S3MSRPreSelfRefDr, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockDr ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDr (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DR; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = FALSE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDr; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for DR + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[PCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DR + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CPCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DR + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[MSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DR + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CMSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DR + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstDr ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListDr) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListDr[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListDr[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegDr ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DR); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegDr[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DR); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegDr[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h new file mode 100755 index 0000000000..d2607ca962 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnS3dr.h @@ -0,0 +1,83 @@ +/** + * @file + * + * mnS3dr.h + * + * S3 resume memory related function for DR. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _MNS3DR_H_ +#define _MNS3DR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of DR +typedef enum { + PCI_LST_ESR_DR, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DR, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DR, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DR, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DR, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DR, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DR, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DR, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDr; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3DR_H_ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c new file mode 100755 index 0000000000..52a589ecb6 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndctdr.c @@ -0,0 +1,509 @@ +/** + * @file + * + * mndctdr.c + * + * Northbridge DR DCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "cpuFamRegisters.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mndr.h" +#include "merrhdl.h" +#include "OptionMemory.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNDCTDR_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemTCtlOnDimmMirrorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BOOLEAN SetFlag + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +memNAutoConfigDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0); + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS or DDR2 that support parity + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) || (RefPtr->EnableParity)) { + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + } + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + // For DDR3 Registered Dimms + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN ClearODM; + + ClearODM = FALSE; + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) { + if (MemNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) { + // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS + MemTCtlOnDimmMirrorDr (NBPtr, FALSE); + ClearODM = TRUE; + } + } + + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE ("\t\t\tCS%d MR%d %04x\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); + + if (ClearODM) { + // Restore ODM if necessary + MemTCtlOnDimmMirrorDr (NBPtr, TRUE); + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function disables/enables F2x[1, 0][5C:40][OnDimmMirror] + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] SetFlag - Enable or disable flag - TRUE - Enable, FALSE - DISABLE + * + */ + +VOID +STATIC +MemTCtlOnDimmMirrorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BOOLEAN SetFlag + ) +{ + UINT8 Chipsel; + UINT32 CSBaseAddrReg; + + for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) { + CSBaseAddrReg = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel); + if ((CSBaseAddrReg & 1) == 1) { + if (SetFlag && ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) { + CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror); + } else { + CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror); + } + MemNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function adjusts Avg PRE value of Phy fence training according to specific CPU family. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Value16 - Pointer to the value that we want to adjust + * + */ + +VOID +MemNPFenceAdjustDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ) +{ + if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) { + *Value16 += 5; //for RB C0, the Avg PRE value is subtracted by 3 only. + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function uses calculated values from DCT.Timings structure to + * program its RB registers. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramCycTimingsDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CTENTRY DDR3TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 4, 12, 4, 2}, + {BFTrcd, 5, 12, 5, 2}, + {BFTrp, 5, 12, 5, 2}, + {BFTrtp, 4, 7, 4, 2}, + {BFTras, 15, 30, 15, 2}, + {BFTrc, 11, 42, 11, 2}, + {BFTwrDDR3, 5, 12, 4, 2}, + {BFTrrd, 4, 7, 4, 2}, + {BFTwtr, 4, 7, 4, 2}, + {BFFourActWindow, 16, 32, 14, 1} + }; + + CTENTRY DDR2TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 3, 7, 1, 2}, + {BFTrcd, 3, 6, 3, 2}, + {BFTrp, 3, 6, 3, 4}, + {BFTrtp, 2, 3, 2, 4}, + {BFTras, 5, 18, 3, 2}, + {BFTrc, 11, 26, 11, 2}, + {BFTwr, 3, 6, 3, 2}, + {BFTrrd, 2, 5, 2, 2}, + {BFTwtr, 5, 8, 4, 2}, + {BFFourActWindow, 8, 20, 7, 2} + }; + + CTENTRY *TmgAdjTab; + DCT_STRUCT *DCTPtr; + UINT8 *MiniMaxTmg; + UINT8 *MiniMaxTrfc; + UINT8 Value8; + UINT8 j; + UINT8 BurstMode; + BIT_FIELD_NAME BitField; + + DCTPtr = NBPtr->DCTPtr; + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + TmgAdjTab = DDR3TmgAdjTab; + } else if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) { + // DDR2-1066 uses DDR3 table but differs in tCL + TmgAdjTab = DDR3TmgAdjTab; + TmgAdjTab[0].Min = 3; + TmgAdjTab[0].Max = 7; + TmgAdjTab[0].Bias = 1; + } else { + TmgAdjTab = DDR2TmgAdjTab; + } + + MiniMaxTmg = &DCTPtr->Timings.CasL; + for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { + BitField = TmgAdjTab[j].BitField; + + if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { + MiniMaxTmg[j] = TmgAdjTab[j].Min; + } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { + MiniMaxTmg[j] = TmgAdjTab[j].Max; + } + + Value8 = (UINT8) MiniMaxTmg[j]; + + if (BitField == BFTwrDDR3) { + Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8; + } else if (BitField == BFTrtp) { + Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6; + } + + Value8 = Value8 - TmgAdjTab[j].Bias; + Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; + + MemNSetBitFieldNb (NBPtr, BitField, Value8); + } + + MiniMaxTrfc = &DCTPtr->Timings.Trfc0; + for (j = 0; j < 4; j++) { + MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); + } + + MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us + + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + //====================================================================== + // DDR3 additional settings + //====================================================================== + + MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? + (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0)); + + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF); + + MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); + + // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) + MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); + + // burst length control + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2); + } + + // ASR=1, auto self refresh; SRT=0 + MemNSetBitFieldNb (NBPtr, BFASR, 1); + } else { + //====================================================================== + // DDR2 additional settings + //====================================================================== + + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0xFF77); + + BurstMode = UserOptions.CfgUseBurstMode; + IDS_OPTION_HOOK (IDS_BURST_LENGTH32, &BurstMode, &(NBPtr->MemPtr->StdHeader)); + if (BurstMode) { + if (!NBPtr->MCTPtr->GangedMode) { + NBPtr->SetBitField (NBPtr, BFBurstLength32, 1); + } + } + } +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c new file mode 100755 index 0000000000..af67da104b --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.c @@ -0,0 +1,452 @@ +/** + * @file + * + * mndr.c + * + * Common Northbridge functions for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "mu.h" +#include "merrhdl.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNDR_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataDr (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDr (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DR; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DR; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR; + NBPtr->DefDctSelIntLvAddr = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->InitializeMCT = MemNInitializeMctNb; + NBPtr->FinalizeMCT = MemNFinalizeMctDr; + NBPtr->SendMrsCmd = MemNSendMrsCmdDr; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDr; + NBPtr->ReadPattern = MemNReadPatternDr; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDr; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = MemNDefFalseNb; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsDr; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = (BOOLEAN (*) (MEM_NB_BLOCK *)) MemMDefRet; //@attention - due to build issue with MemNOtherTimingDr + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDr; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDr; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPPhyFenceTrainingNb = MemPPhyFenceTrainingDr; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDr; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDr; + NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustDr; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[CheckDynamicDramTerm] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsDR ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; + // + + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h new file mode 100755 index 0000000000..b630071def --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mndr.h @@ -0,0 +1,188 @@ +/** + * @file + * + * mndr.h + * + * Northbridge DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNDR_H_ +#define _MNDR_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_DR 2 +#define MAX_DCTS_PER_NODE_DR 2 +#define MAX_CHANNELS_PER_DCT_DR 1 +#define MAX_NODES_SUPPORTED_DR 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockDR ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsDR ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNFinalizeMctDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +memNAutoConfigDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +MemPNodeMemBoundaryDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ); + +VOID +InitNBRegTableDr ( + IN OUT TSEFO NBRegTable[] + ); + +BOOLEAN +MemNIsIdSupportedDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +VOID +MemNBeforeDramInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforePlatformSpecDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemPPhyFenceTrainingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNPFenceAdjustDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ); + +VOID +MemNProgramCycTimingsDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MNDR_H_ */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c new file mode 100755 index 0000000000..b89a8bb312 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnflowdr.c @@ -0,0 +1,137 @@ +/** + * @file + * + * mnflowdr.c + * + * Deerhound initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mndr.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNFLOWDR_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledDR[f] != NULL); + if (memPlatSpecFFInstalledDR[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c new file mode 100755 index 0000000000..19df019650 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnidendimmdr.c @@ -0,0 +1,134 @@ +/** + * @file + * + * mnidendimmdr.c + * + * DR northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + * + */ + +BOOLEAN +MemNIdentifyDimmConstructorDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DR; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableDr (NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c new file mode 100755 index 0000000000..615c005187 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnmctdr.c @@ -0,0 +1,141 @@ +/** + * @file + * + * mnmctdr.c + * + * Northbridge DR MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "mu.h" +#include "OptionMemory.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNMCTDR_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1); + MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0); + MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0); + MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1); + // Recommended settings for F2x11C + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16); + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0); + MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1); + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c new file mode 100755 index 0000000000..7dbcd12f60 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnotdr.c @@ -0,0 +1,194 @@ +/** + * @file + * + * mnotdr.c + * + * Northbridge Non-SPD timings for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNOTDR_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNPowerDownCtlDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingDR (NBPtr); // Set DR Timings + MemNPowerDownCtlNb (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingDR (NBPtr); // Set DR Timings + MemNPowerDownCtlNb (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings into the PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNPowerDownCtlDR ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} + + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c new file mode 100755 index 0000000000..ee2ada03f7 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnprotodr.c @@ -0,0 +1,164 @@ +/** + * @file + * + * mnprotodr.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + + +#include "AGESA.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNPROTODR_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNTrainFenceWHardCodeValDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function conditionally executes specific Phy fence training function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemPPhyFenceTrainingDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) { + //DDR2 specific. + if (NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) { + MemNTrainFenceWHardCodeValDr (NBPtr); + } else { + MemNTrainPhyFenceNb (NBPtr); + } + } else { + //DDR3 specific. + MemNTrainPhyFenceNb (NBPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes hardcoded Phy fence training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNTrainFenceWHardCodeValDr ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 CurDct; + UINT16 Speed; + + CurDct = NBPtr->Dct; + if (NBPtr->MCTPtr->NodeMemSize) { + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + Speed = NBPtr->DCTPtr->Timings.Speed; + NBPtr->SetBitField (NBPtr, BFPhyFence, ((Speed == DDR800_FREQUENCY) || (Speed == DDR1066_FREQUENCY)) ? 20 : 20); + NBPtr->SetBitField (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0); + NBPtr->SetBitField (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl); + NBPtr->SetBitField (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg); + } + } + + NBPtr->SwitchDCT (NBPtr, CurDct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes Node memory 1GB boundary alignment. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *NodeSysLimit - Pointer to the NodeSysLimit + * + */ + +VOID +MemPNodeMemBoundaryDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT32 *NodeSysLimit + ) +{ + if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) { + // only apply to DDR2. + if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) { + // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node + *NodeSysLimit += 1; + *NodeSysLimit &= 0xFFFFC000; + *NodeSysLimit -= 1; + } + } +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c new file mode 100755 index 0000000000..c2fe73ccaa --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/DR/mnregdr.c @@ -0,0 +1,530 @@ +/** + * @file + * + * mnregdr.c + * + * Common Northbridge register related functions for DR + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/DR) + * @e \$Revision: 13216 $ @e \$Date: 2009-05-06 18:20:12 -0500 (Wed, 06 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mndr.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_DR_MNREGDR_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedDr + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a RB. + * @return FALSE - This node is not a RB. + * + */ +BOOLEAN +MemNIsIdSupportedDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + + if ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL + | AMD_F10_BL_ALL + | AMD_F10_DA_ALL )) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldDr ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldDr (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldDr (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableDr ( + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFF3X188B8); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c new file mode 100755 index 0000000000..9ae62d6862 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnParTrainHy.c @@ -0,0 +1,213 @@ +/** + * @file + * + * mnParTrainHy.c + * + * Feature which performs Memory DQS training on each node with each node training + * its own memory through code running on a core in the associated processor. + * This way memory can be trained in parallel by more than one processor. + * + * This file contains the Hydra specific parallel training function. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Feat/HCTRN) + * @e \$Revision: 6516 $ @e \$Date: 2008-06-24 06:06:40 -0500 (Tue, 24 Jun 2008) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuServices.h" +#include "GeneralServices.h" +#include "cpuApicUtilities.h" +#include "mfParallelTraining.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE +/*----------------------------------------------------------------------------- +* EXPORTED FUNCTIONS +* +*----------------------------------------------------------------------------- +*/ +#ifdef UNUSED_CODE +BOOLEAN +STATIC +MemConstructRemoteNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr +); +#endif +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is the training function which set up the environment for remote + * training on the ap and launches the remote routine. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Launch training on AP successfully. + * @return FALSE - Fail to launch training on AP. + */ +#ifdef UNUSED_CODE +STATIC BOOLEAN +MemFParallelTrainingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + DIE_STRUCT *MCTPtr; + REMOTE_TRAINING_ENV *EnvPtr; + AP_TASK TrainingTask; + UINT8 Socket; + UINT8 Module; + UINT8 APCore; + UINT8 p; + UINT32 LowCore; + UINT32 HighCore; + UINT32 BspSocket; + UINT32 BspModule; + UINT32 BspCore; + AGESA_STATUS Status; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + UINT16 MctDataSize; + StdHeader = &(NBPtr->MemPtr->StdHeader); + MCTPtr = NBPtr->MCTPtr; + Socket = MCTPtr->SocketId; + Module = MCTPtr->DieId; + + // + // Allocate buffer for REMOTE_TRAINING_ENV + // + MctDataSize = MAX_DCTS_PER_NODE_HY * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) { + EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV); + + // + // Setup Remote training environment + // + LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader); + LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader); + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p]; + } + EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling; + EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY; + EnvPtr->FeatPtr = NBPtr->FeatPtr; + EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase; + EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo; + EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize; + EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit; + EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations; + EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration; + + LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader); + + // + // Get Socket, Core of the BSP + // + IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status); + EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF); + EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF); + + // + // Set up the remote task structure + // + TrainingTask.DataTransfer.DataPtr = EnvPtr; + TrainingTask.DataTransfer.DataSizeInDwords = (AllocHeapParams.RequestedBufferSize + 3) / 4; + TrainingTask.DataTransfer.DataTransferFlags = 0; + TrainingTask.ExeFlags = 0; + TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining; + + // + // Get Target AP Core + // + GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); + APCore = (UINT8) (LowCore & 0x000000FF); + + // + // Launch Remote Training + // + ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader); + + HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader); + + return TRUE; + } else { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV" + return FALSE; + } +} + +BOOLEAN +STATIC +MemConstructRemoteNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN DIE_STRUCT *MCTPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr + ) +{ + NBPtr->MCTPtr = MCTPtr; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + + MemNInitNBDataHy (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} +#endif diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c new file mode 100755 index 0000000000..a4d3377f21 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.c @@ -0,0 +1,738 @@ +/** + * @file + * + * mns3hy.c + * + * HY memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnhy.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3hy.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstHy ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3ExitSelfRefRegHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegHy ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = { + 0, + (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorHy, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = { + 0, + (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorHy, + PciSpecialCaseFuncHy +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = { + 0, + (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorHy, + PciSpecialCaseFuncHy +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FFull}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000ull}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000ull}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFFull} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorHy, + NULL +}; + +VOID *MemS3RegListHy[] = { + (VOID *)&S3PciPreSelfRefHy, + NULL, + (VOID *)&S3CPciPreSelfRefHy, + (VOID *)&S3CPciPostSelfRefHy, + (VOID *)&S3MSRPreSelfRefHy, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemS3ResumeConstructNBBlockHy ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ); + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemS3ResumeConstructNBBlockHy ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableHy (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; + NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for HY + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstHy ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListHy[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListHy[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegHy ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_HY); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegHy[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_HY); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegHy[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h new file mode 100755 index 0000000000..88c293e9d0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnS3hy.h @@ -0,0 +1,83 @@ +/** + * @file + * + * mnS3hy.h + * + * S3 resume memory related function for HY. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _MNS3HY_H_ +#define _MNS3HY_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of HY +typedef enum { + PCI_LST_ESR_HY, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_HY, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_HY, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_HY, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_HY, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_HY ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDHy; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3HY_H_ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c new file mode 100755 index 0000000000..87b8ed437a --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mndcthy.c @@ -0,0 +1,361 @@ +/** + * @file + * + * mndctHy.c + * + * Northbridge DCT support for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 47176 $ @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mnhy.h" +#include "merrhdl.h" +#include "cpuFamRegisters.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the memory controller with configuration parameters + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value + */ + +BOOLEAN +MemNAutoConfigHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 PowerDownMode; + UINT32 Value32; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + //====================================================================== + // Build Dram Control Register Value (F2x78) + //====================================================================== + // + //It is recommended that these bits remain in the default state. + //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5); + + MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1); + + //====================================================================== + // Build Dram Config Lo Register Value + //====================================================================== + // + + if (MCTPtr->Status[SbParDimms]) { + // + // SbParDimms should be set for all DDR3 RDIMMS + // Cannot turn off ParEn for DDR3 + // + //@attention - add debug option for parity control + MemNSetBitFieldNb (NBPtr, BFParEn, 1); + } + + + if (MCTPtr->GangedMode) { + MemNSetBitFieldNb (NBPtr, BFWidth128, 1); + } + + MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF); + + if (!MCTPtr->Status[SbRegistered]) { + MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1); + } + + if (MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1); + } + + //====================================================================== + // Build Dram Config Hi Register Value + //====================================================================== + // + + MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed)); + + if (MCTPtr->Status[SbRegistered]) { + if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) { + MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1); + } + } + + if (RefPtr->EnableBankSwizzle) { + MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1); + } + + if (DCTPtr->Timings.DimmQrPresent) { + if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) { + MemNSetBitFieldNb (NBPtr, BFF2X98B17, 1); + } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) { + MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1); + } + } + + MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF); + MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1); + //====================================================================== + // Build Dram Config Misc Register Value + //====================================================================== + // + if (MCTPtr->Status[SbRegistered]) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1); + } + } + //====================================================================== + // Build Dram Config Misc 2 Register Value + //====================================================================== + // + // + // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms + // + if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) { + MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1); + } + // + // DTaxTxFifpWrDly + // + Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit); + if ((Value32 >= 2) && (Value32 <= 5)) { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32)); + } + + // + // ProgOdtEn + // + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1); + } else { + MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0); + } + // + // OdtSwizzle + // + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) { + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode == 1) { + MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1); + } + } + + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends an MRS command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendMrsCmdHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwapBitsNb (NBPtr); + + IDS_HDT_CONSOLE ("\t\t\tCS%lx MR%lx %04lx\n", + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF, + (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF)); + + // 1.Set SendMrsCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1); + + // 2.Wait for SendMrsCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM init + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDramInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + //Set PllLockTime and DllLockTime to default. + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Enable DLL Shut down + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNEnDLLShutDownHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + BOOLEAN DllShutDownEn; + + DllShutDownEn = TRUE; + IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader)); + + if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) { + if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C); + MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D); + MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0); + } + } + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Workaround for erratum 322 and 263 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNBeforePlatformSpecHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Errata 263 + if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) { + MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800); + } else { + MemNSetBitFieldNb (NBPtr, BFErr263, 0); + } + + // Errata 322 + // 1.Write 00000000h to F2x[1,0]9C_xD08E000 + MemNSetBitFieldNb (NBPtr, BFErr322I, 0); + // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is + // greater than or equal to 011b (DDR-800 and higher), + // then write 00000080h to F2x[1,0]9C_xD02E001, + // else write 00000090h to F2x[1,0]9C_xD02E001. + MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c new file mode 100755 index 0000000000..b21a86121c --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnflowhy.c @@ -0,0 +1,130 @@ +/** + * @file + * + * mnflowhy.c + * + * Hydra initializer for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/Main) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mnhy.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE +/* features */ + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the platform specific block + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_SUCCESS at least one dorm factor was found + * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found + */ + +BOOLEAN +MemNPlatformSpecificFormFactorInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 f; + UINT8 ErrUnSuppFFCount; + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + if (NBPtr->ChannelPtr->ChDimmValid != 0) { + ErrUnSuppFFCount = 0; + for (f = 0; f < MAX_FF_TYPES; f++) { + ASSERT (memPlatSpecFFInstalledHy[f] != NULL); + if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) { + ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors + } else { + break; + } + } + if (ErrUnSuppFFCount == MAX_FF_TYPES) { + return FALSE; // No FF types are supported + } + } + } + return TRUE; +} +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c new file mode 100755 index 0000000000..71d35f0c6b --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.c @@ -0,0 +1,453 @@ +/** + * @file + * + * mnhy.c + * + * Common Northbridge functions for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 47246 $ @e \$Date: 2011-02-16 13:46:56 -0700 (Wed, 16 Feb 2011) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct; + } + + MemNInitNBDataHy (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableHy (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_256B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0x1FF; + NBPtr->DefDctSelIntLvAddr = 3; + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->InitializeMCT = MemNInitializeMctNb; + NBPtr->FinalizeMCT = MemNFinalizeMctHy; + NBPtr->SendMrsCmd = MemNSendMrsCmdHy; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternHy; + NBPtr->ReadPattern = MemNReadPatternHy; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = MemNAutoConfigHy; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = MemNDefFalseNb; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingHy; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingHy; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; + NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNInitPhyComp = MemNInitPhyCompHy; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE; + NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE; + NBPtr->IsSupported[CheckODTControls] = TRUE; + NBPtr->IsSupported[CheckDummyCLRead] = TRUE; + NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsHY ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; + // + + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h new file mode 100755 index 0000000000..9e283d4f26 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnhy.h @@ -0,0 +1,189 @@ +/** + * @file + * + * mnhy.h + * + * Northbridge Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 47176 $ @e \$Date: 2011-02-15 19:56:01 -0700 (Tue, 15 Feb 2011) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNHY_H_ +#define _MNHY_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +#define MAX_CHANNELS_PER_SOCKET_HY 4 +#define MAX_DCTS_PER_NODE_HY 2 +#define MAX_CHANNELS_PER_DCT_HY 1 +#define MAX_NODES_SUPPORTED_HY 8 + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +#include "OptionMemory.h" + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +MemConstructNBBlockHY ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsHY ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +BOOLEAN +MemNFinalizeMctHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNSendMrsCmdHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNAutoConfigHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNOtherTimingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitPhyCompHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNWritePatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +InitNBRegTableHy ( + IN OUT TSEFO NBRegTable[] + ); + +UINT8 +MemNGetSocketRelativeChannelHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ); + +BOOLEAN +MemNIsIdSupportedHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ); + +VOID +MemNBeforeDramInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +BOOLEAN +MemNPlatformSpecificFormFactorInitHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNEnDLLShutDownHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT32 +MemNCmnGetSetFieldHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ); + +VOID +MemNBeforePlatformSpecHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNBeforeDQSTrainingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#endif /* _MNHY_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c new file mode 100755 index 0000000000..2b8758e58a --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnidendimmhy.c @@ -0,0 +1,134 @@ +/** + * @file + * + * mnidendimmhy.c + * + * Hy northbridge constructor for dimm identification translator. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "Ids.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mfidendimm.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for dimm identification translator + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in,out] NodeID - ID of current node to construct + * @return TRUE - This is the correct constructor for the targeted node. + * @return FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNIdentifyDimmConstructorHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY; + NBPtr->DctCount = MAX_DCTS_PER_NODE_HY; + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Ganged = FALSE; + InitNBRegTableHy (NBPtr->NBRegTable); + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy; + + return TRUE; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c new file mode 100755 index 0000000000..469acae054 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnmcthy.c @@ -0,0 +1,150 @@ +/** + * @file + * + * mnmcthy.c + * + * Northbridge Hydra MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets final values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNFinalizeMctHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + UINT16 Speed; + UINT32 ExtMctCfgLoRegVal; + + MemPtr = NBPtr->MemPtr; + Speed = NBPtr->DCTPtr->Timings.Speed; + MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40); + + ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); + ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001; + + ExtMctCfgLoRegVal &= 0x0FFFFFFF; + if (Speed == DDR667_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x40000000; + } else if (Speed == DDR800_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x50000000; + } else if (Speed == DDR1066_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x60000000; + } else if (Speed == DDR1333_FREQUENCY) { + ExtMctCfgLoRegVal |= 0x80000000; + } else { + ExtMctCfgLoRegVal |= 0x90000000; + } + MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal); + + if (NBPtr->Node == BSP_DIE) { + if (!NBPtr->ClToNbFlag) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c new file mode 100755 index 0000000000..0f5f37fcd5 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnothy.c @@ -0,0 +1,239 @@ +/** + * @file + * + * mnothy.c + * + * Northbridge Non-SPD timings for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 44323 $ @e \$Date: 2010-12-22 01:24:58 -0700 (Wed, 22 Dec 2010) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNSetOtherTimingHY ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +#ifdef UNUSED_CODE +UINT32 +STATIC +MemNGetODTDelaysHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +#endif + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNOtherTimingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSwitchDCTNb (NBPtr, 0); + if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { + MemNSetOtherTimingHY (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownHy (NBPtr); + } + + MemNSwitchDCTNb (NBPtr, 1); + if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) { + MemNSetOtherTimingHY (NBPtr); + MemNPowerDownCtlNb (NBPtr); + MemNEnDLLShutDownHy (NBPtr); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the non-SPD timings in PCI registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNSetOtherTimingHY ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + + MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr)); + MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the ODT delays + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +#ifdef UNUSED_CODE +UINT32 +STATIC +MemNGetODTDelaysHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Ld; + UINT32 ODTDelays; + // + // On revision D processors, the BIOS must additionally configure the ODT pattern + // and the ODT switching delays. + // + // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. + // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. + // -Value of 2, BL = 4 else assume BL=8. + // -Initialize ODTDelays based on BL value + // -WrOdtOnDuration [14:12] = BL / 2 + 1 + // -WrOdtTrnOnDly [10:8] = 0 + // -RdOdtOnDuration [6:4] = BL / 2 + 1 + // + ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; + + // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) + // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] + Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if (Ld < 0) { + Ld = 0; + } + if (Ld > 7) { + Ld = 7; + } + ODTDelays += Ld; + return ODTDelays; +} +#endif +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +#ifdef UNUSED_CODE +VOID +STATIC +MemNPowerDownCtlHY ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} +#endif diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c new file mode 100755 index 0000000000..908263862c --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnphyhy.c @@ -0,0 +1,234 @@ +/** + * @file + * + * mnphyHy.c + * + * Northbridge Phy support for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "ma.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mnhy.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; + CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; + CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; + CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; + UINT8 i; + UINT8 j; + UINT8 CurrDct; + UINT8 MaxDimmsPerChannel; + UINT8 *DimmsPerChPtr; + + CurrDct = NBPtr->Dct; + + // + // Get Platform Information + // + DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID); + if (DimmsPerChPtr != NULL) { + MaxDimmsPerChannel = *DimmsPerChPtr; + } else { + MaxDimmsPerChannel = 2; + } + + // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp will be cleared after Dram init has completed + // + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + MemUWait10ns (500, NBPtr->MemPtr); + MemNSwitchDCTNb (NBPtr, CurrDct); + + // 3. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the + // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. + // + // 4. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding + // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, + // D3Cmp2PCal]. + // + j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); + i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); + + MemNSwitchDCTNb (NBPtr, 0); + ASSERT (j <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); + + ASSERT (i <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); + + // + // Special Case for certain configs + // + // 3DPCH Fully populated. + if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) { + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5); + } + + MemNSwitchDCTNb (NBPtr, CurrDct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDQSTrainingHy ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 ChipSel; + UINT32 TestAddrRJ16; + UINT32 RealAddr; + + MemTBeginTraining (NBPtr->TechPtr); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { + + RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); + + MemUDummyCLRead (RealAddr); + + MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); + MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns + MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); + MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us + MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); + break; + } + } + } + if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { + if (!NBPtr->MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); + } + if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { + MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); + } + } + } + + MemTEndTraining (NBPtr->TechPtr); + + MemNSetBitFieldNb (NBPtr, BFDisDatMsk, 1); +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c new file mode 100755 index 0000000000..dd48661f65 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnprotohy.c @@ -0,0 +1,62 @@ +/** + * @file + * + * mnprotohy.c + * + * Northbridge support functions for Errata and early samples + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 7735 $ @e \$Date: 2008-08-27 14:49:19 -0500 (Wed, 27 Aug 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + + +#include "AGESA.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* + *----------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *----------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c new file mode 100755 index 0000000000..dba28799c0 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/HY/mnreghy.c @@ -0,0 +1,573 @@ +/** + * @file + * + * mnreghy.c + * + * Common Northbridge register related functions for Hydra + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/HY) + * @e \$Revision: 13632 $ @e \$Date: 2009-05-13 10:10:13 -0500 (Wed, 13 May 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnhy.h" +#include "merrhdl.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*-----------------------------------------------------------------------------*/ +/** + * MemNIsIdSupportedHy + * This function matches the CPU_LOGICAL_ID with certain criteria to + * determine if it is supported by this NBBlock. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID + * + * @return TRUE - This node is a Hydra. + * @return FALSE - This node is not a Hydra. + * + */ +BOOLEAN +MemNIsIdSupportedHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN CPU_LOGICAL_ID *LogicalIdPtr + ) +{ + if ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0) { + return TRUE; + } else { + return FALSE; + } +} + +/*-----------------------------------------------------------------------------*/ +/** + * This function calculates the memory channel index relative to the + * socket, taking the Die number, the Dct, and the channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct + * @param[in] Channel + * + */ +UINT8 +MemNGetSocketRelativeChannelHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ) +{ + return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct); +} +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or sets a value to a bit field in a PCI register. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field to be programmed + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNCmnGetSetFieldHy ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + TSEFO Address; + PCI_ADDR PciAddr; + UINT8 Type; + UINT8 IsLinked; + UINT32 Value; + UINT32 Highbit; + UINT32 Lowbit; + UINT32 Mask; + + Value = 0; + if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + Address = NBPtr->NBRegTable[FieldName]; + if (Address) { + Lowbit = TSEFO_END (Address); + Highbit = TSEFO_START (Address); + Type = (UINT8) TSEFO_TYPE (Address); + IsLinked = (UINT8) TSEFO_LINKED (Address); + + // If Fn2 and DCT1 selected, set Address to be 1xx + if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) { + if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) { + Address |= 0x0100; + } + } + + if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) { + // Special DCT Phy access + Address &= 0x0FFFFFFF; + Lowbit = 0; + Highbit = 16; + IsLinked = 0; + } else { + // Normal DCT Phy access + Address = TSEFO_OFFSET (Address); + } + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + Address = PciAddr.AddressValue; + LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg); + } else { + IDS_ERROR_TRAP; + } + + if (IsSet) { + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } else { + Mask = (UINT32)0xFFFFFFFF; + } + Value &= ~(Mask << Lowbit); + Value |= (Field & Mask) << Lowbit; + + if (Type == NB_ACCESS) { + PciAddr.AddressValue = Address; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } else if (Type == DCT_PHY_ACCESS) { + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + } else if (Type == DCT_EXTRA) { + MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + } else { + IDS_ERROR_TRAP; + } + if (IsLinked) { + MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1)); + } + } else { + Value = Value >> Lowbit; // Shift + // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case + if ((Highbit - Lowbit) != 31) { + Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1); + } + if (IsLinked) { + Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1); + } + } + } + } else { + IDS_ERROR_TRAP; // Invalid bit field index + } + return Value; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes bit field translation table + * + * @param[in,out] NBRegTable[] - Pointer to the bit field data structure + * + */ + +VOID +InitNBRegTableHy ( + IN OUT TSEFO NBRegTable[] + ) +{ + UINT16 i; + for (i = 0; i < BFEndOfList; i++) { + NBRegTable[i] = 0; + } + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 23, 21, BFDramIntlvEn); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFF3X188B8); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFF2X78B16); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFF2X98B17); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt); + + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl); + MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri); + + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow); + MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II); + + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime); + MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime); + + LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi); + LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi); + LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi); + +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c new file mode 100755 index 0000000000..3579eb7a81 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.c @@ -0,0 +1,462 @@ +/** + * @file + * + * mnNi.c + * + * Common Northbridge functions for Nile + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mnda.h" +#include "mnNi.h" +#include "mu.h" +#include "S3.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "GeneralServices.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_NI_MNNI_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +#define SPLIT_CHANNEL (UINT32) 0x20000000 +#define CHANNEL_SELECT (UINT32) 0x10000000 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; +extern PSO_ENTRY DefaultPlatformMemoryConfiguration[]; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB + * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA + * @param[in] NodeID - UINT8 indicating node ID of the NB object. + * + * @return Boolean indicating that this is the correct memory + * controller type for the node number that was passed in. + */ + +BOOLEAN +MemConstructNBBlockNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ) +{ + UINT8 Dct; + UINT8 Channel; + UINT8 SpdSocketIndex; + UINT8 SpdChannelIndex; + DIE_STRUCT *MCTPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->RefPtr = MemPtr->ParameterListPtr; + NBPtr->SharedPtr = SharedPtr; + + MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->MCTPtr = MCTPtr; + NBPtr->MCTPtr->NodeId = NodeID; + NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue; + NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + + // + // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs + // + AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * ( + sizeof (DCT_STRUCT) + ( + MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK)) + ) + ); + AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0); + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) { + PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader); + SetMemError (AGESA_FATAL, MCTPtr); + return FALSE; + } + + MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA; + MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr; + AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT); + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MCTPtr->DctData[Dct].Dct = Dct; + MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA; + MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr; + MCTPtr->DctData[Dct].ChData[0].Dct = Dct; + AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT); + } + NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr; + + // + // Initialize Socket List + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]); + MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings); + MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct; + } + + MemNInitNBDataDA (NBPtr); + + FeatPtr->InitCPG (NBPtr); + NBPtr->FeatPtr = FeatPtr; + + // + // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel + // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that + // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the + // dimm types(QR or not) are known. This is done in the Technology block constructor. + // + // Calculate the SpdSocketIndex separately from the SpdChannelIndex. + // This will facilitate modifications due to some processors that might + // map the DCT-CHANNEL differently. + // + SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader); + // + // Traverse the Dct/Channel structures + // + for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) { + // + // Calculate the number of Dimms on this channel using the + // die/dct/channel to Socket/channel conversion. + // + SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, + NBPtr->MCTPtr->SocketId, + MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel), + &MemPtr->StdHeader); + NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]); + } + } + + MemNSwitchDCTNb (NBPtr, 0); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + InitNBRegTableDA (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->Ganged = FALSE; + NBPtr->PosTrnPattern = POS_PATTERN_72B; + NBPtr->MemCleared = FALSE; + NBPtr->StartupSpeed = DDR800_FREQUENCY; + NBPtr->RcvrEnDlyLimit = 0xFF; + NBPtr->DefDctSelIntLvAddr = 3; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader); + + NBPtr->SetMaxLatency = MemNSetMaxLatencyNb; + NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->InitializeMCT = MemNInitializeMctNb; + NBPtr->FinalizeMCT = MemNFinalizeMctDA; + NBPtr->SendMrsCmd = MemNSendMrsCmdDA; + NBPtr->sendZQCmd = MemNSendZQCmdNb; + NBPtr->WritePattern = MemNWritePatternDA; + NBPtr->ReadPattern = MemNReadPatternDA; + NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb; + NBPtr->StitchMemory = MemNStitchMemoryNb; + NBPtr->AutoConfig = memNAutoConfigDA; + NBPtr->PlatformSpec = MemNPlatformSpecNb; + NBPtr->InitMCT = MemNInitMCTNb; + NBPtr->DisableDCT = MemNDisableDCTNb; + NBPtr->StartupDCT = MemNStartupDCTNb; + NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb; + NBPtr->ChangeFrequency = MemNChangeFrequencyNb; + NBPtr->RampUpFrequency = MemNRampUpFrequencyNb; + NBPtr->ChangeNbFrequency = MemNDefFalseNb; + NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb; + NBPtr->SyncDctsReady = MemNSyncDctsReadyNb; + NBPtr->HtMemMapInit = MemNHtMemMapInitNb; + NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb; + NBPtr->CpuMemTyping = MemNCPUMemTypingNb; + NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb; + NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->OtherTiming = MemNOtherTimingDA; + NBPtr->UMAMemTyping = MemNUMAMemTypingNb; + NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet; + NBPtr->TrainingFlow = MemNTrainingFlowNb; + NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb; + MemNInitNBDataNb (NBPtr); + NBPtr->PollBitField = MemNPollBitFieldNb; + NBPtr->BrdcstCheck = MemNBrdcstCheckNb; + NBPtr->BrdcstSet = MemNBrdcstSetNb; + NBPtr->GetTrainDly = MemNGetTrainDlyNb; + NBPtr->SetTrainDly = MemNSetTrainDlyNb; + NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb; + NBPtr->GetSysAddr = MemNGetMCTSysAddrNb; + NBPtr->RankEnabled = MemNRankEnabledNb; + NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb; + NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA; + NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA; + NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb; + NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA; + NBPtr->MemNInitPhyComp = MemNInitPhyCompNb; + NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb; + NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA; + NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet; + NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb; + NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb; + NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb; + NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb; + NBPtr->CSPerChannel = MemNCSPerChannelNb; + NBPtr->CSPerDelay = MemNCSPerDelayNb; + NBPtr->FlushPattern = MemNFlushPatternNb; + NBPtr->GetUmaSize = MemNGetUmaSizeNb; + NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb; + NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA; + NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb; + + NBPtr->IsSupported[SetSpareEn] = TRUE; + NBPtr->IsSupported[CheckSpareEn] = TRUE; + NBPtr->IsSupported[SetDllShutDown] = TRUE; + NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE; + NBPtr->IsSupported[CheckMaxDramRate] = TRUE; + NBPtr->IsSupported[Check1GAlign] = TRUE; + NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE; + NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE; + NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE; + NBPtr->IsSupported[CheckFindPSDct] = TRUE; + NBPtr->IsSupported[CheckDllStdBy] = TRUE; + NBPtr->IsSupported[CheckDynamicDramTerm] = TRUE; + NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE; + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->IsSupported[CheckDllRegDis] = TRUE; + NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the default values in the MEM_DATA_STRUCT + * + * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT + * + */ +VOID +MemNInitDefaultsNi ( + IN OUT MEM_DATA_STRUCT *MemPtr + ) +{ + UINT8 Socket; + UINT8 Channel; + MEM_PARAMETER_STRUCT *RefPtr; + ASSERT (MemPtr != NULL); + RefPtr = MemPtr->ParameterListPtr; + + // Memory Map/Mgt. + // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB + RefPtr->BottomIo = 0xE0; + RefPtr->UmaMode = UserOptions.CfgUmaMode; + RefPtr->UmaSize = UserOptions.CfgUmaSize; + RefPtr->MemHoleRemapping = TRUE; + RefPtr->LimitMemoryToBelow1Tb = UserOptions.CfgLimitMemoryToBelow1Tb; + + // Dram Timing + RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect; + RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect; + for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) { + for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) { + MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL; + MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL; + } + } + + // Memory Clear + RefPtr->EnableMemClr = TRUE; + + // TableBasedAlterations + RefPtr->TableBasedAlterations = NULL; + + // Platform config table + RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration; + + // Memory Restore + RefPtr->MemRestoreCtl = FALSE; + RefPtr->SaveMemContextCtl = FALSE; + AmdS3ParamsInitializer (&RefPtr->MemContext); + + // Dram Configuration + RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving; + RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving; + RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving; + RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle; + RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable; + RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare; + + // Dram Power + RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown; + + // ECC + RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function writes training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern[] - Pattern to write + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNWritePatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function reads training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer to fill + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNReadPatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUReadCachelines (Buffer, Address, ClCount); +} + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h new file mode 100755 index 0000000000..a36d7e1dce --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnNi.h @@ -0,0 +1,109 @@ +/** + * @file + * + * mnNi.h + * + * Northbridge Ni for Nile + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _MNNI_H_ +#define _MNNI_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +typedef struct _MEM_FEAT_BLOCK_NB MEM_FEAT_BLOCK_NB; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +MemConstructNBBlockNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN MEM_FEAT_BLOCK_NB *FeatPtr, + IN MEM_SHARED_DATA *SharedPtr, + IN UINT8 NodeID + ); + +VOID +MemNInitNBDataNi ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +MemNInitDefaultsNi ( + IN OUT MEM_DATA_STRUCT *MemPtr + ); + +VOID +MemNWritePatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +MemNReadPatternNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +#endif /* _MNNI_H_ */ + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c new file mode 100755 index 0000000000..fb6af1ed95 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.c @@ -0,0 +1,738 @@ +/** + * @file + * + * mns3Ni.c + * + * Ni memory specific function to support S3 resume + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "mnda.h" +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "mnS3Ni.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_NI_MNS3NI_FILECODE + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +UINT16 +STATIC +MemNS3GetRegLstPtrNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ); + +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstNi ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ); + +VOID +STATIC +MemNS3SetSpecialPCIRegNi ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ); + +VOID +STATIC +MemNS3ExitSelfRefRegNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +PCI_SPECIAL_CASE PciSpecialCaseFuncNi[] = { + {MemNS3GetCSRNb, MemNS3SetCSRNb}, + {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegNi}, + {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb} +}; + +PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorNi[] = { + {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03}, + {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03}, + {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF}, + {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF}, + {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF}, + {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF}, + {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83}, + {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, + {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF}, + {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, + {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00}, + {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF}, + {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF}, + {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F} +}; + +CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefNi = { + 0, + (sizeof (S3PciPreSelfRefDescriptorNi) / sizeof (PCI_REG_DESCRIPTOR)), + S3PciPreSelfRefDescriptorNi, + NULL +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorNi[] = { + // DCT 0 + {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 322 + {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + //errata 263 + {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT 1 + {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 322 + {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // errata 263 + {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + // Dll regulator disable + {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore F2x[1,0]94 right before exit self refresh + {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK} +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefNi = { + 0, + (sizeof (S3CPciPreSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPreSelfDescriptorNi, + PciSpecialCaseFuncNi +}; + +CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorNi[] = { + // DCT0 + {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + + // DCT1 + {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + + // DllShutDown + {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK}, + + // Restore scrubber related registers after restoring training related registers + {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK}, + {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}, +}; + +CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefNi = { + 0, + (sizeof (S3CPciPostSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), + S3CPciPostSelfDescriptorNi, + PciSpecialCaseFuncNi +}; + +MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorNi[] = { + {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF}, + {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, + {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF} +}; + +CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefNi = { + 0, + (sizeof (S3MSRPreSelfRefDescriptorNi) / sizeof (MSR_REG_DESCRIPTOR)), + S3MSRPreSelfRefDescriptorNi, + NULL +}; + +VOID *MemS3RegListNi[] = { + (VOID *)&S3PciPreSelfRefNi, + NULL, + (VOID *)&S3CPciPreSelfRefNi, + (VOID *)&S3CPciPostSelfRefNi, + (VOID *)&S3MSRPreSelfRefNi, + NULL, + NULL, + NULL +}; + +CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = { + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), + SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04) +}; +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the northbridge block for S3 resume + * + * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. + * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. + * @param[in] NodeID - Node ID of the target node. + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ +BOOLEAN +MemS3ResumeConstructNBBlockNi ( + IN OUT VOID *S3NBPtr, + IN OUT MEM_DATA_STRUCT *MemPtr, + IN UINT8 NodeID + ) +{ + INT32 i; + MEM_NB_BLOCK *NBPtr; + + NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; + + // + // Determine if this is the expected NB Type + // + GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); + if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { + return FALSE; + } + + NBPtr->MemPtr = MemPtr; + NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); + NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; + InitNBRegTableDA (NBPtr->NBRegTable); + NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; + NBPtr->Dct = 0; + NBPtr->Channel = 0; + NBPtr->Ganged = FALSE; + NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA; + NBPtr->DctCount = MAX_DCTS_PER_NODE_DA; + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); + + NBPtr->IsSupported[CheckDllSpeedUp] = TRUE; + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; + NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA; + NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegNi; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrNi; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstNi; + ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)) * sizeof (UINT32); + + MemNSwitchDCTNb (NBPtr, 0); + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the register list for each device for Ni + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return UINT16 - size of the device descriptor on the target node. + */ +UINT16 +STATIC +MemNS3GetRegLstPtrNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + UINT8 i; + UINT16 Size; + Size = 0; + for (i = PRESELFREF; i <= POSTSELFREF; i ++) { + DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); + DescriptPtr->PCIDevice[i].Node = NBPtr->Node; + DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i; + Size += sizeof (PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); + DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; + DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); + } + DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); + DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i; + Size += sizeof (MSR_DEVICE_DESCRIPTOR); + } + DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); + DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; + if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) { + DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i; + Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); + } + } + return Size; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function return the register list according to the register ID. + * + * @param[in] RegisterLstID - value of the Register list ID. + * @param[out] **RegisterHeader - pointer to the address of the register list. + * @return none + */ +AGESA_STATUS +STATIC +MemNS3GetDeviceRegLstNi ( + IN UINT32 RegisterLstID, + OUT VOID **RegisterHeader + ) +{ + if (RegisterLstID >= (sizeof (MemS3RegListNi) / sizeof (VOID *))) { + ASSERT(FALSE); // RegisterListID exceeded size of Register list + return AGESA_FATAL; + } + if (MemS3RegListNi[RegisterLstID] != NULL) { + *RegisterHeader = MemS3RegListNi[RegisterLstID]; + return AGESA_SUCCESS; + } + ASSERT(FALSE); // Device register list error + return AGESA_FATAL; +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3SetSpecialPCIRegNi ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (Address.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Save the value in the heap at appropriate offset based on the index + // of the target register in the special case array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) { + if (SpecialCasePCIRegNi[i] == Address.Address.Register) { + *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value; + } + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function stores special case register on the heap. + * + * @param[in,out] *NBPtr - Pointer to the northbridge block. + * @param[in,out] *StdHeader - Config handle for library and services. + * @return none + */ +VOID +STATIC +MemNS3ExitSelfRefRegNi ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ) +{ + LOCATE_HEAP_PTR LocateBufferPtr; + UINT8 i; + PCI_ADDR PciAddr; + UINT32 Value; + UINT8 NodeID; + UINT8 Offset; + S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader; + + Offset = 0; + PciAddr.Address.Device = NBPtr->PciAddr.Address.Device; + PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus; + PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment; + PciAddr.Address.Function = 2; + LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) { + SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr; + // Get the node ID of the target die. + NodeID = (UINT8) (PciAddr.Address.Device - 24); + for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) { + if (SpecialHeapHeader[i].Node == NodeID) { + // Get the offset in the heap for the target die. + Offset = SpecialHeapHeader[i].Offset; + break; + } + } + ASSERT (i < MAX_NODES_SUPPORTED_DA); + // Restore the value one by one in the sequence of the special case register array. + if (Offset != 0) { + for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) { + PciAddr.Address.Register = SpecialCasePCIRegNi[i]; + Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)); + MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader); + } + } + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h new file mode 100755 index 0000000000..8b5a3dba2d --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/NI/mnS3Ni.h @@ -0,0 +1,83 @@ +/** + * @file + * + * mnS3Ni.h + * + * S3 resume memory related function for Ni. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/NI) + * @e \$Revision: 6474 $ @e \$Date: 2008-06-20 03:07:59 -0500 (Fri, 20 Jun 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +#ifndef _MNS3DA_H_ +#define _MNS3DA_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ +/// ID for register list of HY +typedef enum { + PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh. + PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh. + CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh. + CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh. + MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh. + MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh. + CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh. + CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh. +} RegisterListIDDA; + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ + +#endif //_MNS3DA_H_ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c new file mode 100755 index 0000000000..df93fea53d --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mn.c @@ -0,0 +1,538 @@ +/** + * @file + * + * mn.c + * + * Common Northbridge functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MN_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNDefaultFamilyHookNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[]; + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes member functions and variables of NB block. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitNBDataNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT32 i; + UINT8 *BytePtr; + + NBPtr->DctCachePtr = NBPtr->DctCache; + NBPtr->PsPtr = NBPtr->PSBlock; + + BytePtr = (UINT8 *) (NBPtr->DctCache); + for (i = 0; i < sizeof (NBPtr->DctCache); i++) { + *BytePtr++ = 0; + } + + for (i = 0; i < EnumSize; i++) { + NBPtr->IsSupported[i] = FALSE; + } + + for (i = 0; i < NumberOfHooks; i++) { + NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb; + } + + NBPtr->SwitchDCT = MemNSwitchDCTNb; + NBPtr->SwitchChannel = MemNSwitchChannelNb; + NBPtr->GetBitField = MemNGetBitFieldNb; + NBPtr->SetBitField = MemNSetBitFieldNb; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Get System address of Chipselect RJ 16 bits (Addr[47:16]) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Receiver - Chipselect to be targeted [0-7] + * @param[out] AddrPtr - Pointer to System Address [47:16] + * + * @return TRUE - Address is valid + * @return FALSE - Address is not valid + */ + +BOOLEAN +MemNGetMCTSysAddrNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Receiver, + OUT UINT32 *AddrPtr + ) +{ + S_UINT64 SMsr; + UINT32 CSBase; + UINT32 HoleBase; + UINT32 DctSelBaseAddr; + UINT32 BottomUma; + DIE_STRUCT *MCTPtr; + MEM_DATA_STRUCT *MemPtr; + + MCTPtr = NBPtr->MCTPtr; + MemPtr = NBPtr->MemPtr; + + ASSERT (Receiver < 8); + + CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); + if (CSBase & 1) { + ASSERT ((CSBase & 0xE0) == 0); // Should not enable CS interleaving before DQS training. + + // Scale base address from [39:8] to [47:16] + CSBase >>= 8; + + HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF; + + if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) { + DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16); + if (DctSelBaseAddr > HoleBase) { + DctSelBaseAddr -= _4GB_RJ16 - HoleBase; + } + CSBase += DctSelBaseAddr; + } else { + CSBase += MCTPtr->NodeSysBase; + } + + if (CSBase >= HoleBase) { + CSBase += _4GB_RJ16 - HoleBase; + } + + CSBase += (UINT32)1 << (21 - 16); // Add 2MB offset to avoid compat area. + if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) { + CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0; + } + + if (MCTPtr->Status[SbHWHole]) { + if (MCTPtr->Status[SbSWNodeHole]) { + LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) { + return FALSE; + } + } + } + + BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16; + if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) { + return FALSE; + } + *AddrPtr = CSBase; + return TRUE; + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function determines if a Rank is enabled. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Receiver - Receiver to check + * @return - FALSE + * + */ + +BOOLEAN +MemNRankEnabledNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Receiver + ) +{ + UINT32 CSBase; + CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver); + if (CSBase & 1) { + return TRUE; + } else { + return FALSE; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the EccSymbolSize bit depending upon configurations + * and system override. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSetEccSymbolSizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 X4DimmsOnly; + BOOLEAN Size; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + + ASSERT (NBPtr != NULL); + + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + + // Determine if this node has only x4 DRAM parts + X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present); + // + // Check if EccSymbolSize BKDG value is overridden + // + if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) { + Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE; + } else { + if (X4DimmsOnly && MCTPtr->GangedMode) { + Size = FALSE; + } else { + Size = TRUE; + } + } + IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader)); + MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function sets the training control flow + * The DDR3 mode bit must be set prior to calling this function + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +BOOLEAN +MemNTrainingFlowNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) { + memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr); + } else { + memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr); + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is the default NB return function + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +BOOLEAN +MemNDefNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function is used in place of an un-supported function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ +BOOLEAN +MemNDefFalseNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return FALSE; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function flushes the training pattern + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +MemNFlushPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + // Due to speculative execution during MemUReadCachelines, we must + // flush one more cache line than we read. + MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @return PASS - Bitmap of results of comparison + */ + +UINT16 +MemNCompareTestPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + UINT16 i; + UINT16 Pass; + UINT8 ColumnCount; + UINT8 FailingBitMask[8]; + + ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); + + ColumnCount = NBPtr->ChannelPtr->ColumnCount; + Pass = 0xFFFF; + // + // Clear Failing Bit Mask + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + FailingBitMask[i] = 0; + } + + if (NBPtr->Ganged && (NBPtr->Dct != 0)) { + i = 8; // DCT 1 in ganged mode + } else { + i = 0; + } + + for (; i < ByteCount; i++) { + if (Buffer[i] != Pattern[i]) { + // if bytelane n fails + Pass &= ~((UINT16)1 << (i % 8)); // clear bit n + FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]); + } + + if (NBPtr->Ganged && ((i & 7) == 7)) { + i += 8; // if ganged, skip over other Channel's Data + } + } + // + // Accumulate Failing bit data + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= + FailingBitMask[i]; + } + + return Pass; +} + +/*----------------------------------------------------------------------------- + * + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @retval PASS - Bitmap of results of comparison + * ---------------------------------------------------------------------------- + */ +UINT16 +MemNInsDlyCompareTestPatternNb ( + IN MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + UINT16 i; + UINT16 Pass; + UINT16 BeatOffset; + UINT16 BeatCnt; + UINT8 ColumnCount; + UINT8 FailingBitMask[8]; + + ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64)); + + ColumnCount = NBPtr->ChannelPtr->ColumnCount; + Pass = 0xFFFF; + // + // Clear Failing Bit Mask + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + FailingBitMask[i] = 0; + } + + if (NBPtr->Ganged && (NBPtr->Dct != 0)) { + i = 8; // DCT 1 in ganged mode + } else { + i = 0; + } + + if (NBPtr->Ganged) { + BeatOffset = 16; + } else { + BeatOffset = 8; + } + + BeatCnt = 0; + for (; i < ByteCount; i++) { + + if (Buffer[i] != Pattern[i + BeatOffset]) { + // if bytelane n fails + Pass &= ~((UINT16)1 << (i % 8)); // clear bit n + FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]); + } + + if ((i & 7) == 7) { + if (NBPtr->Ganged) { + i += 8; // if ganged, skip over other Channel's Data + } + BeatCnt++; + } + + if ((BeatCnt & 3) == 3) { + // Skip last data beat of a 4-beat burst. + BeatCnt++; + i = i + BeatOffset; + } + } + // + // Accumulate Failing bit data + // + for (i = 0; i < sizeof (FailingBitMask); i++) { + NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &= + FailingBitMask[i]; + } + + return Pass; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * + * + * This function is an empty function used to intialize FamilySpecificHook array + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] OptParam - Optional parameter + * + * @return TRUE - always + * ---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNDefaultFamilyHookNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT VOID *OptParam + ) +{ + return TRUE; +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c new file mode 100755 index 0000000000..d0dd6bdd3d --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnS3.c @@ -0,0 +1,677 @@ +/** + * @file + * + * mnS3.c + * + * Common Northbridge S3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "S3.h" +#include "mfs3.h" +#include "cpuFamilyTranslation.h" +#include "heapManager.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNS3_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +STATIC +MemNS3GetSetBitField ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN BOOLEAN IsSet, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ); + +BOOLEAN +STATIC +MemNS3GetDummyReadAddr ( + IN OUT MEM_NB_BLOCK *NBPtr, + OUT UINT64 *TestAddr + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes the S3 resume for a node + * + * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK + * @param[in] NodeID - The Node id of the target die + * + * @return BOOLEAN + * TRUE - This is the correct constructor for the targeted node. + * FALSE - This isn't the correct constructor for the targeted node. + */ + +BOOLEAN +MemNS3ResumeNb ( + IN OUT S3_MEM_NB_BLOCK *S3NBPtr, + IN UINT8 NodeID + ) +{ + UINT8 DCT; + BOOLEAN GangedEn; + UINT64 TestAddr; + MEM_NB_BLOCK *NBPtr; + MEM_DATA_STRUCT *MemPtr; + + NBPtr = S3NBPtr->NBPtr; + MemPtr = NBPtr->MemPtr; + GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE; + + // Errata before S3 resume sequence + + // Resume Sequence + // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + + // Program F2x[1, 0]94[MemClkFreqVal] = 1. + // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { + MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1); + while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {} + } + } + + // Program F2x9C_x08[DisAutoComp]=0 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); + // BIOS must wait 750 us for the phy compensation engine + // to reinitialize. + MemFS3Wait10ns (75000, NBPtr->MemPtr); + + // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C + // 4. Restore F2x[1,0]9C_x04 + // Get the register value from the heap. + S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader); + + // Add a hook here + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); + if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) { + } + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader); + + // 5. Set F2x[1,0]90[ExitSelfRef] + // 6. Wait for F2x[1,0]90[ExitSelfRef]=0 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) { + MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1); + while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {} + } + if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); + if (DCT == 0) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); + } + // NOTE: wait 512 clocks for DLL-relock + MemFS3Wait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + + // Errata After S3 resume sequence + // Errata 350 + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + MemNSwitchDCTNb (NBPtr, DCT); + if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) { + if (!((DCT == 1) && GangedEn)) { + if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) { + // Do dummy read + Read64Mem8 (TestAddr); + } + } + MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); + MemFS3Wait10ns (60, NBPtr->MemPtr); // Wait 300ns + MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); + MemFS3Wait10ns (400, NBPtr->MemPtr); // Wait 2us + } + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function returns the conditional PCI device mask + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP + * @return none + */ +VOID +MemNS3GetConPCIMaskNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT DESCRIPTOR_GROUP *DescriptPtr + ) +{ + BIT_FIELD_NAME bitfield; + UINT32 RegVal; + UINT8 DCT; + UINT8 DimmMask; + UINT8 BadDimmMask; + UINT8 DctGangEn; + BOOLEAN IsDDR3; + + IsDDR3 = FALSE; + DimmMask = 0; + BadDimmMask = 0; + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + NBPtr->SwitchDCT (NBPtr, DCT); + if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { + if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) { + IsDDR3 = TRUE; + } + for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { + RegVal = MemNGetBitFieldNb (NBPtr, bitfield); + if (RegVal & 0x3) { + DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); + } else if (RegVal & 0x4) { + BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT)); + } + } + } + } + + NBPtr->SwitchDCT (NBPtr, 0); + DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn); + // Set channel mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; + for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { + if (DimmMask & (0x55 << DCT)) { + // Set mask before exit self refresh + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; + // Set mask after exit self refresh + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT; + // Set DDR3 mask if Dimms present are DDR3 + if (IsDDR3) { + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); + } + } else if (BadDimmMask & (0x55 << DCT)) { + // Need to save function 2 registers for bad dimm + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; + } + } + // Set dimm mask + DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; + if (DctGangEn) { + // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers + // need to be restored on both channels in ganged mode + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2; + if (IsDDR3) { + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4); + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4); + } + // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored + // in that time frame don't care about individual dimm population. We want to + // skip registers that are not needed to be restored for DCT1 in ganged mode. + // + // After exit self refresh, training registers will be restored and will only be + // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1. + // + DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1; + } + + // Adjust the mask if there is no dimm on the node + if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) && + (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) { + DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; + DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function read the value of CSR register. + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3GetCSRNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 ExtendOffset; + UINT32 ValueRead; + UINT8 DataPort; + + ValueRead = 0; + ExtendOffset = Address.Address.Register; + if (ExtendOffset & 0x800) { + Address.Address.Register = 0xF0; + DataPort = 0xF4; + } else { + Address.Address.Register = 0x98; + DataPort = 0x9C; + } + if (ExtendOffset & 0x400) { + Address.Address.Register |= 0x100; + } + ExtendOffset &= 0x3FF; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); + while (((ValueRead >> 31) & 1) == 0) { + LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); + } + Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort; + LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function write to a CSR register + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetCSRNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + UINT32 ExtendOffset; + UINT32 ValueRead; + UINT32 ValueWrite; + UINT8 DataOffset; + + ValueRead = 0; + ExtendOffset = Address.Address.Register; + // Check the flag and see the type of the access + if (ExtendOffset & 0x800) { + Address.Address.Register = 0xF4; + DataOffset = 0xF0; + } else { + Address.Address.Register = 0x9C; + DataOffset = 0x98; + } + if (ExtendOffset & 0x400) { + Address.Address.Register |= 0x100; + } + ExtendOffset &= 0x3FF; + ExtendOffset |= 0x40000000; + switch (AccessWidth) { + case AccessS3SaveWidth8: + ValueWrite = *(UINT8 *) Value; + break; + case AccessS3SaveWidth16: + ValueWrite = *(UINT16 *) Value; + break; + case AccessS3SaveWidth32: + ValueWrite = *(UINT32 *) Value; + break; + default: + ASSERT (FALSE); + } + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); + Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset; + LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); + while (((ValueRead >> 31) & 1) == 0) { + LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads register bitfield + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value be read. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3GetBitFieldNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function writes register bitfield + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in, out] *Value - Pointer to the value to be written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +MemNS3SetBitFieldNb ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function restores scrubber base register + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Node - The Node id of the target die + * + */ +VOID +MemNS3RestoreScrubNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Node + ) +{ + UINT32 ScrubAddrRJ16; + + ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8; + ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24; + MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16); + MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16); +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *----------------------------------------------------------------------------*/ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads and writes register bitfield + * + * @param[in] AccessWidth - Access width of the register + * @param[in] Address - address of the CSR register in PCI_ADDR format. + * @param[in] IsSet - if this is a register read or write + * @param[in, out] *Value - Pointer to the value be read or written. + * @param[in, out] *ConfigPtr - Pointer to Config handle. + * @return none + */ +VOID +STATIC +MemNS3GetSetBitField ( + IN ACCESS_WIDTH AccessWidth, + IN PCI_ADDR Address, + IN BOOLEAN IsSet, + IN OUT VOID *Value, + IN OUT VOID *ConfigPtr + ) +{ + BIT_FIELD_NAME BitField; + MEM_NB_BLOCK *NBPtr; + LOCATE_HEAP_PTR LocateBufferPtr; + S3_MEM_NB_BLOCK *S3NBPtr; + UINT32 RegValue; + UINT8 Die; + + RegValue = 0; + // See which Node should be accessed + Die = (UINT8) (Address.Address.Device - 24); + + LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; + if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { + S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; + NBPtr = S3NBPtr[Die].NBPtr; + + // Function field contains the DCT number + NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); + + // Get the bitfield name to be accessed + // Register field contains the bitfield name + BitField = (BIT_FIELD_NAME) Address.Address.Register; + + if (IsSet) { + switch (AccessWidth) { + case AccessS3SaveWidth8: + RegValue = *(UINT8 *) Value; + break; + case AccessS3SaveWidth16: + RegValue = *(UINT16 *) Value; + break; + case AccessS3SaveWidth32: + RegValue = *(UINT32 *) Value; + default: + ASSERT (FALSE); + } + MemNSetBitFieldNb (NBPtr, BitField, RegValue); + } else { + RegValue = MemNGetBitFieldNb (NBPtr, BitField); + + switch (AccessWidth) { + case AccessS3SaveWidth8: + *(UINT8 *) Value = (UINT8) RegValue; + break; + case AccessS3SaveWidth16: + *(UINT16 *) Value = (UINT16) RegValue; + break; + case AccessS3SaveWidth32: + *(UINT32 *) Value = RegValue; + break; + default: + ASSERT (FALSE); + } + } + } else { + ASSERT (FALSE); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the dummy read address for a channel of a node. + * + * @param[in, out] *NBPtr - Pointer to northbridge block + * @param[out] *TestAddr - Pointer to the test address + * + * @retval TRUE - Dummy read address can be found + * @retval FALSE - Dummy read address cannot be found + * + */ +BOOLEAN +STATIC +MemNS3GetDummyReadAddr ( + IN OUT MEM_NB_BLOCK *NBPtr, + OUT UINT64 *TestAddr + ) +{ + BOOLEAN DctSelIntlvEn; + UINT8 DramIntlvEn; + UINT8 DctSelIntlvAddr; + UINT8 IntLvRgnBaseAddr; + UINT8 IntLvRgnLmtAddr; + UINT8 IntLvRgnSize; + UINT32 DctSelBaseAddr; + UINT64 TOM; + BOOLEAN AddrFound; + + AddrFound = TRUE; + // Check if Node interleaving is enabled + DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn); + if (DramIntlvEn != 0) { + // Set the address bits that identify the node + *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12; + } else { + *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27; + } + + // Check if channel interleaving is enabled + DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn); + DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr); + if (!DctSelIntlvEn) { + if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { + *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); + } + } else { + DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr); + // Set the address bits that identify the channel + if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) { + *TestAddr |= (UINT64) NBPtr->Dct << 6; + } else if (DctSelIntlvAddr == 1) { + *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1)); + } else if (DctSelIntlvAddr == 3) { + *TestAddr |= (UINT64) NBPtr->Dct << 9; + } + } + // Adding 2M to avoid conflict + *TestAddr += 0x200000; + + // If memory hoisting is disabled, the address can fall into MMIO area + // Need to find an address out of MMIO area but belongs to the channel + // If the whole channel is in MMIO, then do not do dummy read. + // + LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader); + if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) { + if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) { + // This is the DCT that goes to high address range + if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) { + // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr + if (DctSelIntlvEn) { + *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF); + } + } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) { + // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as + // dummy read address + *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); + } else { + AddrFound = FALSE; + } + } else { + // This is the DCT that only goes to low address range + if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) { + // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address + // Keep the lower bits for node and channel selection + *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF); + } else { + AddrFound = FALSE; + } + } + } + + // Interleaved Swap Region handling + if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) { + IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr); + IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr); + IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize); + ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1)); + if (((*TestAddr >> 34) == 0) && + ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr)) + || ((*TestAddr >> 27) < IntLvRgnSize))) { + *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27; + } + } + + return AddrFound; +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c new file mode 100755 index 0000000000..76712ff0e2 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mndct.c @@ -0,0 +1,2053 @@ +/** + * @file + * + * mndct.c + * + * Common Northbridge DCT support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 11758 $ @e \$Date: 2009-04-03 10:58:22 -0500 (Fri, 03 Apr 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "mftds.h" +#include "merrhdl.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNDCT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemNAfterStitchMemNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +UINT8 +MemNGet1KTFawTkNb ( + IN UINT8 k + ); + +UINT8 +MemNGet2KTFawTkNb ( + IN UINT8 k + ); + +VOID +STATIC +MemNQuarterMemClk2NClkNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *SubTotalPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +extern BUILD_OPT_CFG UserOptions; + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function combines all the memory into a contiguous map. + * Requires that Mask values for each bank be programmed first and that + * the chip-select population indicator is correctly set. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNStitchMemoryNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BOOLEAN DSpareEn; + UINT32 NxtCSBase; + UINT32 CurCSBase; + UINT32 CsSize; + UINT32 BiggestBank; + UINT8 p; + UINT8 q; + UINT8 BiggestDimm; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + DCT_STRUCT *DCTPtr; + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + DCTPtr = NBPtr->DCTPtr; + DSpareEn = FALSE; + if (NBPtr->IsSupported[SetSpareEn]) { + DSpareEn = FALSE; + if (RefPtr->GStatus[GsbEnDIMMSpareNW]) { + DSpareEn = TRUE; + } + } + + DCTPtr->Timings.CsEnabled = 0; + NxtCSBase = 0; + for (p = 0; p < MAX_CS_PER_CHANNEL; p++) { + BiggestBank = 0; + BiggestDimm = 0; + for (q = 0; q < MAX_CS_PER_CHANNEL; q++) { + if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) { + if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) { + // (CSEnable|Spare==1)bank is not enabled yet + CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1)); + if (CsSize != 0) { + CsSize += ((UINT32)1 << 19); + CsSize &= 0xFFF80000; + } + if (CsSize > BiggestBank) { + BiggestBank = CsSize; + BiggestDimm = q; + } + } + } + } + + if (BiggestBank != 0) { + CurCSBase = NxtCSBase; + if (NBPtr->IsSupported[CheckSpareEn]) { + if (DSpareEn) { + CurCSBase = ((UINT32)1 << BFSpare); + DSpareEn = FALSE; + } else { + CurCSBase |= ((UINT32)1 << BFCSEnable); + NxtCSBase += BiggestBank; + } + } else { + CurCSBase |= ((UINT32)1 << BFCSEnable); + NxtCSBase += BiggestBank; + } + if ((BiggestDimm & 1) != 0) { + if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) { + CurCSBase |= ((UINT32)1 << BFOnDimmMirror); + } + } + MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase); + DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm); + } + if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) { + MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail); + } + } + + if (NxtCSBase != 0) { + DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16] + MemNAfterStitchMemNb (NBPtr); + } + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets platform specific config/timing values from the interface layer and + * programs them into DCT. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST BIT_FIELD_NAME ChipletPDRegs[] = { + BFPhyClkConfig0, + BFPhyClkConfig3, + BFPhyClkConfig1, + BFPhyClkConfig2 + }; + CONST UINT8 ChipletPDClkDisMap[][2] = { + //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]] + {0, 1}, + //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]] + {6, 7}, + //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]] + {4, 5}, + //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]] + {2, 3}, + //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]] + {2, 5}, + //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]] + {3, 4} + }; + + UINT8 MemClkDis; + UINT8 i; + UINT8 MemoryAllClocks; + UINT8 *MemClkDisMap; + UINT16 CsPresent; + UINT8 RegIndex; + UINT8 Cs1; + UINT8 Cs2; + + if (!MemNGetPlatformCfgNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + MemNProgramPlatformSpecNb (NBPtr); + if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { + IDS_ERROR_TRAP; + } + + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS); + + if (NBPtr->MCTPtr->GangedMode) { + MemNSwitchDCTNb (NBPtr, 1); + if (!MemNGetPlatformCfgNb (NBPtr)) { + IDS_ERROR_TRAP; + } + MemNProgramPlatformSpecNb (NBPtr); + MemNSwitchDCTNb (NBPtr, 0); + } + + //====================================================================== + // Disable unused MemClk to save power + //====================================================================== + // + MemClkDis = 0; + MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; + IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); + if (!MemoryAllClocks) { + // Special Jedec SPD diagnostic bit - "enable all clocks" + if (!NBPtr->MCTPtr->Status[SbDiagClks]) { + MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0)); + if (MemClkDisMap == NULL) { + MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; + } + + // Turn off the unused CS clocks + CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + + if (NBPtr->IsSupported[CheckMemClkCSPresent]) { + if (NBPtr->ChannelPtr->RegDimmPresent != 0) { + // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register + // regardless of how many Ranks are on the DIMM (Single, Dual or Quad) + CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555; + } + } + for (i = 0; i < 8; i++) { + if ((CsPresent & MemClkDisMap[i]) == 0) { + MemClkDis |= (UINT8) (1 << i); + } + } + //Chiplet power down + for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) { + if ((NBPtr->Dct == 1) && (RegIndex >= 2)) { + Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]]; + Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]]; + } else { + Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]]; + Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]]; + } + if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) { + MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10)); + } + } + } + } + MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); + + AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNInitPhyComp (NBPtr); + + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS); + + if (NBPtr->IsSupported[CheckDynamicDramTerm]) { + // Program DramTerm for DDR2 + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) { + MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm); + } else { + // Dynamic Dynamic DramTerm for DDR3 + // Dram Term for DDR3 may vary based on chip selects + MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm); + } + } + // Program DramTerm for DDR2 + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) { + MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm); + } else { + // Dynamic Dynamic DramTerm for DDR3 + // Dram Term for DDR3 may vary based on chip selects + MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm); + } + + MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets platform specific config/timing values from the interface layer and + * programs them into DCT. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNPlatformSpecClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 MemClkDis; + UINT8 i; + UINT8 MemoryAllClocks; + UINT8 *MemClkDisMap; + UINT16 CsPresent; + + if (!MemNGetPlatformCfgNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + MemNProgramPlatformSpecNb (NBPtr); + if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) { + IDS_ERROR_TRAP; + } + + //====================================================================== + // Disable unused MemClk to save power + //====================================================================== + // + MemClkDis = 0; + MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn; + IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader)); + if (!MemoryAllClocks) { + // Special Jedec SPD diagnostic bit - "enable all clocks" + if (!NBPtr->MCTPtr->Status[SbDiagClks]) { + MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct); + if (MemClkDisMap == NULL) { + MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap; + } + + // Turn off unused clocks + CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + + for (i = 0; i < 8; i++) { + if ((CsPresent & MemClkDisMap[i]) == 0) { + MemClkDis |= (UINT8) (1 << i); + } + } + + // Turn off unused chiplets + if ((MemClkDis & 0x3) == 0x3) { + MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0, 0x0010); + } + if ((MemClkDis & 0xC) == 0xC) { + MemNSetBitFieldNb (NBPtr, BFPhyClkConfig1, 0x0010); + } + } + } + MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis); + MemFInitTableDrive (NBPtr, MTAfterPlatformSpec); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function disables the DCT and mem clock + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNDisableDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); + MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); + MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); + + // To maximize power savings when DisDramInterface=1b, + // all of the MemClkDis bits should also be set. + // + MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); + + MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function disables the DCT and mem clock for client NB + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNDisableDCTClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03); + MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F); + MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF); + + //Wait for 24 MEMCLKs + MemUWait10ns (6, NBPtr->MemPtr); + + // To maximize power savings when DisDramInterface=1b, + // all of the MemClkDis bits should also be set. + // + MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); + + MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000); + + MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DRAM devices on all DCTs at the same time + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNStartupDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1. + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp is still being set since InitPhyComp + + if (NBPtr->MCTPtr->NodeMemSize != 0) { + // Init MemClk frequency + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + + + AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNBeforeDramInitNb (NBPtr); + + AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); + NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); + } + + // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0. + // 8. BIOS must wait 750 us for the phy compensation engine + // to reinitialize. + // DisAutoComp will be cleared after DramEnabled turns to 1 + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes the DRAM devices on all DCTs at the same time + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNStartupDCTClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + + // Update NB frequency for startup DDR speed + NBPtr->ChangeNbFrequency (NBPtr); + + // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999. + MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000); + + // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #193770. + MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118); + + // Phy Voltage Level Programming + MemNPhyVoltageLevelClientNb (NBPtr); + + // Run frequency change sequence + MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); + MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + MemNProgramNbPstateDependentRegistersClientNb (NBPtr); + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE ("!\tDct %d\n", Dct); + + // Phy fence programming + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + NBPtr->PhyFenceTraining (NBPtr); + + // Phy compensation initialization + AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNInitPhyComp (NBPtr); + } + } + + // Run DramInit sequence + AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader)); + NBPtr->FeatPtr->DramInit (NBPtr->TechPtr); + +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * MemNChangeFrequencyHy: + * + * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNChangeFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 Dct; + UINT8 ChipSel; + UINT32 Dummy; + + TechPtr = NBPtr->TechPtr; + if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { + // #107421 + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); + } + + //Program F2x[1,0]90[EnterSelfRefresh]=1. + //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. + MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + + //Program F2x9C_x08[DisAutoComp]=1 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + + //Program F2x[1, 0]94[MemClkFreqVal] = 0. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); + + //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency. + MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + + //Program F2x[1, 0]94[MemClkFreqVal] = 1. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + + //Wait until F2x[1, 0]94[FreqChgInProg]=0. + MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE); + + if (NBPtr->IsSupported[CheckPhyFenceTraining]) { + //Perform Phy Fence retraining after frequency changed + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE ("!\tDct %d\n", Dct); + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + MemNPhyFenceTrainingNb (NBPtr); + } + } + } + + //Program F2x9C_x08[DisAutoComp]=0 + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); + + //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. + //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. + MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + + if (NBPtr->MCTPtr->Status[SbRegistered]) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + TechPtr->FreqChgCtrlWrd (TechPtr); + } + } + } + + //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns + MemUWait10ns (125, NBPtr->MemPtr); + + if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) { + // #107421 + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); + } + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE ("!\tDct %d\n", Dct); + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + + //9.Configure the DCT to send initialization MR commands: + // BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. + // Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values. + TechPtr->AutoCycTiming (TechPtr); + if (!MemNPlatformSpecNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (NBPtr->IsSupported[CheckGetMCTSysAddr]) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { + // if chip select present + TechPtr->SendAllMRCmds (TechPtr, ChipSel); + // NOTE: wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + if (NBPtr->IsSupported[CheckSendAllMRCmds]) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { + // if chip select present + TechPtr->SendAllMRCmds (TechPtr, ChipSel); + } + } + } + if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000)); + MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000)); + if (Dct == 0) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000)); + } + // NOTE: wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + } + // Re-enable phy compensation since it had been disabled during InitPhyComp + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function ramp up frequency the next level if it have not reached + * its TargetSpeed yet. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNRampUpFrequencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 FreqList[] = { + DDR400_FREQUENCY, + DDR533_FREQUENCY, + DDR667_FREQUENCY, + DDR800_FREQUENCY, + DDR1066_FREQUENCY, + DDR1333_FREQUENCY, + DDR1600_FREQUENCY, + DDR1866_FREQUENCY + }; + UINT8 Dct; + UINT8 i; + UINT16 NewSpeed; + DIE_STRUCT *MCTPtr; + + MCTPtr = NBPtr->MCTPtr; + + // Do not change frequency when it is already at TargetSpeed + if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) { + return TRUE; + } + + // Find the next supported frequency level + NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed; + for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) { + if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) { + NewSpeed = FreqList[i + 1]; + break; + } + } + ASSERT (i < (GET_SIZE_OF (FreqList) - 1)); + ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed); + + // BIOS must program both DCTs to the same frequency. + IDS_HDT_CONSOLE ("\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed); + for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + NBPtr->DCTPtr->Timings.Speed = NewSpeed; + } + IDS_HDT_CONSOLE (" -> %d MHz", NewSpeed); + + IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader)); + NBPtr->ChangeFrequency (NBPtr); + + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function uses calculated values from DCT.Timings structure to + * program its registers. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramCycTimingsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST CTENTRY TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 4, 12, 4, 2}, + {BFTrcd, 5, 12, 5, 2}, + {BFTrp, 5, 12, 5, 2}, + {BFTrtp, 4, 7, 4, 2}, + {BFTras, 15, 30, 15, 2}, + {BFTrc, 11, 42, 11, 2}, + {BFTwrDDR3, 5, 12, 4, 2}, + {BFTrrd, 4, 7, 4, 2}, + {BFTwtr, 4, 7, 4, 2}, + {BFFourActWindow, 16, 32, 14, 1} + }; + + DCT_STRUCT *DCTPtr; + UINT8 *MiniMaxTmg; + UINT8 *MiniMaxTrfc; + UINT8 Value8; + UINT8 j; + BIT_FIELD_NAME BitField; + + DCTPtr = NBPtr->DCTPtr; + + //====================================================================== + // Program turnaround timings to their max during DRAM init and training + //====================================================================== + // + MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF); + + MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A); + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + MiniMaxTmg = &DCTPtr->Timings.CasL; + for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { + BitField = TmgAdjTab[j].BitField; + + if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { + MiniMaxTmg[j] = TmgAdjTab[j].Min; + } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { + MiniMaxTmg[j] = TmgAdjTab[j].Max; + } + + Value8 = (UINT8) MiniMaxTmg[j]; + + if (BitField == BFTwrDDR3) { + Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8; + } else if (BitField == BFTrtp) { + Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6; + } + + Value8 = Value8 - TmgAdjTab[j].Bias; + Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; + + MemNSetBitFieldNb (NBPtr, BitField, Value8); + } + + MiniMaxTrfc = &DCTPtr->Timings.Trfc0; + for (j = 0; j < 4; j++) { + MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); + } + + MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? + (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0)); + + MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us + + //====================================================================== + // DRAM MRS Register, set ODT + //====================================================================== + // + // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7) + MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1); + + // burst length control + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2); + } + + // ASR=1, auto self refresh; SRT=0 + MemNSetBitFieldNb (NBPtr, BFASR, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function uses calculated values from DCT.Timings structure to + * program its registers. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramCycTimingsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST CTENTRY TmgAdjTab[] = { + // BitField, Min, Max, Bias, Ratio_x2 + {BFTcl, 5, 14, 4, 2}, + {BFTrcd, 5, 14, 5, 2}, + {BFTrp, 5, 14, 5, 2}, + {BFTrtp, 4, 8, 4, 2}, + {BFTras, 15, 36, 15, 2}, + {BFTrc, 20, 49, 11, 2}, + {BFTwrDDR3, 5, 16, 4, 2}, + {BFTrrd, 4, 8, 4, 2}, + {BFTwtr, 4, 8, 4, 2}, + {BFFourActWindow, 16, 40, 14, 1} + }; + + DCT_STRUCT *DCTPtr; + UINT8 *MiniMaxTmg; + UINT8 *MiniMaxTrfc; + UINT8 Value8; + UINT8 j; + UINT8 Tcwl; + BIT_FIELD_NAME BitField; + + DCTPtr = NBPtr->DCTPtr; + + //====================================================================== + // Program DRAM Timing values + //====================================================================== + // + MiniMaxTmg = &DCTPtr->Timings.CasL; + for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) { + BitField = TmgAdjTab[j].BitField; + + if (MiniMaxTmg[j] < TmgAdjTab[j].Min) { + MiniMaxTmg[j] = TmgAdjTab[j].Min; + } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) { + MiniMaxTmg[j] = TmgAdjTab[j].Max; + } + + Value8 = (UINT8) MiniMaxTmg[j]; + + if (BitField == BFTwrDDR3) { + Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8; + } + + Value8 = Value8 - TmgAdjTab[j].Bias; + Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1; + + MemNSetBitFieldNb (NBPtr, BitField, Value8); + } + + MiniMaxTrfc = &DCTPtr->Timings.Trfc0; + for (j = 0; j < 4; j++) { + MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]); + } + + Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2; + MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0)); + + MemNSetBitFieldNb (NBPtr, BFTref, 2); // Tref = 7.8 us + + MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (DCTPtr->Timings.Trcd > 10) ? 0 : 1); + + MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0); + + // Set ProcOdtAdv + if (DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) & 0xBFFF)); + } else { + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x4000)); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets platform specific settings for the current channel + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - All platform types defined have initialized successfully + * @return FALSE - At least one of the platform types gave not been initialized successfully + */ + +BOOLEAN +MemNGetPlatformCfgNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 p; + + for (p = 0; p < MAX_PLATFORM_TYPES; p++) { + ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL); + if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) { + break; + } + } + return (p < MAX_PLATFORM_TYPES); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function retrieves the Max latency parameters + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value + * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value + * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + */ + +VOID +MemNGetMaxLatParamsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ) +{ + *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2; + MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr); + + *MaxDlyPtr = 0x3FF; + + *DlyBiasPtr = 4; + MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr); // 1 MEMCLK Margin + + *DlyBiasPtr += 1; // add 1 NCLK +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function retrieves the Max latency parameters + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value + * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value + * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value + * @param[in] MaxDlyForMaxRdLat - Maximum receiver enable delay value + * + */ + +VOID +MemNGetMaxLatParamsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxDlyForMaxRdLat, + IN OUT UINT16 *MinDlyPtr, + IN OUT UINT16 *MaxDlyPtr, + IN OUT UINT16 *DlyBiasPtr + ) +{ + UINT32 P; + UINT32 T; + UINT32 MemClkPeriod; + + T = MemNTotalSyncComponentsClientNb (NBPtr); + + // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime)) + P = (MaxDlyForMaxRdLat + 31) / 32; + + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + + *MinDlyPtr = (UINT16) (((((P * MemClkPeriod + 1) / 2) + T) * NBPtr->NBClkFreq + 999999) / 1000000); + + *MinDlyPtr += 4; + + *MaxDlyPtr = 0x50; + + *DlyBiasPtr = 3; + + // Need to set ForceCasToSlot0=1 before MaxRdLatency training + MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the maximum round-trip latency in the system from the processor to the DRAM + * devices and back. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] MaxRcvEnDly - Maximum receiver enable delay value + * + */ + +VOID +MemNSetMaxLatencyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 MaxRcvEnDly + ) +{ + UINT16 SubTotal; + + AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader)); + + SubTotal = 0xC8; // init value for MaxRdLat used in training + + + if (MaxRcvEnDly != 0xFFFF) { + // Get all sync components BKDG steps 1-5 + SubTotal = MemNTotalSyncComponentsNb (NBPtr); + + // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay + // that exists across all DIMMs and byte lanes. + // + SubTotal += MaxRcvEnDly >> 5; + + + // Add 14.5 to the sub-total. 14.5 represents part of the processor + // specific constant delay value in the DRAM clock domain. + // + SubTotal <<= 1; // scale 1/2 MemClk to 1/4 MemClk + SubTotal += 29; // add 14.5 1/2 MemClk + + // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs) + // as follows (assuming DDR400 and assuming that no P-state or link speed + // changes have occurred). + // + MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal); + + // Add 2 NCLKs to the sub-total. 2 represents part of the processor + // specific constant value in the northbridge clock domain. + // + SubTotal += 2; + } + + NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal; + // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value + IDS_HDT_CONSOLE ("\t\tMaxRdLat: %03x\n", SubTotal); + MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sends the ZQCL command + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSendZQCmdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // 1.Program MrsAddress[10]=1 + MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10); + + // 2.Set SendZQCmd=1 + MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1); + + // 3.Wait for SendZQCmd=0 + MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE); + + // 4.Wait 512 MEMCLKs + MemUWait10ns (128, NBPtr->MemPtr); // 512*2.5ns=1280, wait 1280ns +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function is used to create the DRAM map + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + */ + +VOID +STATIC +MemNAfterStitchMemNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->MCTPtr->GangedMode) { + NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize; + NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; + NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent; + NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize; + } else { + // In unganged mode, add DCT0 and DCT1 to NodeMemSize + NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize; + NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1; + } +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Return the binary value of tfaw associated with + * the index k + * + * @param[in] k value + * + * @return F[k], in Binary MHz. + */ + +UINT8 +MemNGet1KTFawTkNb ( + IN UINT8 k + ) +{ + CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19}; + ASSERT (k <= 5); + return Tab1KTfawTK[k]; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function Return the binary value of the 2KTFaw associated with + * the index k + * + * @param[in] k value + * + * @return 2KTFaw converted based on k. + */ + +UINT8 +MemNGet2KTFawTkNb ( + IN UINT8 k + ) +{ + CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24}; + ASSERT (k <= 5); + return Tab2KTfawTK[k]; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs) + * (assuming DDR400 and assuming that no P-state or link speed + * changes have occurred). + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *SubTotalPtr - pointer to Sub-Total + */ + +VOID +STATIC +MemNQuarterMemClk2NClkNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *SubTotalPtr + ) +{ + UINT32 NBFreq; + UINT32 MemFreq; + + // Multiply SubTotal by NB COF + NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; + // Divide SubTotal by 4 times current MemClk frequency + MemFreq = NBPtr->DCTPtr->Timings.Speed * 4; + *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the total of sync components for Max Read Latency calculation + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Total in 1/2 MEMCLKs + */ + +UINT16 +MemNTotalSyncComponentsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT16 SubTotal; + + // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs. + SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1; + if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) { + SubTotal += 3; + } + SubTotal *= 2; + + // If registered DIMMs are being used then add 1 MEMCLK to the sub-total. + if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) { + SubTotal += 2; + } + + // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1 + // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2 + if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { + SubTotal += 1; + } else { + SubTotal += 2; + } + + // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs, + // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total. + // + SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit)); + + return SubTotal; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function swaps bits for OnDimmMirror support + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSwapBitsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 ChipSel; + UINT32 MRSReg; + + ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel); + if ((ChipSel & 1) != 0) { + MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg); + if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) { + MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1); + MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Programs Address/command timings, driver strengths, and tri-state fields. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNProgramPlatformSpecNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 PinType[3] = {PSO_CKE_TRI, PSO_ODT_TRI, PSO_CS_TRI}; + CONST UINT8 TabSize[3] = { 2, 4, 8}; + CONST BIT_FIELD_NAME BitField[3] = { BFCKETri, BFODTTri, BFChipSelTri}; + UINT8 *TabPtr; + UINT8 i; + UINT8 k; + UINT8 Value; + //=================================================================== + // Tristate unused CKE, ODT and chip select to save power + //=================================================================== + // + TabPtr = NULL; + for (k = 0; k < sizeof (PinType); k++) { + if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) { + TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0)); + } + if (NBPtr->IsSupported[CheckFindPSDct]) { + TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct); + } + if (TabPtr == NULL) { + switch (k) { + case 0: + TabPtr = NBPtr->ChannelPtr->CKETriMap; + break; + case 1: + TabPtr = NBPtr->ChannelPtr->ODTTriMap; + break; + case 2: + TabPtr = NBPtr->ChannelPtr->ChipSelTriMap; + break; + default: + IDS_ERROR_TRAP; + } + } + ASSERT (TabPtr != NULL); + + Value = 0; + for (i = 0; i < TabSize[k]; i++) { + if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) { + Value |= (UINT8) (1 << i); + } + } + MemNSetBitFieldNb (NBPtr, BitField[k], Value); + } + NBPtr->MemNBeforePlatformSpecNb (NBPtr); + + //=================================================================== + // Program Address/Command timings and driver strength + //=================================================================== + // + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS); + MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS); + + MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0); + MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl); + MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg); + + if (NBPtr->IsSupported[CheckODTControls]) { + MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow); + MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh); + MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow); + MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh); + } +} +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Trdrd value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Trdrd value + */ + +UINT8 +MemNGetTrdrdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DCT_STRUCT *DCTPtr; + INT8 Cgdd; + + DCTPtr = NBPtr->DCTPtr; + + // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the + // converted field value. BIOS rounds fractional values down. + // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1, + // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1, + // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM. + + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly); + DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3; + + // Transfer clk to reg definition, 2T is 00b, etc. + DCTPtr->Timings.Trdrd -= 2; + if (DCTPtr->Timings.Trdrd > 8) { + DCTPtr->Timings.Trdrd = 8; + } + + return DCTPtr->Timings.Trdrd; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Twrwr value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Twrwr value + */ + +UINT8 +MemNGetTwrwrNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DCT_STRUCT *DCTPtr; + INT8 Cgdd; + + DCTPtr = NBPtr->DCTPtr; + + // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the + // converted field value. BIOS rounds fractional values down. + // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6, + // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, + // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross + // Delay Difference (CGDD) for Twrwr. + + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly); + DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3; + NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr); + + return DCTPtr->Timings.Twrwr; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs + * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional + * values down. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Value to be programmed to Twrrd field + * pDCT->Timings.Twrrd updated + */ + +UINT8 +MemNGetTwrrdNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Cgdd; + INT8 Ld; + INT8 Twrrd; + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + + // + // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS + // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive + // value. + // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). + // + Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); + + // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM + // minus the DqsRcvEnGrossDelay delay of any other DIMM is + // equal to the Critical Gross Delay Difference (CGDD) for Twrrd. + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly); + Twrrd = (Cgdd / 2) - Ld + 3; + DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0); + NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr); + + return DCTPtr->Timings.Twrrd; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the TrwtTO value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return pDCT->Timings.TrwtTO updated + */ + +UINT8 +MemNGetTrwtTONb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + INT8 Cgdd; + INT8 Ld; + INT8 TrwtTO; + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + // + // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS + // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive + // value. + // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1). + // + Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr); + + // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus + // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross + // Delay Difference (CGDD) for TrwtTO. + Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly); + TrwtTO = (Cgdd / 2) + Ld + 3; + TrwtTO -= 2; + DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1); + + return DCTPtr->Timings.TrwtTO; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the TrwtWB value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TrwtWB value + */ +UINT8 +MemNGetTrwtWBNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + DCT_STRUCT *DCTPtr; + + DCTPtr = NBPtr->DCTPtr; + + // TrwtWB ensures read-to-write data-bus turnaround. + // This value should be one more than the programmed TrwtTO. + return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts MemClk frequency in MHz to MemClkFreq value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Speed - MemClk frequency in MHz + * + * @return MemClkFreq value + */ +UINT8 +MemNGetMemClkFreqIdNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ) +{ + return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables swapping interleaved region feature. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Base - Swap interleaved region base [47:27] + * @param[in] Limit - Swap interleaved region limit [47:27] + * + */ +VOID +MemNEnableSwapIntlvRgnNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN UINT32 Limit + ) +{ + UINT32 Size; + UINT32 SizeOfAlign; + + // Swapped interleaving region must be below 16G + if (Limit < (1 << (34 - 27))) { + // Adjust Base and Size to meet : + // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase]. + // 2. Entire UMA region is swapped with interleaving region. + Size = Limit - Base; + SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); + while (SizeOfAlign <= Size) { + // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB. + Base -= 1; + Size += 1; + SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base); + } + MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base); + MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1)); + MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size); + MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function converts MemClk frequency in MHz to MemClkFreq value + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Speed - MemClk frequency in MHz + * + * @return MemClkFreq value + */ +UINT8 +MemNGetMemClkFreqIdClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT16 Speed + ) +{ + return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55))); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed + * for client NB. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNChangeFrequencyClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 Dct; + UINT8 ChipSel; + UINT32 Dummy; + BOOLEAN FrequencyChangeSuccess; + + TechPtr = NBPtr->TechPtr; + + // 1. Program D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0190h for Llano + // 1. Program D18F2x9C_x0D0F_E006[PllLockTime] = 1838h for Ontario + MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault); + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1); + + //Program F2x[1,0]90[EnterSelfRefresh]=1. + //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0. + MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + + if (NBPtr->ChangeNbFrequency (NBPtr)) { + // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0); + + // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency. + MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed)); + + // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. + // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, + // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule + // Delay Programming]. + // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) + // THEN 2 ELSE 3 ENDIF (Ontario) + MemNProgramNbPstateDependentRegistersClientNb (NBPtr); + + // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1. + MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1); + + FrequencyChangeSuccess = TRUE; + } else { + // If NB frequency cannot be updated, use the current speed as the target speed + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed; + NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed; + } + FrequencyChangeSuccess = FALSE; + } + + //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs. + //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0. + MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1); + MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE); + MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0); + + // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program + // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh. + // (CsrPhySrPllPdMode is kept 0 before training) + MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F); + + if (FrequencyChangeSuccess) { + // Perform Phy Fence training and Phy comp init after frequency change + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + IDS_HDT_CONSOLE ("!\tDct %d\n", Dct); + + // Phy fence programming + AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader)); + NBPtr->PhyFenceTraining (NBPtr); + + // Phy compensation initialization + AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader)); + NBPtr->MemNInitPhyComp (NBPtr); + } + } + + //====================================================================== + // Calculate and program DRAM Timings at new frequency + //====================================================================== + // + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + IDS_HDT_CONSOLE ("!\tDct %d\n", Dct); + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + + //9.Configure the DCT to send initialization MR commands: + // BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency. + TechPtr->AutoCycTiming (TechPtr); + if (!MemNPlatformSpecNb (NBPtr)) { + IDS_ERROR_TRAP; + } + + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) { + // if chip select present + TechPtr->SendAllMRCmds (TechPtr, ChipSel); + } + } + // Wait 512 clocks for DLL-relock + MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us + } + } + } +} + + +/* -----------------------------------------------------------------------------*/ +CONST UINT16 PllDivTab[10] = {1, 2, 4, 8, 16, 128, 256, 1, 3, 6}; + +/** + * + * This function calculates and programs NB P-state dependent registers + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNProgramNbPstateDependentRegistersClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 i; + UINT8 Dct; + UINT8 NclkFid; + UINT16 MemClkDid; + UINT8 PllMult; + UINT8 NclkDiv; + UINT8 RdPtrInitMin; + UINT8 RdPtrInit; + UINT32 NclkPeriod; + UINT32 MemClkPeriod; + INT32 PartialSum2x; + INT32 PartialSumSlotI2x; + + NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 10); + ASSERT (MemNGetBitFieldNb (NBPtr, BFPllDiv) < 10); + MemClkDid = PllDivTab[MemNGetBitFieldNb (NBPtr, BFPllDiv)]; + PllMult = (UINT8) MemNGetBitFieldNb (NBPtr, BFPllMult); + if (MemNGetBitFieldNb (NBPtr, BFNbPs1Act) == 1) { + NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv); + IDS_HDT_CONSOLE ("\n\tNB P1"); + } else { + NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv); + IDS_HDT_CONSOLE ("\n\tNB P0"); + } + NclkPeriod = (2500 * NclkDiv) / NclkFid; + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + RdPtrInitMin = RdPtrInit = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; + ASSERT (NBPtr->NBClkFreq == (((UINT32) NclkFid * 400) / NclkDiv)); + + IDS_HDT_CONSOLE (" Freq: %lxMHz\n", NBPtr->NBClkFreq); + IDS_HDT_CONSOLE ("\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed); + // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano) + // THEN 2 ELSE 3 ENDIF (Ontario) + MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit); + IDS_HDT_CONSOLE ("\t\tRdPtr: %d\n", RdPtrInit); + + // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator]. + MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16); + MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv); + IDS_HDT_CONSOLE ("\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16); + IDS_HDT_CONSOLE ("\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv); + + // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1, + // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. + // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - + // CmdSetup - PtrSeparation - 1. (Llano) + // PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL - + // CmdSetup - PtrSeparation - 1. (Ontario) + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod; + PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod; + PartialSum2x += 520 * 2; + PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here + PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); + if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) { + PartialSum2x -= 1; + } else { + PartialSum2x -= 2; + } + PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16); + PartialSum2x -= 2; + + // If PartialSumSlotN is positive: + // DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN). + // DataTxFifoSchedDlyNegSlotN=0. + // Else if PartialSumSlotN is negative: + // DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)). + // DataTxFifoSchedDlyNegSlotN=1. + for (i = 0; i < 2; i++) { + PartialSumSlotI2x = PartialSum2x; + if ((i == 0) && (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 0)) { + PartialSumSlotI2x += 2; + } + if (PartialSumSlotI2x > 0) { + ASSERT ((i != 0) && (PartialSumSlotI2x <= 2)); // Real system constrain + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2); + IDS_HDT_CONSOLE ("\t\tDataTxFifoSchedDlySlot%d: %lx\n", i, (PartialSumSlotI2x + 1) / 2); + } else { + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1); + PartialSumSlotI2x = (((-PartialSumSlotI2x) * MemClkPeriod) + (2 * NclkPeriod - 1)) / (2 * NclkPeriod); + MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x); + IDS_HDT_CONSOLE ("\t\tDataTxFifoSchedDlySlot%d: -%lx\n", i, PartialSumSlotI2x); + } + } + } + } + + MemFInitTableDrive (NBPtr, MTAfterNbPstateChange); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the total of sync components for Max Read Latency calculation + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Total in 1/2 MEMCLKs + */ + +UINT32 +MemNTotalSyncComponentsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 P; + UINT32 T; + UINT8 RdPtrInitMin; + UINT8 RdPtrInit; + UINT32 AddrTmgCtl; + UINT8 DbeGskMemClkAlignMode; + UINT32 MemClkPeriod; + + // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) + RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667; + RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit); + P = (16 + RdPtrInitMin - RdPtrInit) % 16; + + // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1 + AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl); + if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) { + P += 1; + } + + // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup))) + // THEN P = P + 1 + DbeGskMemClkAlignMode = 2; // from BKDG recommendation. + if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) && + !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) { + P += 1; + } + + // IF (SlowAccessMode==1) THEN P = P + 2 + if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) { + P += 2; + } + + // IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) + // THEN T = T + MemClkPeriod - 786 ps + // ELSE T = T + (0.5 * MemClkPeriod) - 786 ps + MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed; + if (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) { + T = MemClkPeriod - 786; + } else { + T = (MemClkPeriod / 2) - 786; + } + + // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0) + // then P = P + 1 + // else P = P + 2 + if ((AddrTmgCtl & 0x0202020) == 0) { + P += 1; + } else { + P += 2; + } + + // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1)) + P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1); + + // If (DisCutThroughMode==0) + // then P = P + 3 + // else P = P + 7 + if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) { + P += 3; + } else { + P += 7; + } + + return (((P * MemClkPeriod + 1) / 2) + T); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets up phy power saving for client NB + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNPhyPowerSavingClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b. + // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b. + // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b. + MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3); + // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins. + MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, 0xA1); + // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1. + MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100); + // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <= + // 800 MHz) THEN 1 ELSE 0 ENDIF. + MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0); + // 10. Program D18F2x[1,0]9C_x0000_000D as follows: + // TxMaxDurDllNoLock/RxMaxDurDllNoLock = 9h. + MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 9); + MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 9); + // TxCPUpdPeriod/RxCPUpdPeriod = 000b. + MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 0); + MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 0); + // TxDLLWakeupTime/RxDLLWakeupTime = 11b. + MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3); + MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3); +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c new file mode 100755 index 0000000000..1b462a996d --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnfeat.c @@ -0,0 +1,560 @@ +/** + * @file + * + * mnfeat.c + * + * Common Northbridge features + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define MAX_CL_CONT_READ 32 +#define MAX_CL_CONT_WRITE 32 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +VOID +STATIC +MemNContWritePatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +STATIC +MemNContReadPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +STATIC +MemNGenHwRcvEnReadsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ); + +UINT16 +STATIC +MemNCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ); + +UINT16 +STATIC +MemNInsDlyCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ); + +VOID +STATIC +MemNContWritePatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ); + +VOID +STATIC +MemNContReadPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ); + +VOID +STATIC +MemNGenHwRcvEnReadsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +VOID +MemNInitCPGClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function assigns read/write function pointers to CPG read/write modules. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNInitCPGNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); +VOID +MemNInitCPGNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->WritePattern = MemNContWritePatternNb; + NBPtr->ReadPattern = MemNContReadPatternNb; + NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb; +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function writes 9 or 18 cache lines continuously using GH CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern - Array of bytes that will be written to DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ +VOID +STATIC +MemNContWritePatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + UINT16 ClDiff; + if (ClCount > MAX_CL_CONT_WRITE) { + ClDiff = ClCount - MAX_CL_CONT_WRITE; + ClCount = MAX_CL_CONT_WRITE; + } else { + ClDiff = 0; + } + + // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst. + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount); + + // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set + // again), all the writes are written to DRAM. + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + MemUWriteCachelines (Address, Pattern, ClCount); + + // Flush out prior writes by setting F2x11C[FlushWr]. + MemNSetBitFieldNb (NBPtr, BFFlushWr, 1); + // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed. + while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {} + + // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting. + MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F); + + if (ClDiff > 0) { + MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads 9 or 18 cache lines continuously using GH CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +STATIC +MemNContReadPatternNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + BOOLEAN DisAutoRefresh; + UINT16 ClDiff; + if (ClCount > MAX_CL_CONT_READ) { + ClDiff = ClCount - MAX_CL_CONT_READ; + ClCount = MAX_CL_CONT_READ; + } else { + ClDiff = 0; + } + + Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr); + + // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads. + // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64 + // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices + // to change to an 8-beat burst length and then to restore the desired burst length after training + // is complete. + + if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) { + DisAutoRefresh = FALSE; + // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1. + // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description. + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1); + // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); // ForceAutoPchg is 0 by default. + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0); + } else { + DisAutoRefresh = TRUE; + } + + MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0); + + // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the + // training sequence. + MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1); + + // 6. BIOS sets F2x11C[PrefDramTrainMode] bit. + // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor + // table (removing any existing prefetch stride patterns). + MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1); + + // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes. + // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS + // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must + // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary. + // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to + // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears + // F2x11C[PrefDramTrainMode]. + MemUDummyCLRead (Address); + MemUDummyCLRead (Address + 0x40); + if (NBPtr->IsSupported[CheckDummyCLRead]) { + MemUDummyCLRead (Address + 0x80); + } + // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after + // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines + // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches + // and read the data from the prefetch buffer. + while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {} + MemUReadCachelines (Buffer, Address, ClCount); + + // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and + // F2x[1, 0]90[BurstLength32]. + if (!DisAutoRefresh) { + MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0); + MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2); + } + + if (ClDiff > 0) { + MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function generates a continuous burst of reads during HW RcvEn training. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - System Address [47:16] + * + */ +VOID +STATIC +MemNGenHwRcvEnReadsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ) +{ + UINT8 TempBuffer[12 * 64]; + UINT8 BurstCount; + + for (BurstCount = 0; BurstCount < 10; BurstCount++) { + NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12); + NBPtr->FlushPattern (NBPtr, Address, 12); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function writes cache lines continuously using TCB CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Pattern - Array of bytes that will be written to DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ +VOID +STATIC +MemNContWritePatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address, + IN UINT8 Pattern[], + IN UINT16 ClCount + ) +{ + UINT32 PatternHash; + UINT32 *DwordPtr; + UINT16 i; + + // 1. Program D18F2x1C0[WrDramTrainMode]=1. + MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1); + + PatternHash = (ClCount << 24) | (Pattern[9] << 16) | (Pattern[64 + 9] << 8) | Pattern[2 * 64 + 9]; + if (NBPtr->CPGInit != PatternHash) { + // If write training buffer has not been initialized, initialize it + // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. + MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount); + + // 3. Program D18F2x1D0[WrTrainBufAddr]=000h. + MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); + + // 4. Successively write each dword of the training pattern to D18F2x1D4. + DwordPtr = (UINT32 *) Pattern; + for (i = 0; i < (ClCount * 16); i++) { + MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]); + } + + NBPtr->CPGInit = PatternHash; + } + + // 5. Program D18F2x1D0[WrTrainBufAddr]=000h + MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); + + // 6. Program the DRAM training address + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); + + // 7. Program D18F2x1C0[WrTrainGo]=1. + MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1); + + // 8. Wait for D18F2x1C0[WrTrainGo]=0. + while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {} + + // 9. Program D18F2x1C0[WrDramTrainMode]=0. + MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function reads cache lines continuously using TCB CPG engine + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM + * @param[in] Address - System Address [47:16] + * @param[in] ClCount - Number of cache lines + * + */ + +VOID +STATIC +MemNContReadPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT32 Address, + IN UINT16 ClCount + ) +{ + // 1. Program D18F2x1C0[RdDramTrainMode]=1. + MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1); + + // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines. + MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount); + + // 3. Program the DRAM training address as follows: + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6)); + MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3); + + // 4. Program D18F2x1D0[WrTrainBufAddr]=000h + MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0); + + // 5. Program D18F2x1C0[RdTrainGo]=1. + MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1); + + // 6. Wait for D18F2x1C0[RdTrainGo]=0. + while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {} + + // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2]. + // This step will be accomplished in Compare routine. + + // 8. Program D18F2x1C0[RdDramTrainMode]=0. + MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function generates a continuous burst of reads during HW RcvEn training. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Address - System Address [47:16] + * + */ +VOID +STATIC +MemNGenHwRcvEnReadsClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Address + ) +{ + UINT8 TempBuffer[64]; + UINT8 Count; + + for (Count = 0; Count < 3; Count++) { + NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function assigns read/write function pointers to CPG read/write modules. + * + * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNInitCPGClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->WritePattern = MemNContWritePatternClientNb; + NBPtr->ReadPattern = MemNContReadPatternClientNb; + NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb; + NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet; + NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb; + NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb; + NBPtr->CPGInit = 0; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @return PASS - Bitmap of results of comparison + */ + +UINT16 +STATIC +MemNCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts)); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function compares test pattern with data in buffer and + * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare + * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against + * @param[in] ByteCount - Byte count + * + * @retval Bitmap of results of comparison + */ +UINT16 +STATIC +MemNInsDlyCompareTestPatternClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Buffer[], + IN UINT8 Pattern[], + IN UINT16 ByteCount + ) +{ + return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2)); +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c new file mode 100755 index 0000000000..f6af51c50f --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnflow.c @@ -0,0 +1,258 @@ +/** + * @file + * + * mnflow.c + * + * Common Northbridge initializer flow for MCT and DCT + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemNInitDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +VOID +STATIC +MemNCleanupDctRegsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the MCT with initial values + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS) + * @return FALSE - AGESA_FATAL error occurred + */ + +BOOLEAN +MemNInitMCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + UINT8 Dct; + BOOLEAN Flag; + + TechPtr = NBPtr->TechPtr; + // Switch Tech functions for Nb + NBPtr->TechBlockSwitch (NBPtr); + // Start Memory controller initialization sequence + Flag = FALSE; + if (TechPtr->DimmPresence (TechPtr)) { + AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader)); + if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) { + AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader)); + if (TechPtr->SpdCalcWidth (TechPtr)) { + AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader)); + if (TechPtr->SpdGetTargetSpeed (TechPtr)) { + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + NBPtr->SwitchDCT (NBPtr, Dct); + + Flag |= MemNInitDCTNb (NBPtr); + } + + if (Flag && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) { + MemFInitTableDrive (NBPtr, MTBeforeDInit); + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + AgesaHookBeforeDramInit (0, NBPtr->MemPtr); + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader)); + IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader)); + NBPtr->StartupDCT (NBPtr); + } + } + } + } + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL); +} + + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function programs the DCT with initial values + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - Error did not occur + * @return FALSE - Error occurred + */ + +BOOLEAN +STATIC +MemNInitDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + TechPtr = NBPtr->TechPtr; + TechPtr->SetDramMode (TechPtr); + + if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) { + if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) { + NBPtr->DisableDCT (NBPtr); + } else { + MemNCleanupDctRegsNb (NBPtr); + if (TechPtr->AutoCycTiming (TechPtr)) { + if (TechPtr->SpdSetBanks (TechPtr)) { + if (NBPtr->StitchMemory (NBPtr)) { + // if all dimms on a DCT are disabled, the DCT needs to be disabled. + if (NBPtr->DCTPtr->Timings.CsEnabled != 0) { + if (NBPtr->AutoConfig (NBPtr)) { + if (NBPtr->PlatformSpec (NBPtr)) { + return TRUE; + } + } + } else { + NBPtr->DisableDCT (NBPtr); + } + } + } + } + } + } + return FALSE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function selects appropriate Tech functions for the NB. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNTechBlockSwitchNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + + // Specify Dimm-Byte training for Nb + MemTDimmByteTrainInit (TechPtr); + + // Filter included for RcvrEn training. + // note: If you'd like to drop the filter, you have to comment out these two lines together. + TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3; + TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter; +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * This function clears DCT registers + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +STATIC +MemNCleanupDctRegsNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BIT_FIELD_NAME BitField; + + for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) { + MemNSetBitFieldNb (NBPtr, BitField, 0); + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c new file mode 100755 index 0000000000..2ad6e1255b --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnmct.c @@ -0,0 +1,1043 @@ +/** + * @file + * + * mnmct.c + * + * Northbridge Common MCT supporting functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 11793 $ @e \$Date: 2009-04-06 15:08:53 -0500 (Mon, 06 Apr 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mu.h" +#include "OptionMemory.h" +#include "PlatformMemoryConfiguration.h" +#include "GeneralServices.h" +#include "cpuFeatures.h" +#include "merrhdl.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNMCT_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define _16MB_RJ16 0x0100 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +BOOLEAN +STATIC +MemNSetMTRRrangeNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN OUT UINT32 *LimitPtr, + IN UINT32 MtrrAddr, + IN UINT8 MtrrType + ); + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets initial values in BUCFG and BUCFG2 + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNInitializeMctNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_DATA_STRUCT *MemPtr; + S_UINT64 SMsr; + + MemPtr = NBPtr->MemPtr; + + if (NBPtr->Node == BSP_DIE) { + LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (SMsr.lo & ((UINT32)1 << 15)) { + NBPtr->ClToNbFlag = 1; + } + SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis + LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + } + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Get max frequency from OEM platform definition, from + * any user override (limiting) of max frequency, and + * from any Si Revision Specific information. Return + * the least of these three in DIE_STRUCT.Timings.TargetSpeed. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSyncTargetSpeedNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT16 DdrMaxRateTab[] = { + UNSUPPORTED_DDR_FREQUENCY, + DDR1600_FREQUENCY, + DDR1333_FREQUENCY, + DDR1066_FREQUENCY, + DDR800_FREQUENCY, + DDR667_FREQUENCY, + DDR533_FREQUENCY, + DDR400_FREQUENCY + }; + + UINT8 Dct; + UINT8 Channel; + UINT16 MinSpeed; + UINT16 DdrMaxRate; + DCT_STRUCT *DCTPtr; + USER_MEMORY_TIMING_MODE *ChnlTmgMod; + USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET]; + MEMORY_BUS_SPEED MemClkFreq; + MEMORY_BUS_SPEED ProposedFreq; + + ASSERT (NBPtr->DctCount <= sizeof (Mode)); + MinSpeed = 16000; + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + DCTPtr = NBPtr->DCTPtr; + + // Check if input user time mode is valid or not + ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) || + (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) || + (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO)); + Mode[Dct] = NBPtr->RefPtr->UserTimingMode; + // Check if input clock value is valid or not + ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? + (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) : + (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY)); + MemClkFreq = NBPtr->RefPtr->MemClockValue; + if (DCTPtr->Timings.DctDimmValid != 0) { + Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0); + ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel); + if (ChnlTmgMod != NULL) { + // Check if input user timing mode is valid or not + ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) || + (ChnlTmgMod[0] != TIMING_MODE_AUTO)); + if (ChnlTmgMod[0] != TIMING_MODE_AUTO) { + Mode[Dct] = ChnlTmgMod[0]; + // Check if input clock value is valid or not + ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? + ((MEMORY_BUS_SPEED)ChnlTmgMod[1] >= DDR667_FREQUENCY) : + ((MEMORY_BUS_SPEED)ChnlTmgMod[1] <= DDR1066_FREQUENCY)); + MemClkFreq = ChnlTmgMod[1]; + } + } + + ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit; + if (Mode[Dct] == TIMING_MODE_LIMITED) { + if (MemClkFreq < ProposedFreq) { + ProposedFreq = MemClkFreq; + } + } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) { + ProposedFreq = MemClkFreq; + } + + if (Mode[Dct] == TIMING_MODE_SPECIFIC) { + DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; + } else { + // "limit" mode + if (DCTPtr->Timings.TargetSpeed > ProposedFreq) { + DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq; + } + } + + IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) { + // + //Call Platform POR Frequency Override + // + if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) { + // + // Get the POR frequency limit + // + NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr); + } + } + + if (MinSpeed > DCTPtr->Timings.TargetSpeed) { + MinSpeed = DCTPtr->Timings.TargetSpeed; + } + } + } + + if (NBPtr->IsSupported[CheckMaxDramRate]) { + // Check maximum DRAM data rate that the processor is designed to support. + DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)]; + if (MinSpeed > DdrMaxRate) { + MinSpeed = DdrMaxRate; + } + } + + if (MinSpeed == DDR667_FREQUENCY) { + NBPtr->StartupSpeed = DDR667_FREQUENCY; + } + + // Sync all DCTs to the same speed + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if ((Mode[Dct] == TIMING_MODE_SPECIFIC) && (NBPtr->DCTPtr->Timings.TargetSpeed > MinSpeed)) { + PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader); + SetMemError (AGESA_ALERT, NBPtr->MCTPtr); + } + NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed; + NBPtr->MemNCapSpeedBatteryLife (NBPtr); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function waits for all DCTs to be ready + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNSyncDctsReadyNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->MCTPtr->DimmValid) { + MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE); + // Re-enable phy compensation engine after Dram init has completed + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); + } + // Wait 750 us for the phy compensation engine to reinitialize. + MemUWait10ns (75000, NBPtr->MemPtr); + + MemNSyncAddrMapToAllNodesNb (NBPtr); + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function create the HT memory map + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ + +BOOLEAN +MemNHtMemMapInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 BottomIo; + UINT32 HoleOffset; + UINT32 DctSelBaseAddr; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + MEM_PARAMETER_STRUCT *RefPtr; + DIE_STRUCT *MCTPtr; + + RefPtr = NBPtr->RefPtr; + MCTPtr = NBPtr->MCTPtr; + // + // Physical addresses in this function are right adjusted by 16 bits ([47:16]) + // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. + // + + // Enforce bottom of IO be be 128MB aligned + ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0)); + BottomIo = (RefPtr->BottomIo & 0xF8) << 8; + + if (!MCTPtr->GangedMode) { + DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; + } else { + DctSelBaseAddr = 0; + } + + if (MCTPtr->NodeMemSize) { + NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase; + NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1; + DctSelBaseAddr += NodeSysBase; + + if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) { + if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) { + // HW Dram Remap + MCTPtr->Status[SbHWHole] = TRUE; + RefPtr->GStatus[GsbHWHole] = TRUE; + MCTPtr->NodeHoleBase = BottomIo; + RefPtr->HoleBase = BottomIo; + + HoleOffset = _4GB_RJ16 - BottomIo; + + NodeSysLimit += HoleOffset; + + if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { + HoleOffset += DctSelBaseAddr; + } else { + if (DctSelBaseAddr >= BottomIo) { + DctSelBaseAddr += HoleOffset; + } + HoleOffset += NodeSysBase; + } + + MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); + MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); + MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); + + } else if (NodeSysBase == BottomIo) { + // SW Node Hoist + MCTPtr->Status[SbSWNodeHole] = TRUE; + RefPtr->GStatus[GsbSpIntRemapHole] = TRUE; + RefPtr->GStatus[GsbSoftHole] = TRUE; + + RefPtr->HoleBase = NodeSysBase; + DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase); + NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase); + NodeSysBase = _4GB_RJ16; + + } else if ((NodeSysBase < HT_REGION_BASE_RJ16) && (NodeSysLimit >= HT_REGION_BASE_RJ16)) { + if (!NBPtr->SharedPtr->UndoHoistingAbove1TB) { + // SW Hoisting above 1TB to avoid HT Reserved region + DctSelBaseAddr = _1TB_RJ16 + (DctSelBaseAddr - NodeSysBase); + NodeSysLimit = _1TB_RJ16 + (NodeSysLimit - NodeSysBase); + NodeSysBase = _1TB_RJ16; + + if (RefPtr->LimitMemoryToBelow1Tb) { + // Flag to undo 1TB hoisting after training + NBPtr->SharedPtr->UndoHoistingAbove1TB = TRUE; + } + } + + } else { + // No Remapping. Normal Contiguous mapping + } + } else { + // No Remapping. Normal Contiguous mapping + } + + if (NBPtr->IsSupported[Check1GAlign]) { + if (UserOptions.CfgNodeMem1GBAlign) { + NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit); + } + } + + MCTPtr->NodeSysBase = NodeSysBase; + MCTPtr->NodeSysLimit = NodeSysLimit; + RefPtr->SysLimit = NodeSysLimit; + RefPtr->Sub1THoleBase = (NodeSysLimit < HT_REGION_BASE_RJ16) ? (NodeSysLimit + 1) : RefPtr->Sub1THoleBase; + IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader); + + NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase; + NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00; + + MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16)); + MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16)); + + if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { + MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); + MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); + MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); + MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); + } + + NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0; + } + return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Program system DRAM map to this node + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNSyncAddrMapToAllNodesNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Node; + UINT32 NodeSysBase; + UINT32 NodeSysLimit; + UINT8 WeReMask; + UINT8 Index; + UINT32 Value; + PCI_ADDR PciAddr; + MEM_PARAMETER_STRUCT *RefPtr; + + RefPtr = NBPtr->RefPtr; + for (Node = 0; Node < NBPtr->NodeCount; Node++) { + NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase; + NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit; + if (NBPtr->SharedPtr->NodeMap[Node].IsValid) { + WeReMask = 3; + } else { + WeReMask = 0; + } + // Set the Dram base and set the WE and RE flags in the base. + MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask); + MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24); + // Set the Dram limit and set DstNode. + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node); + MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24); + + if (RefPtr->GStatus[GsbHWHole]) { + MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1); + MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8)); + } + } + + if (RefPtr->SysLimit >= _1TB_RJ16) { + // Initialize all indices of F1x114_x2 and F1x114_x3. + for (Index = 0; Index < 32; Index++) { + PciAddr = NBPtr->PciAddr; + PciAddr.Address.Function = 1; + + PciAddr.Address.Register = 0x110; + Value = 0x20000000 | Index; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + + PciAddr.Address.Register = 0x114; + Value = 0; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + + PciAddr.Address.Register = 0x110; + Value = 0x30000000 | Index; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + + PciAddr.Address.Register = 0x114; + Value = 0; + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function enables power down mode + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPowerDownCtlNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_PARAMETER_STRUCT *RefPtr; + UINT8 PowerDownMode; + + RefPtr = NBPtr->RefPtr; + + // we can't enable powerdown mode when doing WL + if (RefPtr->EnablePowerDown) { + MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); + PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; + IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader)); + if (PowerDownMode) { + MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets the Optimal Critical Gross Delay Difference between + * the delay parameters across all Dimms on each bytelane. Then takes the + * largest of all the bytelanes. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly1 - Type of first Gross Delay parameter + * @param[in] TrnDly2 - Type of second Gross Delay parameter + * + * @return The largest difference between the largest and smallest + * of the two Gross delay types within a single bytelane + */ +INT8 +MemNGetOptimalCGDDNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly1, + IN TRN_DLY_TYPE TrnDly2 + ) +{ + INT8 CGDD; + INT8 GDD; + UINT8 Dimm1; + UINT8 Dimm2; + UINT8 ByteLane; + UINT16 CsEnabled; + BOOLEAN CGDDInit; + BOOLEAN SameDelayType; + + CGDD = 0; + CGDDInit = FALSE; + SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2); + CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + + // If the two delay types compared are the same type, then no need to compare the same + // pair twice. Adjustments are made in the upper bound and lower bound of the loop to + // handle this. + for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) { + if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) { + for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) { + if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) { + for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) { + // check each byte lane delay pair + GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) - + (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5); + // If the 2 delay types to be compared are the same, then keep the absolute difference + if (SameDelayType && (GDD < 0)) { + GDD = (-GDD); + } + + // If CGDD is yet to be initialized, initialize it + // Otherwise, keep the largest difference so far + CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD); + if (!CGDDInit) { + CGDDInit = TRUE; + } + } + } + } + } + } + return CGDD; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function calculates the critical delay difference (CDD) + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDlyType1 - Type of first Gross Delay parameter + * @param[in] TrnDlyType2 - Type of second Gross Delay parameter + * @param[in] SameDimm - CDD of same DIMMs + * @param[in] DiffDimm - CDD of different DIMMs + * + * @return CDD term + */ +INT16 +MemNCalcCDDNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDlyType1, + IN TRN_DLY_TYPE TrnDlyType2, + IN BOOLEAN SameDimm, + IN BOOLEAN DiffDimm + ) +{ + INT16 CDD; + INT16 CDDtemp; + UINT16 TrnDly1; + UINT16 TrnDly2; + UINT8 i; + UINT8 j; + UINT8 ByteLane; + UINT16 CsEnabled; + BOOLEAN SameDlyType; + + SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2); + CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled; + CDD = -32000; + // If the two delay types compared are the same type, then no need to compare the same + // pair twice. Adjustments are made in the upper bound and lower bound of the loop to + // handle this. + for (i = 0; i < MAX_DIMMS_PER_CHANNEL && (CsEnabled & (UINT16) (3 << (i << 1))); i++) { + for (j = SameDlyType ? i : 0; (j < MAX_DIMMS_PER_CHANNEL) && (CsEnabled & (UINT16) (3 << (j << 1))); j++) { + if ((SameDimm && (i == j)) || (DiffDimm && (i != j))) { + for (ByteLane = 0; ByteLane < 8; ByteLane++) { + TrnDly1 = (UINT16) NBPtr->GetTrainDly (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i, ByteLane)); + TrnDly2 = (UINT16) NBPtr->GetTrainDly (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j, ByteLane)); + + CDDtemp = TrnDly1 - TrnDly2; + // If the 2 delay types to be compared are the same, then keep the absolute difference + if ((SameDlyType) && (CDDtemp < 0)) { + CDDtemp = (-CDDtemp); + } + + CDD = CDD < CDDtemp ? CDDtemp : CDD; + } + } + } + } + + return CDD; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the fixed MTRRs for common legacy ranges. + * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return TRUE - An Error value lower than AGESA_FATAL may have occurred + * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred + */ + +BOOLEAN +MemNCPUMemTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 Bottom32bIO; + UINT32 Bottom40bIO; + UINT32 Cache32bTOP; + S_UINT64 SMsr; + + MEM_DATA_STRUCT *MemPtr; + MEM_PARAMETER_STRUCT *RefPtr; + RefPtr = NBPtr->RefPtr; + MemPtr = NBPtr->MemPtr; + + // + //====================================================================== + // Set temporary top of memory from Node structure data. + // Adjust temp top of memory down to accommodate 32-bit IO space. + //====================================================================== + //Bottom40bIO=top of memory, right justified 16 bits (defines dram versus IO space type) + //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) + //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits + // + if (RefPtr->HoleBase != 0) { + Bottom32bIO = RefPtr->HoleBase; + } else if (RefPtr->BottomIo != 0) { + Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16); + } else { + Bottom32bIO = (UINT32)1 << (24 - 16); + } + + Cache32bTOP = RefPtr->SysLimit + 1; + if (Cache32bTOP < _4GB_RJ16) { + Bottom40bIO = 0; + if (Bottom32bIO >= Cache32bTOP) { + Bottom32bIO = Cache32bTOP; + } + } else { + Bottom40bIO = Cache32bTOP; + } + + Cache32bTOP = Bottom32bIO; + + + // + //====================================================================== + // Set default values for CPU registers + //====================================================================== + // + LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + SMsr.lo |= 0x1C0000; // turn on modification enable bit and + // mtrr enable bits + LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + SMsr.lo = SMsr.hi = 0x1E1E1E1E; + LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 0 - 512K = WB Mem + LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 512K - 640K = WB Mem + + // + //====================================================================== + // Set variable MTRR values + //====================================================================== + // + MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); + + RefPtr->Sub4GCacheTop = Cache32bTOP << 16; + + // + //====================================================================== + // Set TOP_MEM and TOM2 CPU registers + //====================================================================== + // + SMsr.hi = Bottom32bIO >> (32 - 16); + SMsr.lo = Bottom32bIO << 16; + LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); + IDS_HDT_CONSOLE ("TOP_MEM: %08lx0000\n", Bottom32bIO); + + if (Bottom40bIO) { + SMsr.hi = Bottom40bIO >> (32 - 16); + SMsr.lo = Bottom40bIO << 16; + } else { + SMsr.hi = 0; + SMsr.lo = 0; + } + LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + if (Bottom40bIO) { + IDS_HDT_CONSOLE ("TOP_MEM2: %08lx0000\n", Bottom40bIO); + IDS_HDT_CONSOLE ("Sub1THoleBase: %08lx0000\n", RefPtr->Sub1THoleBase); + // Enable TOM2 + SMsr.lo |= 0x00600000; + } else { + // Disable TOM2 + SMsr.lo &= ~0x00600000; + } + LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader); + + return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges. + * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNUMAMemTypingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 Bottom32bIO; + UINT32 Bottom32bUMA; + UINT32 Cache32bTOP; + UINT32 Value32; + UINT8 BitCount; + UINT8 i; + + MEM_PARAMETER_STRUCT *RefPtr; + RefPtr = NBPtr->RefPtr; + BitCount = 0; + // + //====================================================================== + // Adjust temp top of memory down to accommodate UMA memory start + //====================================================================== + // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type) + // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits + // + Bottom32bIO = RefPtr->Sub4GCacheTop >> 16; + Bottom32bUMA = RefPtr->UmaBase; + + if (Bottom32bUMA < Bottom32bIO) { + Cache32bTOP = RefPtr->Sub4GCacheTop = Bottom32bUMA; + // + //====================================================================== + //Set variable MTRR values + //====================================================================== + // + Value32 = Cache32bTOP; + //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing. + while (Value32 != 0) { + i = LibAmdBitScanForward (Value32); + Value32 &= ~ (1 << i); + BitCount++; + } + + if (BitCount > 5) { + NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE; + MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO); + } else { + MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6); + } + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Program MTRRs to describe given range as given cache type. Use MTRR pairs + * starting with the given MTRRphys Base address, and use as many as is + * required up to (excluding) MSR 020C, which is reserved for OS. + * + * "Limit" in the context of this procedure is not the numerically correct + * limit, but rather the Last address+1, for purposes of coding efficiency + * and readability. Size of a region is then Limit-Base. + * + * 1. Size of each range must be a power of two + * 2. Each range must be naturally aligned (Base is same as size) + * + * There are two code paths: the ascending path and descending path (analogous + * to bsf and bsr), where the next limit is a function of the next set bit in + * a forward or backward sequence of bits (as a function of the Limit). We + * start with the ascending path, to ensure that regions are naturally aligned, + * then we switch to the descending path to maximize MTRR usage efficiency. + * Base=0 is a special case where we start with the descending path. + * Correct Mask for region is 2comp(Size-1)-1, + * which is 2comp(Limit-Base-1)-1 * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Base - Base address[47:16] of specified range. + * @param[in] *LimitPtr - Limit address[47:16] of specified range. + * @param[in] MtrrAddr - address of var MTRR pair to start using. + * @param[in] MtrrType - Cache type for the range. + * + * @return TRUE - No failure occurred + * @return FALSE - Failure occurred because run out of variable-size MTRRs before completion. + */ + +BOOLEAN +STATIC +MemNSetMTRRrangeNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 Base, + IN OUT UINT32 *LimitPtr, + IN UINT32 MtrrAddr, + IN UINT8 MtrrType + ) +{ + S_UINT64 SMsr; + UINT32 CurBase; + UINT32 CurLimit; + UINT32 CurSize; + UINT32 CurAddr; + UINT32 Value32; + + CurBase = Base; + CurLimit = *LimitPtr; + CurAddr = MtrrAddr; + + while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) { + CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase); + CurLimit += CurBase; + if ((CurBase == 0) || (*LimitPtr < CurLimit)) { + CurLimit = *LimitPtr - CurBase; + CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit); + CurLimit += CurBase; + } + + // prog. MTRR with current region Base + SMsr.lo = (CurBase << 16) | (UINT32)MtrrType; + SMsr.hi = CurBase >> (32 - 16); + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + // prog. MTRR with current region Mask + CurAddr++; // other half of MSR pair + Value32 = CurSize - (UINT32)1; + Value32 = ~Value32; + SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; + SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + CurBase = CurLimit; + CurAddr++; // next MSR pair + } + + if (CurLimit < *LimitPtr) { + // Announce failure + *LimitPtr = CurLimit; + IDS_ERROR_TRAP; + } + + while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) { + SMsr.lo = SMsr.hi = 0; + LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + CurAddr++; + } + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Program one MTRR to describe Uma region as UC cache type if we detect running out of + * Mtrr circumstance. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] *BasePtr - Base address[47:24] of specified range. + * @param[in] *LimitPtr - Limit address[47:24] of specified range. + * + * @return TRUE - No fatal error occurs. + * @return FALSE - Fatal error occurs. + */ +BOOLEAN +MemNSetMTRRUmaRegionUCNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT32 *BasePtr, + IN OUT UINT32 *LimitPtr + ) +{ + S_UINT64 SMsr; + UINT32 Mtrr; + UINT32 Size; + UINT32 Value32; + + Size = *LimitPtr - *BasePtr; + Mtrr = 0x20A; //Reserved pair of MTRR for UMA region. + + // prog. MTRR with current region Base + SMsr.lo = *BasePtr << 16; + SMsr.hi = *BasePtr >> (32 - 16); + LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + // prog. MTRR with current region Mask + Mtrr++; // other half of MSR pair + Value32 = Size - (UINT32)1; + Value32 = ~Value32; + SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk; + SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID); + LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader); + + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * Report the Uma size that is going to be allocated. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return Uma size [31:0] = Addr [47:16] + */ +UINT32 +MemNGetUmaSizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return 0; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function allocates 16MB of memory for C6 storage when it is requested to be enabled + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ +VOID +MemNAllocateC6StorageNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT32 NodeSysLimit; + S_UINT64 SMsr; + + if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { + NodeSysLimit = NBPtr->MCTPtr->NodeSysLimit; + NodeSysLimit -= _16MB_RJ16; + + // Set Dram Limit + NBPtr->MCTPtr->NodeSysLimit -= NodeSysLimit; + NBPtr->RefPtr->SysLimit -= NodeSysLimit; + MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000)); + + // Set TOPMEM + NodeSysLimit += 1; + SMsr.hi = NodeSysLimit >> (32 - 16); + SMsr.lo = NodeSysLimit << 16; + if (NodeSysLimit < _4GB_RJ16) { + LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); + } else { + LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader)); + } + + // Set C6Base and C6DramLock + MemNSetBitFieldNb (NBPtr, BFC6Base, NodeSysLimit >> (24 - 16)); + MemNSetBitFieldNb (NBPtr, BFC6DramLock, 1); + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c new file mode 100755 index 0000000000..7c188e0e28 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnphy.c @@ -0,0 +1,1086 @@ +/** + * @file + * + * mnphy.c + * + * Common Northbridge Phy support + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 6789 $ @e \$Date: 2008-07-17 15:56:25 -0500 (Thu, 17 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "mport.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "mu.h" +#include "PlatformMemoryConfiguration.h" +#include "heapManager.h" +#include "merrhdl.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNPHY_FILECODE +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +#define UNUSED_CLK 4 + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ +/// Type of an entry for processing phy init compensation for client NB +typedef struct { + BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided + BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified + BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified + UINT16 ExtraValue; ///< Extra value needed to be written to bit field + CONST UINT16 (*TxPrePN)[3][5]; ///< Pointer to slew rate table +} PHY_COMP_INIT_CLIENTNB; + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets a delay value a PCI register during training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * + * @return Value read + */ + +UINT32 +MemNGetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar + ) +{ + return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets a delay value a PCI register during training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * @param[in] Field - Value to be programmed + * + */ + +VOID +MemNSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ) +{ + NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes prototypical Phy fence training function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPhyFenceTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + NBPtr->MemPPhyFenceTrainingNb (NBPtr); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes prototypical Phy fence training function. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPhyFenceTrainingClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 FenceThresholdTxDll; + UINT8 FenceThresholdRxDll; + UINT8 FenceThresholdTxPad; + UINT16 Fence2Data; + + // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b. + // 2. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training]. + // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll]. + MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2); + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence); + IDS_HDT_CONSOLE ("\t\tFenceThresholdTxDll\n"); + MemNTrainPhyFenceNb (NBPtr); + FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); + + // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b. + MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000); + + // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b. + // 6. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training]. + // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll]. + MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1); + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence); + IDS_HDT_CONSOLE ("\n\t\tFenceThresholdRxDll\n"); + MemNTrainPhyFenceNb (NBPtr); + FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); + + // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b. + MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000); + + // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b. + // 10. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training]. + // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad]. + MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3); + MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence); + IDS_HDT_CONSOLE ("\n\t\tFenceThresholdTxPad\n"); + MemNTrainPhyFenceNb (NBPtr); + FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence); + + // Program Fence2 threshold for Clk, Cmd, and Addr + if (FenceThresholdTxPad < 16) { + MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10); + MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10); + MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10); + } else { + MemNSetBitFieldNb (NBPtr, BFClkFence2, 0); + MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0); + MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0); + } + + // Program Fence2 threshold for data + Fence2Data = 0; + if (FenceThresholdTxPad < 16) { + Fence2Data |= FenceThresholdTxPad | 0x10; + } + if (FenceThresholdRxDll < 16) { + Fence2Data |= (FenceThresholdRxDll | 0x10) << 10; + } + if (FenceThresholdTxDll < 16) { + Fence2Data |= (FenceThresholdTxDll | 0x10) << 5; + } + MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); + + // Reprogram F2x9C_04. + MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function executes Phy fence training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNTrainPhyFenceNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Byte; + UINT16 Avg; + UINT8 PREvalue; + + if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) { + return; + } + + // 1. BIOS first programs a seed value to the phase recovery + // engine registers. + // + IDS_HDT_CONSOLE ("\t\tSeeds: "); + for (Byte = 0; Byte < 9; Byte++) { + // This includes ECC as byte 8 + MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19); + IDS_HDT_CONSOLE ("%02x ", 19); + } + + IDS_HDT_CONSOLE ("\n\t\tPhyFenceTrEn = 1"); + // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1. + MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1); + + if (!NBPtr->IsSupported[ClientNbFence]) { + // 3. Wait 200 MEMCLKs. + MemUWait10ns (500, NBPtr->MemPtr); + } else { + // 3. Wait 2000 MEMCLKs. + MemUWait10ns (5000, NBPtr->MemPtr); + } + + // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0. + MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0); + + // 5. BIOS reads the phase recovery engine registers + // F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52. + // 6. Calculate the average value of the fine delay and subtract 8. + // + Avg = 0; + IDS_HDT_CONSOLE ("\n\t\t PRE: "); + for (Byte = 0; Byte < 9; Byte++) { + // This includes ECC as byte 8 + PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte))); + Avg = Avg + ((UINT16) PREvalue); + IDS_HDT_CONSOLE ("%02x ", PREvalue); + } + Avg = ((Avg + 8) / 9); // round up + + Avg -= 8; + NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg); + + IDS_HDT_CONSOLE ("\n\t\tFence: %02x\n", Avg); + + // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence]. + MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg); + + // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control + // Register delays for both channels. This forces the phy to recompute + // the fence. + // + MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl)); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2}; + CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2}; + CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2}; + CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3}; + UINT8 i; + UINT8 j; + UINT8 CurrDct; + UINT8 CurrChannel; + BOOLEAN MarginImprv; + MarginImprv = FALSE; + CurrDct = NBPtr->Dct; + CurrChannel = NBPtr->Channel; + if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { + if (NBPtr->MCTPtr->GangedMode == FALSE) { + for (i = 0; i < NBPtr->DctCount; i++) { + MemNSwitchDCTNb (NBPtr, i); + for (j = 0; j < NBPtr->ChannelCount; j++) { + NBPtr->SwitchChannel (NBPtr, j); + if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) { + MarginImprv = TRUE; + } + } + } + MemNSwitchDCTNb (NBPtr, CurrDct); + NBPtr->SwitchChannel (NBPtr, CurrChannel); + } + } + + // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1 + // 2. BIOS waits 5 us for the disabling of the compensation engine to complete. + // DisAutoComp will be cleared after Dram init has completed + // + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + MemUWait10ns (500, NBPtr->MemPtr); + MemNSwitchDCTNb (NBPtr, CurrDct); + + // 3. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the + // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal]. + // + // 4. For each normalized driver strength code read from + // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding + // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal, + // D3Cmp2PCal]. + // + j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren); + i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren); + + MemNSwitchDCTNb (NBPtr, 0); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]); + + if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) { + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]); + } + if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) { + ASSERT (i <= 3); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]); + MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]); + } + MemNSwitchDCTNb (NBPtr, CurrDct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This is a general purpose function that executes before DRAM training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNBeforeDQSTrainingNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + UINT8 Dct; + UINT8 ChipSel; + UINT32 TestAddrRJ16; + UINT32 RealAddr; + + MemTBeginTraining (NBPtr->TechPtr); + + for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { + MemNSwitchDCTNb (NBPtr, Dct); + if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { + for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { + if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) { + + RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr); + + MemUDummyCLRead (RealAddr); + + MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000); + MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns + MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000); + MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us + MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr); + break; + } + } + } + if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) { + if (!NBPtr->MCTPtr->Status[SbEccDimms]) { + MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010); + } + if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) { + MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080); + } + } + } + + MemTEndTraining (NBPtr->TechPtr); +} + +/*-----------------------------------------------------------------------------*/ +/** + * + * Returns the parameters for a requested delay value to be used in training + * The correct Min, Max and Mask are determined based on the type of Delay, + * and the frequency + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - Type of delay + * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct + * + */ + +VOID +MemNGetTrainDlyParmsNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN TRN_DLY_TYPE TrnDly, + IN OUT TRN_DLY_PARMS *Parms + ) +{ + Parms->Min = 0; + + if (TrnDly == AccessWrDatDly) { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } else if (TrnDly == AccessRdDqsDly) { + if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) { + Parms->Max = 0x3E; + Parms->Mask = 0x03E; + } else { + Parms->Max = 0x1F; + Parms->Mask = 0x01F; + } + } +} + +/*---------------------------------------------------------------------------- + * LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets or set DQS timing during training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * @param[in] Field - Value to be programmed + * @param[in] IsSet - Indicates if the function will set or get + * + * @return value read, if the function is used as a "get" + */ + +UINT32 +MemNcmnGetSetTrainDlyNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ) +{ + UINT16 Index; + UINT16 Offset; + UINT32 Value; + UINT32 Address; + UINT8 Dimm; + UINT8 Rank; + UINT8 Byte; + UINT8 Nibble; + + Dimm = DRBN_DIMM (DrbnVar); + Rank = DRBN_RANK (DrbnVar); + Byte = DRBN_BYTE (DrbnVar); + Nibble = DRBN_NBBL (DrbnVar); + + ASSERT (Dimm < 4); + ASSERT (Byte <= ECC_DLY); + + switch (TrnDly) { + case AccessRcvEnDly: + Index = 0x10; + break; + case AccessWrDqsDly: + Index = 0x30; + break; + case AccessWrDatDly: + Index = 0x01; + break; + case AccessRdDqsDly: + Index = 0x05; + break; + case AccessPhRecDly: + Index = 0x50; + break; + default: + Index = 0; + IDS_ERROR_TRAP; + } + + switch (TrnDly) { + case AccessRcvEnDly: + case AccessWrDqsDly: + Index += (Dimm * 3); + if (Byte & 0x04) { + // if byte 4,5,6,7 + Index += 0x10; + } + if (Byte & 0x02) { + // if byte 2,3,6,7 + Index++; + } + if (Byte > 7) { + Index += 2; + } + Offset = 16 * (Byte % 2); + Index |= (Rank << 8); + Index |= (Nibble << 9); + break; + + case AccessRdDqsDly: + case AccessWrDatDly: + + if (NBPtr->IsSupported[DimmBasedOnSpeed]) { + if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) { + // if DDR speed is below 800, use DIMM 0 delays for all DIMMs. + Dimm = 0; + } + } + + Index += (Dimm * 0x100); + if (Nibble) { + if (Rank) { + Index += 0xA0; + } else { + Index += 0x70; + } + } else if (Rank) { + Index += 0x60; + } + // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need + // to run AccessPhRecDly sequence. + case AccessPhRecDly: + Index += (Byte / 4); + Offset = 8 * (Byte % 4); + break; + default: + Offset = 0; + IDS_ERROR_TRAP; + } + + Address = Index; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + + if (IsSet) { + if (TrnDly == AccessPhRecDly) { + Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; + } + + Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset))); + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE); + + if (TrnDly == AccessPhRecDly) { + NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; + } + } else { + Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF); + } + + return Value; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function gets or set DQS timing during training. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] IsSet - Indicates if the function will set or get + * @param[in] TrnDly - type of delay to be set + * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed + * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding + * @param[in] Field - Value to be programmed + * + * @return value read, if the function is used as a "get" + */ +UINT32 +MemNcmnGetSetTrainDlyClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 IsSet, + IN TRN_DLY_TYPE TrnDly, + IN DRBN DrbnVar, + IN UINT16 Field + ) +{ + UINT16 Index; + UINT16 Offset; + UINT32 Value; + UINT32 Address; + UINT8 Dimm; + UINT8 Byte; + + Dimm = DRBN_DIMM (DrbnVar); + Byte = DRBN_BYTE (DrbnVar); + + if ((Dimm > 1) || (Byte > 7)) { + // LN only support DIMM 0 and 8 byte lanes. + return 0; + } + + switch (TrnDly) { + case AccessRcvEnDly: + Index = 0x10; + break; + case AccessWrDqsDly: + Index = 0x30; + break; + case AccessWrDatDly: + Index = 0x01; + break; + case AccessRdDqsDly: + Index = 0x05; + break; + case AccessPhRecDly: + Index = 0x50; + break; + default: + Index = 0; + IDS_ERROR_TRAP; + } + + switch (TrnDly) { + case AccessRcvEnDly: + case AccessWrDqsDly: + Index += (Dimm * 3); + if (Byte & 0x04) { + // if byte 4,5,6,7 + Index += 0x10; + } + if (Byte & 0x02) { + // if byte 2,3,6,7 + Index++; + } + Offset = 16 * (Byte % 2); + break; + + case AccessRdDqsDly: + case AccessWrDatDly: + Index += (Dimm * 0x100); + // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need + // to run AccessPhRecDly sequence. + case AccessPhRecDly: + Index += (Byte / 4); + Offset = 8 * (Byte % 4); + break; + default: + Offset = 0; + IDS_ERROR_TRAP; + } + + Address = Index; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg); + + if (IsSet) { + if (TrnDly == AccessPhRecDly) { + Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03]; + } + + Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset))); + MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); + Address |= DCT_ACCESS_WRITE; + MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); + + if (TrnDly == AccessPhRecDly) { + NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value; + } + } else { + Value = (Value >> Offset) & 0xFF; + } + + return Value; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initializes the training pattern. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return AGESA_STATUS - Result + * AGESA_SUCCESS - Training pattern is ready to use + * AGESA_ERROR - Unable to initialize the pattern. + */ + +AGESA_STATUS +MemNTrainingPatternInitNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + ALLOCATE_HEAP_PARAMS AllocHeapParams; + POS_TRN_PATTERN_TYPE TrainPattern; + AGESA_STATUS Status; + + TechPtr = NBPtr->TechPtr; + // + // Determine pattern to be used + // + if (NBPtr->PosTrnPattern == POS_PATTERN_256B) { + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + TrainPattern = TestPatternJD256B; + TechPtr->PatternLength = 64; + } else { + TrainPattern = TestPatternJD256A; + TechPtr->PatternLength = 32; + } + } else { + // + // 72 bit pattern will be used if PosTrnPattern is not specified + // + if (NBPtr->MCTPtr->Status[Sb128bitmode]) { + TrainPattern = TestPatternJD1B; + TechPtr->PatternLength = 18; + } else { + TrainPattern = TestPatternJD1A; + TechPtr->PatternLength = 9; + } + } + // + // Allocate training buffer + // + AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16; + AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + if (Status != AGESA_SUCCESS) { + return Status; + } + TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr; + AlignPointerTo16Byte (&TechPtr->PatternBufPtr); + TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64); + + // Prepare training pattern + MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64); + + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finalizes the training pattern. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Index - Index of Write Data Delay Value + * @param[in,out] *Value - Write Data Delay Value + * @return BOOLEAN - TRUE - Use the value returned. + * FALSE - No more values in table. + */ + +BOOLEAN +MemNGetApproximateWriteDatDelayNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Index, + IN OUT UINT8 *Value + ) +{ + CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F}; + if (Index < GET_SIZE_OF (WriteDatDelayValue)) { + *Value = WriteDatDelayValue[Index]; + return TRUE; + } + return FALSE; +} + + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function finalizes the training pattern. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return AGESA_STATUS - Result + * AGESA_SUCCESS - Training pattern has been finalized. + * AGESA_ERROR - Unable to initialize the pattern. + */ + +AGESA_STATUS +MemNTrainingPatternFinalizeNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + AGESA_STATUS Status; + // + // Deallocate training buffer + // + Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader); + ASSERT (Status == AGESA_SUCCESS); + return Status; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the number of chipselects per channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNCSPerChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return MAX_CS_PER_CHANNEL; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the number of Chipselects controlled by each set + * of Delay registers under current conditions. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNCSPerDelayNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + return MAX_CS_PER_DELAY; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function returns the minimum data eye width in 32nds of a UI for + * the type of data eye(Rd/Wr) that is being trained. This value will + * be the minimum number of consecutive delays that yield valid data. + * Uses TechPtr->Direction to determine read or write. + * + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + * @return + */ + +UINT8 +MemNMinDataEyeWidthNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + if (NBPtr->TechPtr->Direction == DQS_READ_DIR) { + return MIN_RD_DATAEYE_WIDTH_NB; + } else { + return MIN_WR_DATAEYE_WIDTH_NB; + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function programs the phy registers according to the desired phy VDDIO voltage level + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNPhyVoltageLevelClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + BIT_FIELD_NAME BitField; + UINT16 Value; + UINT16 Mask; + + Mask = 0xFFE7; + Value = (UINT16) NBPtr->RefPtr->DDR3Voltage << 3; + + /// @todo: Need to verify if the following logic can work on real hardware or not + for (BitField = BFDataRxVioLvl; BitField <= BFCmpVioLvl; BitField++) { + if (BitField == BFCmpVioLvl) { + Mask = 0x3FFF; + Value <<= (14 - 3); + } + MemNBrdcstSetNb (NBPtr, BitField, ((MemNGetBitFieldNb (NBPtr, BitField) & Mask)) | Value); + } +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function adjusts Avg PRE value of Phy fence training according to specific CPU family. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in,out] *Value16 - Pointer to the value that we want to adjust + * + */ +VOID +MemNPFenceAdjustClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN OUT UINT16 *Value16 + ) +{ + *Value16 += 2; //for LN, the Avg PRE value is subtracted by 6 only. +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function initializes the DDR phy compensation logic + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +VOID +MemNInitPhyCompClientNb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + // Slew rate table array [x][y][z] + // array[0]: slew rate for VDDIO 1.5V + // array[1]: slew rate for VDDIO 1.35V + // array[x][y]: slew rate for a certain frequency + // array[x][y][0]: frequency mask for current entry + CONST STATIC UINT16 TxPrePNDataDqs[2][3][5] = { + {{ (UINT16) DDR800, 0xFF6, 0xDAD, 0xDAD, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}} + }; + CONST STATIC UINT16 TxPrePNCmdAddr[2][3][5] = { + {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, + { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB}, + { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}}, + {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492}, + { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB}, + { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}} + }; + CONST STATIC UINT16 TxPrePNClock[2][3][5] = { + {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}, + {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924}, + { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD}, + { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}} + }; + + CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = { + // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V. + // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}. + // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}. + {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs}, + {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs}, + {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs}, + // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V. + // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}. + // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}. + {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr}, + {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr}, + {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, + {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr}, + {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr}, + // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V. + // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}. + {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock} + }; + + BIT_FIELD_NAME CurrentBitField; + UINT16 SpeedMask; + CONST UINT16 (*TxPrePNArray)[5]; + UINT8 Voltage; + UINT8 i; + UINT8 j; + UINT8 k; + + // 1. Program D18F2x[1,0]9C_x0000_0008[DisAutoComp] = 1. + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1); + // 2. Program D18F2x[1,0]9C_x0D0F_E003[DisalbePredriverCal]=1 + MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, (1 << 13)); + + SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66); + Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage; + + for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) { + i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField); + TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage]; + for (k = 0; k < 3; k ++) { + if ((TxPrePNArray[k][0] & SpeedMask) != 0) { + for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) { + MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1])); + } + break; + } + } + ASSERT (k < 3); + } + + // 6. Program D18F2x[1,0]9C_x0000_0008[DisAutoComp] = 0. + MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0); +}
\ No newline at end of file diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c new file mode 100755 index 0000000000..39b54d00fe --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mnreg.c @@ -0,0 +1,396 @@ +/** + * @file + * + * mnreg.c + * + * Common Northbridge register access functions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB/) + * @e \$Revision: 11190 $ @e \$Date: 2009-03-02 10:39:45 -0600 (Mon, 02 Mar 2009) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "AdvancedApi.h" +#include "amdlib.h" +#include "Ids.h" +#include "mm.h" +#include "mn.h" +#include "merrhdl.h" +#include "Filecode.h" +#include "GeneralServices.h" +#define FILECODE PROC_MEM_NB_MNREG_FILECODE + + +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the current DCT to work on. + * Should be called before accessing a certain DCT + * All data structures will be updated to point to the current DCT + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct - ID of the target DCT + * + */ + +VOID +MemNSwitchDCTNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct + ) +{ + ASSERT (NBPtr->DctCount > 1); + NBPtr->Dct = Dct ? 1 : 0; + NBPtr->MCTPtr->Dct = NBPtr->Dct; + NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]); + NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]); + NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]); + + MemNSwitchChannelNb (NBPtr, NBPtr->Channel); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets the current channel to work on. + * Should be called before accessing a certain channel + * All data structures will be updated to point to the current channel + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Channel - ID of the target channel + * + */ + +VOID +MemNSwitchChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Channel + ) +{ + NBPtr->Channel = Channel ? 1 : 0; + NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function gets a bit field from PCI register + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Field name + * + * @return Bit field value + */ + +UINT32 +MemNGetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName + ) +{ + UINT32 Value; + + ASSERT (FieldName < BFEndOfList); + Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0); + return Value; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function sets a bit field from PCI register + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Field name + * @param[in] Field - Value to be stored in PCT register + * + */ + +VOID +MemNSetBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + ASSERT (FieldName < BFEndOfList); + NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore + * DCTs that are disabled. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be checked + * + * @return TRUE - All enabled DCTs have the expected value on the bitfield. + * @return FALSE - Not all enabled DCTs have the expected value on the bitfield. + * + * ---------------------------------------------------------------------------- + */ +BOOLEAN +MemNBrdcstCheckNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + UINT8 Dct; + UINT8 CurrentDCT; + Dct = NBPtr->Dct; + for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { + MemNSwitchDCTNb (NBPtr, CurrentDCT); + if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { + if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) { + MemNSwitchDCTNb (NBPtr, Dct); + return FALSE; + } + } + } + MemNSwitchDCTNb (NBPtr, Dct); + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Set bitfields of all enabled DCTs on a die to a value. Ignore + * DCTs that are disabled. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be set + * + * ---------------------------------------------------------------------------- + */ +VOID +MemNBrdcstSetNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field + ) +{ + UINT8 Dct; + UINT8 CurrentDCT; + Dct = NBPtr->Dct; + for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) { + MemNSwitchDCTNb (NBPtr, CurrentDCT); + if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) { + MemNSetBitFieldNb (NBPtr, FieldName, Field); + } + } + MemNSwitchDCTNb (NBPtr, Dct); +} + +/*-----------------------------------------------------------------------------*/ +/** + * This function calculates the memory channel index relative to the + * socket, taking the Die number, the Dct, and the channel. + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] Dct + * @param[in] Channel + * + */ +UINT8 +MemNGetSocketRelativeChannelNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN UINT8 Dct, + IN UINT8 Channel + ) +{ + return ((NBPtr->MCTPtr->DieId *NBPtr->DctCount) + Dct); +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * Poll a bitfield. If the bitfield does not get set to the target value within + * specified microseconds, it times out. + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * @param[in] FieldName - Bit Field name + * @param[in] Field - Value to be set + * @param[in] MicroSecond - Number of microsecond to wait + * @param[in] IfBroadCast - Need to broadcast to both DCT or not + * + * ---------------------------------------------------------------------------- + */ +VOID +MemNPollBitFieldNb ( + IN OUT MEM_NB_BLOCK *NBPtr, + IN BIT_FIELD_NAME FieldName, + IN UINT32 Field, + IN UINT32 MicroSecond, + IN BOOLEAN IfBroadCast + ) +{ + UINT8 ExcludeDCT; + UINT16 ExcludeChipSelMask; + UINT32 EventInfo; + UINT64 InitTSC; + UINT64 CurrentTSC; + UINT64 TimeOut; + AGESA_STATUS EventClass; + MEM_DATA_STRUCT *MemPtr; + DIE_STRUCT *MCTPtr; + BOOLEAN TimeoutEn; + + MemPtr = NBPtr->MemPtr; + MCTPtr = NBPtr->MCTPtr; + ExcludeDCT = EXCLUDE_ALL_DCT; + ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL; + TimeoutEn = TRUE; + IDS_TIMEOUT_CTL (&TimeoutEn); + + CurrentTSC = 0; + LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader); + TimeOut = InitTSC + ((UINT64) MicroSecond * 1600); + + while ((CurrentTSC < TimeOut) || !TimeoutEn) { + if (IfBroadCast) { + if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) { + break; + } + } else { + if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) { + break; + } + } + LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader); + } + + if ((CurrentTSC >= TimeOut) && TimeoutEn) { + // Default event class + // If different event class is needed in one entry, override it. + EventClass = AGESA_ERROR; + switch (FieldName) { + case BFDramEnabled: + EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT; + break; + case BFDctAccessDone: + EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFSendCtrlWord: + EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFPrefDramTrainMode: + EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFEnterSelfRef: + EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT; + break; + case BFFreqChgInProg: + EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFExitSelfRef: + EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT; + break; + case BFSendMrsCmd: + EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFSendZQCmd: + EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFDctExtraAccessDone: + EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + case BFMemClrBusy: + EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT; + break; + case BFMemCleared: + EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT; + break; + case BFFlushWr: + EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT; + ExcludeDCT = NBPtr->Dct; + break; + default: + EventClass = 0; + EventInfo = 0; + IDS_ERROR_TRAP; + } + + PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader); + SetMemError (EventClass, MCTPtr); + MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader); + } +} + + diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c new file mode 100755 index 0000000000..85e476c6da --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain2.c @@ -0,0 +1,127 @@ +/** + * @file + * + * mntrain2.c + * + * Common Northbridge function for training flow for DDR2 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemNDQSTiming2Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + NBPtr = TechPtr->NBPtr; + if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr); + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + //Execute Technology specific training features + if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { + if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); + if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) { + if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); + if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); + } + } + } + } + } + MemTMarkTrainFail (TechPtr); + } +} diff --git a/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c new file mode 100755 index 0000000000..b3b2075561 --- /dev/null +++ b/src/vendorcode/amd/agesa/f10/Proc/Mem/NB/mntrain3.c @@ -0,0 +1,193 @@ +/** + * @file + * + * mntrain3.c + * + * Common Northbridge function for training flow for DDR3 + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: (Mem/NB) + * @e \$Revision: 7081 $ @e \$Date: 2008-07-31 01:47:27 -0500 (Thu, 31 Jul 2008) $ + * + **/ +/***************************************************************************** +* +* Copyright (c) 2011, Advanced Micro Devices, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* * Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* * Neither the name of Advanced Micro Devices, Inc. nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +* *************************************************************************** +* +*/ + +/* + *---------------------------------------------------------------------------- + * MODULES USED + * + *---------------------------------------------------------------------------- + */ + + + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "OptionMemory.h" +#include "mm.h" +#include "mn.h" +#include "mt.h" +#include "Filecode.h" +#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE +/* features */ +#include "mftds.h" +/*---------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * TYPEDEFS AND STRUCTURES + * + *---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * PROTOTYPES OF LOCAL FUNCTIONS + * + *---------------------------------------------------------------------------- + */ + +BOOLEAN +STATIC +MemTHwWlPart2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ); +/*---------------------------------------------------------------------------- + * EXPORTED FUNCTIONS + * + *---------------------------------------------------------------------------- + */ +extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3; + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function initiates DQS training + * + * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK + * + */ + +BOOLEAN +MemNDQSTiming3Nb ( + IN OUT MEM_NB_BLOCK *NBPtr + ) +{ + MEM_TECH_BLOCK *TechPtr; + + TechPtr = NBPtr->TechPtr; + if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { + AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { + // Right now we do not have anything to do if the callout is implemented + } + AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); + //Execute Technology specific training features + if (memTechTrainingFeatDDR3.EnterHardwareTraining (TechPtr)) { + if (memTechTrainingFeatDDR3.SwWLTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); + if (memTechTrainingFeatDDR3.HwBasedWLTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); + if (memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); + // If target speed is higher than start-up speed, do frequency change and second pass of WL + if (MemTHwWlPart2 (TechPtr)) { + if (memTechTrainingFeatDDR3.TrainExitHwTrn (TechPtr)) { + IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CNTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); + if (memTechTrainingFeatDDR3.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { + if (memTechTrainingFeatDDR3.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); + if (memTechTrainingFeatDDR3.NonOptimizedSRdWrPosTraining (TechPtr)) { + if (memTechTrainingFeatDDR3.OptimizedSRdWrPosTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); + do { + if (memTechTrainingFeatDDR3.MaxRdLatencyTraining (TechPtr)) { + MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); + } + } while (NBPtr->ChangeNbFrequency (NBPtr)); + } + } + } + } + } + } + } + } + } + } + MemTMarkTrainFail (TechPtr); + } + return TRUE; +} + +/* -----------------------------------------------------------------------------*/ +/** + * + * This function executes HW WL at multiple speeds + * + * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK + * @return TRUE - No errors occurred + * FALSE - errors occurred + */ + +BOOLEAN +STATIC +MemTHwWlPart2 ( + IN OUT MEM_TECH_BLOCK *TechPtr + ) +{ + BOOLEAN retVal; + retVal = TRUE; + while (TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) { + TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; + if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { + if (!memTechTrainingFeatDDR3.HwBasedWLTrainingPart2 (TechPtr)) { + retVal = FALSE; + break; + } + MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); + if (!memTechTrainingFeatDDR3.HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { + retVal = FALSE; + break; + } + MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); + } else { + retVal = FALSE; + break; + } + } + return retVal; +} |