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authorefdesign98 <efdesign98@gmail.com>2011-08-04 12:09:17 -0600
committerPatrick Georgi <patrick@georgi-clan.de>2011-08-06 18:06:18 +0200
commit84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch)
tree57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f12/Proc
parent0df0e14fb5b613e76ff022359c55d5df5633b40f (diff)
downloadcoreboot-84cbce2364cf3e40f24ba37b2f72a711a2e50f58.tar.xz
Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/131 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12/Proc')
-rwxr-xr-xsrc/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h27
-rwxr-xr-xsrc/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c18
-rwxr-xr-xsrc/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c2
3 files changed, 17 insertions, 30 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
index fd8073837e..db4e7ad7ce 100755
--- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Family/cpuFamRegisters.h
@@ -80,24 +80,18 @@
// Family 12h equates
#define AMD_FAMILY_12_LN 0x0000000000000020ull
-#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
-#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
+#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
+#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
// Family 14h equates
#define AMD_FAMILY_14_ON 0x0000000000000040ull
-#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
-#define AMD_FAMILY_14_KR 0x0000000000000080ull
-#define AMD_FAMILY_KR (AMD_FAMILY_14_KR)
-#define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR)
+#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
+#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
// Family 15h equates
#define AMD_FAMILY_15_OR 0x0000000000000100ull
#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
-#define AMD_FAMILY_15_TN 0x0000000000000200ull
-#define AMD_FAMILY_TN (AMD_FAMILY_15_TN)
-#define AMD_FAMILY_15_KM 0x0000000000000400ull
-#define AMD_FAMILY_KM (AMD_FAMILY_15_KM)
-#define AMD_FAMILY_15 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | AMD_FAMILY_15_KM)
+#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
// Family 16h equates
#define AMD_FAMILY_16 0x0000000000000800ull
@@ -203,11 +197,7 @@
#define AMD_F14_ON_Cx (AMD_F14_ON_C0)
#define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx)
-#define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1)
-#define AMD_F14_KR_Bx AMD_F14_KR_B0
-#define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx)
-
-#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL | AMD_F14_UNKNOWN)
+#define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_UNKNOWN)
// Family 15h CPU_LOGICAL_ID.Revision equates
// -------------------------------------
@@ -227,10 +217,7 @@
#define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0)
#define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx)
-#define AMD_F15_TN_Ax (AMD_F15_TN_A0)
-#define AMD_F15_TN_ALL (AMD_F15_TN_Ax)
-
-#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_TN_ALL | AMD_F15_UNKNOWN)
+#define AMD_F15_ALL (AMD_F15_OR_ALL | AMD_F15_UNKNOWN)
// Family 16h CPU_LOGICAL_ID.Revision equates
// TBD
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
index 8563d6e538..333f46c4eb 100755
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
@@ -192,7 +192,7 @@ PcieAlibBuildAcpiTable (
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
// AmlObjName = '10DA';
- AmlObjName = 0x31304441;
+ AmlObjName = Int32FromChar ('1', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -211,7 +211,7 @@ PcieAlibBuildAcpiTable (
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// AmlObjName = '30DA';
- AmlObjName = 0x33304441;
+ AmlObjName = Int32FromChar ('3', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -226,7 +226,7 @@ PcieAlibBuildAcpiTable (
Gen1VidIndex = GnbLocateLowestVidIndex (StdHeader);
BootUpVidIndex = GnbLocateHighestVidIndex (StdHeader);
// AmlObjName = '40DA';
- AmlObjName = 0x34304441;
+ AmlObjName = Int32FromChar ('4', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -235,7 +235,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '50DA';
- AmlObjName = 0x35304441;
+ AmlObjName = Int32FromChar ('5', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -244,7 +244,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '01DA';
- AmlObjName = 0x30314441;
+ AmlObjName = Int32FromChar ('0', '1', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -255,7 +255,7 @@ PcieAlibBuildAcpiTable (
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
// AmlObjName = '20DA';
- AmlObjName = 0x32304441;
+ AmlObjName = Int32FromChar ('2', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -264,7 +264,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '60DA';
- AmlObjName = 0x36304441;
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -278,7 +278,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '60DA';
- AmlObjName = 0x36304441;
+ AmlObjName = Int32FromChar ('6', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
@@ -292,7 +292,7 @@ PcieAlibBuildAcpiTable (
AgesaStatus = AGESA_FATAL;
}
// AmlObjName = '70DA';
- AmlObjName = 0x37304441;
+ AmlObjName = Int32FromChar ('7', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
index 630d688c5a..80095063c9 100755
--- a/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
+++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c
@@ -110,7 +110,7 @@ PcieFmAlibBuildAcpiTable (
AgesaStatus = AGESA_SUCCESS;
AltVddNbSupport = TRUE;
// AmlObjName = 'A0DA';
- AmlObjName = 0x41304441;
+ AmlObjName = Int32FromChar ('A', '0', 'D', 'A');
AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {