AGESA vendorcode: Remove AGESA_ENTRY_INIT_RECOVERY

Deprecated and not used in our builds.

Change-Id: I01773bb62b1599d18ad51d6f444abec46faec942
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 2 insertions, 699 deletions

diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h
index b161cd3be7..6074aee3a3 100644
--- a/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h
@@ -107,31 +107,6 @@
   #define TRANSFER_AP_CORE_NUMBER     TRUE
 #endif
 
-#if AGESA_ENTRY_INIT_RECOVERY == TRUE
-  #undef ID_POSITION_INITIAL_APICID
-  #define ID_POSITION_INITIAL_APICID  TRUE
-  #undef USES_REGISTER_TABLES
-  #define USES_REGISTER_TABLES        TRUE
-  #undef BASE_FAMILY_PCI
-  #define BASE_FAMILY_PCI             TRUE
-  #undef MODEL_SPECIFIC_PCI
-  #define MODEL_SPECIFIC_PCI          TRUE
-  #undef BASE_FAMILY_MSR
-  #define BASE_FAMILY_MSR             TRUE
-  #undef MODEL_SPECIFIC_MSR
-  #define MODEL_SPECIFIC_MSR          TRUE
-  #undef GET_CACHE_INFO
-  #define GET_CACHE_INFO              TRUE
-  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
-  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
-  #undef IS_NB_PSTATE_ENABLED
-  #define IS_NB_PSTATE_ENABLED        TRUE
-  #undef GET_PATCHES
-  #define GET_PATCHES                 TRUE
-  #undef GET_PATCHES_EQUIVALENCE_TABLE
-  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
-#endif
-
 #if AGESA_ENTRY_INIT_EARLY == TRUE
   #undef TRANSITION_PSTATE
   #define TRANSITION_PSTATE           TRUE
diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h
index 63cb0ff3cb..ca0f79d712 100644
--- a/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h
@@ -336,8 +336,6 @@ extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
       #define F12_LN_UCODE_0E
       #define F12_LN_UCODE_0F
 
-      // If a patch is required for recovery mode to function properly, add a
-      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
       #if AGESA_ENTRY_INIT_EARLY == TRUE
         extern  CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000f;
         #undef F12_LN_UCODE_0F
@@ -374,7 +372,7 @@ extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
         #else
           (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
         #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
           F12NbPstateInitEarlySampleHook
         #else
           (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
@@ -388,7 +386,7 @@ extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
         #else
           (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
         #endif
-        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+        #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
           (PF_F12_ES_NB_PSTATE_INIT) CommonVoid
         #else
           (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h
index 4778de358d..d1c6c740f2 100644
--- a/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h
@@ -77,13 +77,6 @@ CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVE
       { (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
       { (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
     };
-  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-    #include <mru.h>
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
-      { (UINTN) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
-      { (UINTN) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
-    };
   #else
     CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
       { (UINTN) CommonReturnFalse, "DefRet()"},
diff --git a/src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h
deleted file mode 100644
index 6d2a445b53..0000000000
--- a/src/vendorcode/amd/agesa/f12/Config/OptionMemoryRecoveryInstall.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 49896 $   @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
-#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
-
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-
-  #define MEM_REC_NB_SUPPORT_OR
-
-  #if (OPTION_MEMCTLR_DR == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
-    #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
-  #else
-    #define MEM_REC_NB_SUPPORT_DR
-  #endif
-  #if (OPTION_MEMCTLR_RB == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
-    #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
-  #else
-    #define MEM_REC_NB_SUPPORT_RB
-  #endif
-  #if (OPTION_MEMCTLR_DA == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
-    #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
-  #else
-    #define MEM_REC_NB_SUPPORT_DA
-  #endif
-  #if (OPTION_MEMCTLR_NI == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
-    #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
-  #else
-    #define MEM_REC_NB_SUPPORT_NI
-  #endif
-  #if (OPTION_MEMCTLR_PH == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
-    #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
-  #else
-    #define MEM_REC_NB_SUPPORT_PH
-  #endif
-  #if (OPTION_MEMCTLR_HY == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
-    #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
-  #else
-    #define MEM_REC_NB_SUPPORT_HY
-  #endif
-  #if (OPTION_MEMCTLR_C32 == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
-    #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
-  #else
-    #define MEM_REC_NB_SUPPORT_C32
-  #endif
-  #if (OPTION_MEMCTLR_LN == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
-    #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
-  #else
-    #define MEM_REC_NB_SUPPORT_LN
-  #endif
-  #if (OPTION_MEMCTLR_ON == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
-    #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
-  #else
-    #define MEM_REC_NB_SUPPORT_ON
-  #endif
-
-  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
-    MEM_REC_NB_SUPPORT_DR
-    MEM_REC_NB_SUPPORT_RB
-    MEM_REC_NB_SUPPORT_DA
-    MEM_REC_NB_SUPPORT_PH
-    MEM_REC_NB_SUPPORT_HY
-    MEM_REC_NB_SUPPORT_C32
-    MEM_REC_NB_SUPPORT_LN
-    MEM_REC_NB_SUPPORT_OR
-    MEM_REC_NB_SUPPORT_ON
-    MEM_REC_NB_SUPPORT_NI
-    NULL
-  };
-
-  #define MEM_REC_TECH_CONSTRUCTOR_DDR2
-  #if (OPTION_DDR3 == TRUE)
-    extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
-    #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
-  #else
-    #define MEM_REC_TECH_CONSTRUCTOR_DDR3
-  #endif
-
-  MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
-    MEM_REC_TECH_CONSTRUCTOR_DDR3
-    MEM_REC_TECH_CONSTRUCTOR_DDR2
-    NULL
-  };
-
-  #if OPTION_MEMCTLR_DR
-    #define PSC_REC_DR_UDIMM_DDR2
-    #define PSC_REC_DR_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_DR_RDIMM_DDR2
-    #define PSC_REC_DR_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
-    #define PSC_REC_DR_SODIMM_DDR2
-    #define PSC_REC_DR_SODIMM_DDR3    MemRecNGetPsCfgSODIMM3Nb,
-  #endif
-  #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
-    #define PSC_REC_DA_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_DA_SODIMM_DDR2
-    #define PSC_REC_DA_SODIMM_DDR3    MemRecNGetPsCfgSODIMM3Nb,
-  #endif
-  #if OPTION_MEMCTLR_HY
-    #define PSC_REC_HY_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_HY_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
-  #endif
-  #if OPTION_MEMCTLR_C32
-    #define PSC_REC_C32_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
-    #define PSC_REC_C32_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
-  #endif
-  #if OPTION_MEMCTLR_OR
-    #define PSC_REC_OR_UDIMM_DDR3    //MemRecNGetPsCfgUDIMM3OR,
-    #define PSC_REC_OR_RDIMM_DDR3    //MemRecNGetPsCfgRDIMM3OR,
-  #endif
-
-  #ifndef PSC_REC_DR_UDIMM_DDR2
-    #define PSC_REC_DR_UDIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DR_UDIMM_DDR3
-    #define PSC_REC_DR_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DR_RDIMM_DDR2
-    #define PSC_REC_DR_RDIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DR_RDIMM_DDR3
-    #define PSC_REC_DR_RDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DR_SODIMM_DDR2
-    #define PSC_REC_DR_SODIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DR_SODIMM_DDR3
-    #define PSC_REC_DR_SODIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DA_UDIMM_DDR3
-    #define PSC_REC_DA_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_DA_SODIMM_DDR2
-    #define PSC_REC_DA_SODIMM_DDR2
-  #endif
-  #ifndef PSC_REC_DA_SODIMM_DDR3
-    #define PSC_REC_DA_SODIMM_DDR3
-  #endif
-  #ifndef PSC_REC_HY_UDIMM_DDR3
-    #define PSC_REC_HY_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_HY_RDIMM_DDR3
-    #define PSC_REC_HY_RDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_C32_UDIMM_DDR3
-    #define PSC_REC_C32_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_C32_RDIMM_DDR3
-    #define PSC_REC_C32_RDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_OR_UDIMM_DDR3
-    #define PSC_REC_OR_UDIMM_DDR3
-  #endif
-  #ifndef PSC_REC_OR_RDIMM_DDR3
-    #define PSC_REC_OR_RDIMM_DDR3
-  #endif
-
-  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
-    PSC_REC_DR_UDIMM_DDR2
-    PSC_REC_DR_RDIMM_DDR2
-    PSC_REC_DR_SODIMM_DDR2
-    PSC_REC_DR_UDIMM_DDR3
-    PSC_REC_DR_RDIMM_DDR3
-    PSC_REC_DR_SODIMM_DDR3
-    PSC_REC_DA_SODIMM_DDR2
-    PSC_REC_DA_UDIMM_DDR3
-    PSC_REC_DA_SODIMM_DDR3
-    PSC_REC_HY_UDIMM_DDR3
-    PSC_REC_HY_RDIMM_DDR3
-    PSC_REC_C32_UDIMM_DDR3
-    PSC_REC_C32_RDIMM_DDR3
-    PSC_REC_OR_UDIMM_DDR3
-    PSC_REC_OR_RDIMM_DDR3
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_PSC_REC_FLOW_BLOCK_END NULL
-  #define PSC_REC_TBL_END NULL
-  #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
-  #if OPTION_MEMCTLR_OR
-    #if OPTION_UDIMMS
-      #if OPTION_AM3_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &RecDramTermTblEntUAM3,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &RecOdtPat1DTblEntUAM3,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3  &RecOdtPat2DTblEntUAM3,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &RecOdtPat3DTblEntUAM3,
-        extern PSC_TBL_ENTRY RecSAOTblEntUAM3;
-        #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3  &RecSAOTblEntUAM3,
-      #endif
-      #if OPTION_C32_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32  &RecDramTermTblEntUC32,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &RecOdtPat1DTblEntUC32,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32  &RecOdtPat2DTblEntUC32,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &RecOdtPat3DTblEntUC32,
-        extern PSC_TBL_ENTRY RecSAOTblEntUC32;
-        #define PSC_REC_TBL_OR_UDIMM3_SAO_C32  &RecSAOTblEntUC32,
-      #endif
-      #if OPTION_G34_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34  &RecDramTermTblEntUG34,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &RecOdtPat1DTblEntUG34,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34  &RecOdtPat2DTblEntUG34,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &RecOdtPat3DTblEntUG34,
-        extern PSC_TBL_ENTRY RecSAOTblEntUG34;
-        #define PSC_REC_TBL_OR_UDIMM3_SAO_G34  &RecSAOTblEntUG34,
-      #endif
-    #endif
-    #if OPTION_RDIMMS
-      #if OPTION_C32_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32  &RecDramTermTblEntRC32,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &RecOdtPat1DTblEntRC32,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32  &RecOdtPat2DTblEntRC32,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &RecOdtPat3DTblEntRC32,
-        extern PSC_TBL_ENTRY RecSAOTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_SAO_C32  &RecSAOTblEntRC32,
-        extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32;
-        #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32  &RecRC2IBTTblEntRC32,
-    #endif
-      #if OPTION_G34_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY RecDramTermTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34  &RecDramTermTblEntRG34,
-        extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &RecOdtPat1DTblEntRG34,
-        extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34  &RecOdtPat2DTblEntRG34,
-        extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &RecOdtPat3DTblEntRG34,
-        extern PSC_TBL_ENTRY RecSAOTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_SAO_G34  &RecSAOTblEntRG34,
-        extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34;
-        #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34  &RecRC2IBTTblEntRG34,
-      #endif
-    #endif
-    //#if OPTION_SODIMMS
-    //#endif
-    //#if OPTION_LRDIMMS
-    //#endif
-    extern PSC_TBL_ENTRY RecMR0WrTblEntry;
-    #define PSC_REC_TBL_OR_MR0_WR  &RecMR0WrTblEntry,
-    extern PSC_TBL_ENTRY RecMR0CLTblEntry;
-    #define PSC_REC_TBL_OR_MR0_CL  &RecMR0CLTblEntry,
-
-    #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
-      #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
-      #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-      #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3
-      #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32
-      #define PSC_REC_TBL_OR_UDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34
-      #define PSC_REC_TBL_OR_UDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
-      #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
-      #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-      #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_SAO_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32
-      #define PSC_REC_TBL_OR_RDIMM3_SAO_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34
-      #define PSC_REC_TBL_OR_RDIMM3_SAO_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
-      #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
-      #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-      #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
-      #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
-    #endif
-    #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
-      #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
-    #endif
-
-    PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = {
-      PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
-      PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
-      PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
-      PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
-      PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
-      PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = {
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
-      PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
-      PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = {
-      PSC_REC_TBL_OR_UDIMM3_SAO_AM3
-      PSC_REC_TBL_OR_UDIMM3_SAO_C32
-      PSC_REC_TBL_OR_UDIMM3_SAO_G34
-      PSC_REC_TBL_OR_RDIMM3_SAO_AM3
-      PSC_REC_TBL_OR_RDIMM3_SAO_C32
-      PSC_REC_TBL_OR_RDIMM3_SAO_G34
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = {
-      PSC_REC_TBL_OR_MR0_WR
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = {
-      PSC_REC_TBL_OR_MR0_CL
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = {
-      PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
-      PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
-      PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
-      PSC_REC_TBL_END
-    };
-
-    MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = {
-      NULL,
-      (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR,
-      (PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL
-    };
-
-    extern MEM_PSC_FLOW MemPRecGetRttNomWr;
-    #define PSC_REC_FLOW_OR_DRAM_TERM   MemPRecGetRttNomWr
-    extern MEM_PSC_FLOW MemPRecGetODTPattern;
-    #define PSC_REC_FLOW_OR_ODT_PATTERN   MemPRecGetODTPattern
-    extern MEM_PSC_FLOW MemPRecGetSAO;
-    #define PSC_REC_FLOW_OR_SAO   MemPRecGetSAO
-    extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
-    #define PSC_REC_FLOW_OR_MR0_WRCL   MemPRecGetMR0WrCL
-    #if OPTION_RDIMMS
-      extern MEM_PSC_FLOW MemPRecGetRC2IBT;
-      #define PSC_REC_FLOW_OR_RC2_IBT    MemPRecGetRC2IBT
-    #endif
-    //#if OPTION_LRDIMMS
-    extern MEM_PSC_FLOW MemPRecGetLRIBT;
-    #define PSC_REC_FLOW_OR_LR_IBT   MemPRecGetLRIBT
-    extern MEM_PSC_FLOW MemPRecGetLRNPR;
-    #define PSC_REC_FLOW_OR_LR_NPR   MemPRecGetLRNPR
-    extern MEM_PSC_FLOW MemPRecGetLRNLR;
-    #define PSC_REC_FLOW_OR_LR_NLR  MemPRecGetLRNLR
-    //#endif
-    #ifndef PSC_REC_FLOW_OR_DRAM_TERM
-      #define PSC_REC_FLOW_OR_DRAM_TERM   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_ODT_PATTERN
-      #define PSC_REC_FLOW_OR_ODT_PATTERN   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_SAO
-      #define PSC_REC_FLOW_OR_SAO   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_MR0_WRCL
-      #define PSC_REC_FLOW_OR_MR0_WRCL   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_RC2_IBT
-      #define PSC_REC_FLOW_OR_RC2_IBT   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_LR_IBT
-      #define PSC_REC_FLOW_OR_LR_IBT   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_LR_NPR
-      #define PSC_REC_FLOW_OR_LR_NPR   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    #ifndef PSC_REC_FLOW_OR_LR_NLR
-      #define PSC_REC_FLOW_OR_LR_NLR   MEM_REC_PSC_FLOW_DEFTRUE
-    #endif
-    MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = {
-      &memRecPSCTblBlockOr,
-      NULL,
-      PSC_REC_FLOW_OR_DRAM_TERM,
-      PSC_REC_FLOW_OR_ODT_PATTERN,
-      PSC_REC_FLOW_OR_SAO,
-      PSC_REC_FLOW_OR_MR0_WRCL,
-      PSC_REC_FLOW_OR_RC2_IBT,
-      NULL,
-      PSC_REC_FLOW_OR_LR_IBT,
-      PSC_REC_FLOW_OR_LR_NPR,
-      PSC_REC_FLOW_OR_LR_NLR
-    };
-    #define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR,
-  #else
-    #define MEM_PSC_REC_FLOW_BLOCK_OR
-  #endif
-
-  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
-    MEM_PSC_REC_FLOW_BLOCK_OR
-    MEM_PSC_REC_FLOW_BLOCK_END
-  };
-
-#else
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {    // Types of technology installed
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT NORTHBRIDGE SUPPORT LIST
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_NB_SUPPORT* MemRecNBInstalled[] = {
-    NULL
-  };
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
-    NULL
-  };
-  /*----------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
-    NULL
-  };
-#endif
-#endif  // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h
index 1fe116a6c7..2153fe7c5e 100644
--- a/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h
@@ -2216,8 +2216,6 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
 #include  "OptionHtInstall.h"
 #include  "OptionMemory.h"
 #include  "OptionMemoryInstall.h"
-#include  "OptionMemoryRecovery.h"
-#include  "OptionMemoryRecoveryInstall.h"
 #include  "OptionCpuFeaturesInstall.h"
 #include  "OptionDmi.h"
 #include  "OptionDmiInstall.h"
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecovery.h
deleted file mode 100644
index 713e73d65f..0000000000
--- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryRecovery.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Memory option API.
- *
- * Contains structures and values used to control the Memory option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  OPTION
- * @e \$Revision: 63425 $   @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
- *
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- ******************************************************************************
- */
-
-#ifndef _OPTION_MEMORY_RECOVERY_H_
-#define _OPTION_MEMORY_RECOVERY_H_
-
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-
-typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  );
-
-typedef VOID MEM_REC_TECH_CONSTRUCTOR (
-  IN OUT   MEM_TECH_BLOCK *TechPtr,
-  IN OUT   MEM_NB_BLOCK   *NBPtr
-  );
-
-#endif  // _OPTION_MEMORY_H_