diff options
| author | efdesign98 <efdesign98@gmail.com> | 2011-08-04 12:09:17 -0600 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-08-06 18:06:18 +0200 |
| commit | 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch) | |
| tree | 57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h | |
| parent | 0df0e14fb5b613e76ff022359c55d5df5633b40f (diff) | |
| download | coreboot-84cbce2364cf3e40f24ba37b2f72a711a2e50f58.tar.xz | |
Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus. It also fixes (again) a ton of warnings, although
not all of them are gone. The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.
Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h index fe41a396a6..11b0cf7664 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h @@ -9,7 +9,7 @@ * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB - * @e \$Revision: 38902 $ @e \$Date: 2010-10-02 02:01:38 +0800 (Sat, 02 Oct 2010) $ + * @e \$Revision: 47437 $ @e \$Date: 2011-02-20 15:32:39 -0700 (Sun, 20 Feb 2011) $ * */ /* @@ -52,13 +52,14 @@ #define PP_FUSE_MAX_NUM_DPM_STATE 5 #define PP_FUSE_MAX_NUM_SW_STATE 6 + /// Fuse definition structure typedef struct { UINT8 PPlayTableRev; ///< PP table revision UINT8 SclkDpmValid[6]; ///< Valid DPM states - UINT8 SclkDpmDid[5]; ///< Sclk DPM DID - UINT8 SclkDpmVid[5]; ///< Sclk DPM VID - UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac + UINT8 SclkDpmDid[6]; ///< Sclk DPM DID + UINT8 SclkDpmVid[6]; ///< Sclk DPM VID + UINT8 SclkDpmCac[6]; ///< Sclk DPM Cac UINT8 PolicyFlags[6]; ///< State policy flags UINT8 PolicyLabel[6]; ///< State policy label UINT8 VclkDid[4]; ///< VCLK DID @@ -72,6 +73,11 @@ typedef struct { UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID UINT8 MainPllId; ///< Main PLL Id from fuses UINT8 WrCkDid; ///< WRCK SMU clock Divisor + UINT8 GpuBoostCap; ///< GPU boost cap + UINT16 SclkDpmTdpLimit[6]; ///< Sclk DPM TDP limit + UINT16 SclkDpmTdpLimitPG; ///< TDP limit PG + UINT32 SclkDpmBoostMargin; ///< Boost margin + UINT32 SclkDpmThrottleMargin; ///< Throttle margin } PP_FUSE_ARRAY; #pragma pack (pop) |