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| author | efdesign98 <efdesign98@gmail.com> | 2011-08-04 12:09:17 -0600 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-08-06 18:06:18 +0200 |
| commit | 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch) | |
| tree | 57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h | |
| parent | 0df0e14fb5b613e76ff022359c55d5df5633b40f (diff) | |
| download | coreboot-84cbce2364cf3e40f24ba37b2f72a711a2e50f58.tar.xz | |
Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus. It also fixes (again) a ton of warnings, although
not all of them are gone. The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.
Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h index a54b7e8939..a7c7da5564 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h @@ -104,6 +104,14 @@ NbSmuIndirectPoll ( ); VOID +NbSmuIndirectWriteEx ( + IN UINT8 Address, + IN ACCESS_WIDTH Width, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID NbSmuIndirectWrite ( IN UINT8 Address, IN ACCESS_WIDTH Width, @@ -112,6 +120,13 @@ NbSmuIndirectWrite ( ); VOID +NbSmuIndirectWriteS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +VOID NbSmuRcuRegisterWrite ( IN UINT16 Address, IN UINT32 *Value, @@ -170,6 +185,14 @@ NbSmuReadEfuse ( IN AMD_CONFIG_PARAMS *StdHeader ); +UINT32 +NbSmuReadEfuseField ( + IN UINT8 Chain, + IN UINT16 Offset, + IN UINT8 Length, + IN AMD_CONFIG_PARAMS *StdHeader + ); + VOID NbSmuFirmwareDownload ( IN SMU_FIRMWARE_HEADER *Firmware, |