Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14 rev C0 cpus. It also fixes (again) a ton of warnings, although not all of them are gone. The warning fixes affect code in the Family 12 tree as well, so there are some small changes therein. This code has been tested on a Persimmon and passes Abuild. This is the first (and largest) of a number of commits to complete the upgrade. Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/131 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
author: efdesign98 <efdesign98@gmail.com> 2011-08-04 12:09:17 -0600
committer: Patrick Georgi <patrick@georgi-clan.de> 2011-08-06 18:06:18 +0200
commit: 84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch)
tree: 57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/Mem
parent: 0df0e14fb5b613e76ff022359c55d5df5633b40f (diff)
download: coreboot-84cbce2364cf3e40f24ba37b2f72a711a2e50f58.tar.xz
44 files changed, 342 insertions, 48 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
index 812aa963e4..0f22e1b71e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c
@@ -86,6 +86,11 @@ MemFDctInterleaveBanks (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
 
+BOOLEAN
+MemFUndoInterleaveBanks (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 VOID
 STATIC
 CsIntSwap (
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
index b4d17194ea..bcbee65444 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Main)
- * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $
  *
  **/
 /*
@@ -84,6 +84,16 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 
+BOOLEAN
+MemFDMISupport3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+BOOLEAN
+MemFDMISupport2 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
@@ -505,7 +515,7 @@ MemFDMISupport2 (
 
           // Form Factor (offset 0Eh)
           FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
-          if ((FormFactor & 0x20) == 4) {
+          if ((FormFactor & 0x04) == 4) {
             DmiTable[DimmIndex].FormFactor = 0x0D;       // SO-DIMM
           } else {
             DmiTable[DimmIndex].FormFactor = 0x09;       // RDIMM or UDIMM
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
index 4ea95e98cd..4344e25663 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c
@@ -75,11 +75,18 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 
+BOOLEAN
+MemFCheckECC (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+/*
 UINT32
 STATIC
 MemFGetScrubAddr (
   IN OUT   MEM_NB_BLOCK *NBPtr
   );
+*/
 
 VOID
 STATIC
@@ -296,6 +303,7 @@ InitECCOverriedeStruct (
  *     @return          Scrubber Address
  */
 
+/*
 UINT32
 STATIC
 MemFGetScrubAddr (
@@ -318,4 +326,4 @@ MemFGetScrubAddr (
   }
   return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
 }
-
+*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
index cdf3568259..75590ede75 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c
@@ -75,6 +75,11 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 BOOLEAN
+MemFInitEMP (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN
 STATIC
 IsPowerOfTwo (
   IN       UINT32 TestNumber
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
index c6e85ec3f0..bcd069b7ca 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Feat/EXCLUDIMM)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -82,6 +82,11 @@ RDATA_GROUP (G2_PEI)
  *----------------------------------------------------------------------------
  */
 
+BOOLEAN
+MemFRASExcludeDIMM (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
@@ -163,6 +168,8 @@ MemFRASExcludeDIMM (
       IsCSIntlvEnabled = TRUE;
     }
 
+    Flag = TRUE;
+    NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
     for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
       NBPtr->SwitchDCT (NBPtr, Dct);
       if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
@@ -179,6 +186,8 @@ MemFRASExcludeDIMM (
         }
       }
     }
+    Flag = FALSE;
+    NBPtr->FamilySpecificHook[BfAfExcludeDimm] (NBPtr, &Flag);
 
     // Re-enable chip select interleaving when remapping is done.
     if (IsCSIntlvEnabled) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
index 9576f8014b..f96841b051 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Feat)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
+ * @e \$Revision: 46495 $ @e \$Date: 2011-02-03 14:10:56 -0700 (Thu, 03 Feb 2011) $
  *
  **/
 /*
@@ -160,6 +160,7 @@ AmdIdentifyDimm (
     // NB block has already been constructed by main block.
     // No need to construct it here.
     NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
+    mmData.NBPtr = NBPtr;
   } else {
     AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
     AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
index b51db06a5b..df2071f5bc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c
@@ -703,7 +703,7 @@ MemFS3Wait10ns (
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
 
   ASSERT (Count <= 1000000);
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader);
 
   LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c
index 378ca7a254..2c0cb25141 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c
@@ -88,6 +88,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
  *----------------------------------------------------------------------------
  */
 
+AGESA_STATUS
+MemMFlowON (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c
index 0d80a4ec4d..a280d40656 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c
@@ -53,6 +53,7 @@
  */
 
 #include "AGESA.h"
+#include "AdvancedApi.h"
 #include "Filecode.h"
 #include "mm.h"
 CODE_GROUP (G1_PEICC)
@@ -77,6 +78,11 @@ RDATA_GROUP (G1_PEICC)
  *----------------------------------------------------------------------------
  */
 
+AGESA_STATUS
+MemMFlowDef (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c
index ba3346bce6..7b6edc4691 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c
@@ -54,6 +54,7 @@
 
 #include "AGESA.h"
 #include "amdlib.h"
+#include "AdvancedApi.h"
 #include "mu.h"
 #include "OptionMemory.h"
 #include "Ids.h"
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c
index 9105b3a57d..1e3067395d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c
@@ -74,6 +74,11 @@ RDATA_GROUP (G1_PEICC)
 *-----------------------------------------------------------------------------
 */
 
+BOOLEAN
+MemMEcc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c
index 9eb20bba72..0b62c00991 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c
@@ -73,6 +73,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
 *-----------------------------------------------------------------------------
 */
 
+BOOLEAN
+MemMRASExcludeDIMM (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
@@ -184,7 +189,7 @@ MemMRASExcludeDIMM (
 
     LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
     // Only when TOM is set can CpuMemTyping be re-run
-    if (SMsr.hi == SMsr.lo == 0) {
+    if ((SMsr.hi == 0) && (SMsr.lo == 0)) {
       if (RefPtr->SysLimit != 0) {
         NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
       }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c
index 1fe217118a..d00f92fe3f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c
@@ -58,6 +58,7 @@
 #include "OptionMemory.h"
 #include "mm.h"
 #include "mn.h"
+#include "mmlvddr3.h"
 #include "Filecode.h"
 CODE_GROUP (G1_PEICC)
 RDATA_GROUP (G1_PEICC)
@@ -71,6 +72,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
 *-----------------------------------------------------------------------------
 */
 
+BOOLEAN
+MemMLvDdr3 (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c
index 55eb5a6d80..a8f504b25d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemClr.c
@@ -69,6 +69,10 @@ RDATA_GROUP (G2_PEI)
 *-----------------------------------------------------------------------------
 */
 
+BOOLEAN
+MemMMctMemClr (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
 
 /* -----------------------------------------------------------------------------*/
 /**
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
index 3038436e41..4a1ad29da6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
@@ -75,6 +75,11 @@ RDATA_GROUP (G1_PEICC)
  *
  *----------------------------------------------------------------------------
  */
+VOID
+MemMContextSave (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 BOOLEAN
 STATIC
 MemMRestoreDqsTimings (
@@ -97,6 +102,12 @@ MemMCreateS3NbBlock (
   IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr,
      OUT   S3_MEM_NB_BLOCK **S3NBPtr
   );
+
+BOOLEAN
+MemMContextRestore (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /*-----------------------------------------------------------------------------
 *                                EXPORTED FUNCTIONS
 *
@@ -125,7 +136,7 @@ MemMContextSave (
   DEVICE_BLOCK_HEADER *DeviceList;
   AMD_CONFIG_PARAMS *StdHeader;
   UINT32 BufferSize;
-  UINT64 BufferOffset;
+  VOID *BufferOffset;
   MEM_NB_BLOCK  *NBArray;
   S3_MEM_NB_BLOCK *S3NBPtr;
   DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
@@ -160,30 +171,31 @@ MemMContextSave (
           DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
 
           // Copy device list on the stack to the heap.
-          BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+//          BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
+          BufferOffset = AllocHeapParams.BufferPtr + sizeof (DEVICE_BLOCK_HEADER);
           for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
             for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
               // Copy PCI device descriptor to the heap if it exists.
               if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
-                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
+                LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
                 DeviceList->NumDevices ++;
                 BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
               }
               // Copy conditional PCI device descriptor to the heap if it exists.
               if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
-                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
+                LibAmdMemCopy (BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
                 DeviceList->NumDevices ++;
                 BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
               }
               // Copy MSR device descriptor to the heap if it exists.
               if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
-                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
+                LibAmdMemCopy ( BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
                 DeviceList->NumDevices ++;
                 BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
               }
               // Copy conditional MSR device descriptor to the heap if it exists.
               if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
-                LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
+                LibAmdMemCopy ( BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
                 DeviceList->NumDevices ++;
                 BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
               }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c
index 066c38ffe3..62d2fda48a 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c
@@ -71,6 +71,11 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
 *-----------------------------------------------------------------------------
 */
 
+BOOLEAN
+MemMInterleaveNodes (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c
index f88cc150f6..b19f60e789 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c
@@ -69,6 +69,11 @@ RDATA_GROUP (G2_PEI)
 *-----------------------------------------------------------------------------
 */
 
+BOOLEAN
+MemMOnlineSpare (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c
index f9de5c5ad8..216c0925d5 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmParallelTraining.c
@@ -82,6 +82,12 @@ extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
 *
 *-----------------------------------------------------------------------------
 */
+
+BOOLEAN
+MemMParallelTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c
index f1a6f612cd..b0376a4819 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmStandardTraining.c
@@ -72,6 +72,10 @@ RDATA_GROUP (G1_PEICC)
 *
 *-----------------------------------------------------------------------------
 */
+BOOLEAN
+MemMStandardTraining (
+  IN OUT   MEM_MAIN_DATA_BLOCK *mmPtr
+  );
 
 /* -----------------------------------------------------------------------------*/
 /**
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
index 0f03a05e2f..755586a08e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c
@@ -82,6 +82,12 @@ RDATA_GROUP (G1_PEICC)
  *
  *----------------------------------------------------------------------------
  */
+
+BOOLEAN
+MemMUmaAlloc (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
 /*-----------------------------------------------------------------------------
 *                                EXPORTED FUNCTIONS
 *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c
index d3c0541327..97fab2e1fe 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c
@@ -60,6 +60,7 @@
 #include "GeneralServices.h"
 #include "cpuFamilyTranslation.h"
 #include "OptionMemory.h"
+#include "AdvancedApi.h"
 #include "mm.h"
 #include "mn.h"
 #include "mt.h"
@@ -174,7 +175,7 @@ AmdMemAuto (
   //----------------------------------------------------------------------------
   // Get TSC rate, which will be used later in Wait10ns routine
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader);
 
   //----------------------------------------------------------------------------
@@ -375,7 +376,7 @@ MemSPDDataProcess (
       }
     }
   } else {
-    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, NULL, NULL, NULL, NULL, &MemPtr->StdHeader);
+    PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, 0, 0, 0, 0, &MemPtr->StdHeader);
     //
     // Assert here if unable to allocate heap for SPDs
     //
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c
index edd39ddb2a..3c83a066bd 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c
@@ -59,6 +59,7 @@
  
 #include "AGESA.h"
 #include "amdlib.h"
+#include "mu.h"
 #include "Filecode.h" 
 
 /*----------------------------------------------------------------------------------------
@@ -76,6 +77,7 @@
  *----------------------------------------------------------------------------------------
  */
  
+/*
 VOID 
 MemUWriteCachelines (
   IN       UINT32 Address,
@@ -110,7 +112,8 @@ VOID
 AlignPointerTo16Byte (
   IN OUT   UINT8 **BufferPtrPtr
   );
- 
+*/
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
index 2ddd305e44..961ea1df00 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
@@ -646,7 +646,7 @@ GetVarMtrrHiMsk (
   CPU_SPECIFIC_SERVICES *FamilySpecificServices;
   CACHE_INFO *CacheInfoPtr;
 
-  GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
-  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader);
+  GetCpuServicesFromLogicalId (LogicalIdPtr, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &TempNotCare, StdHeader);
   return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
 }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
index d683da8e5d..b3f0a8ee14 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c
@@ -217,7 +217,7 @@ MemConstructRemoteNBBlockC32 (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
index 143baac643..2f149a212b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c
@@ -219,7 +219,7 @@ MemConstructRemoteNBBlockDA (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
index d1e241c3b5..f56d02ab3d 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c
@@ -405,7 +405,7 @@ MemNCapSpeedBatteryLifeDA (
   FamilySpecificServices = NULL;
   DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
   ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
-  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
+  GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, (const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
   if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
     NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100;  // Calculate the Nb P1 frequency (NbFreq / 2)
     for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
index 33ec0c77c1..17a8427d22 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c
@@ -219,7 +219,7 @@ MemConstructRemoteNBBlockDR (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
index 651ba7cf56..8a444362a8 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c
@@ -217,7 +217,7 @@ MemConstructRemoteNBBlockHY (
   //----------------------------------------------------------------------------
   // Get TSC rate of the this AP
   //----------------------------------------------------------------------------
-  GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+  GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
   FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
 
   return TRUE;
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
index dcbbf96969..4af0dfba8c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -120,6 +120,14 @@ MemNS3GetConPCIMaskON (
   IN OUT   MEM_NB_BLOCK *NBPtr,
   IN OUT   DESCRIPTOR_GROUP *DescriptPtr
   );
+
+BOOLEAN
+MemS3ResumeConstructNBBlockON (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
 /*----------------------------------------------------------------------------
  *                          DEFINITIONS AND MACROS
  *
@@ -176,6 +184,11 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = {
   {{1, 1, 1}, DCT0,   BFAddrRxVioLvl, 0x00000018},
   // 4. Frequency Change
   {{4, 3, 1}, DCT0,   BFPllLockTime, 0},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimDByte, 0x7000},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimClk, 0x7000},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimCsOdt, 0x7000},
+  {{1, 2, 1}, DCT0,   BFDllCSRBisaTrimAByte2, 0x7000},
+  {{1, 2, 1}, DCT0,   BFReduceLoop, 0x6000},
   {{0, 0, 0}, FUNC_2, 0x94,  0xFFD1CC1F},
   //    NB Pstate Related Register for Pstate 0
   {{0, 0, 0}, FUNC_2, 0x78,  0xFFF63FCF},
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
index c0855b8f43..a3afd55e20 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -149,7 +149,7 @@ MemNAutoConfigON (
     MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
   }
 
-  MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1);
+  MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, (((MemNGetBitFieldNb (NBPtr, BFLowPowerDefault)) == 1) && (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife)) ? 0 : 1);
 
   MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE);
 
@@ -459,7 +459,7 @@ MemNChangeNbFrequencyWrapON (
   if (Status) {
     // When NB frequency change succeeds, TSC rate may have changed.
     // We need to update TSC rate
-    GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
+    GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
     FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
   }
   return Status;
@@ -487,4 +487,33 @@ MemNSetDqsODTON (
     MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20);
   }
   return TRUE;
-}
-\ No newline at end of file
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function sets reduceloop and trim value for DDR-1333 for C0
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  OptParam   - Optional parameter
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNBeforeMemClkFreqValON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  )
+{
+  if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) != 0)) {
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimDByte, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimClk, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimCsOdt, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFDllCSRBisaTrimAByte2, 0x7000);
+    MemNBrdcstSetNb (NBPtr, BFReduceLoop, 0x6000);
+  }
+  return TRUE;
+}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
index b7efd35cbb..f6f170d607 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c
@@ -60,6 +60,7 @@
 #include "OptionMemory.h"
 #include "mm.h"
 #include "mn.h"
+#include "mnon.h"
 #include "mt.h"
 #include "Filecode.h"
 #include "GeneralServices.h"
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
index 9e4060af3f..718e52b608 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c
@@ -85,6 +85,13 @@
  */
 
 
+BOOLEAN
+MemNIdentifyDimmConstructorON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
index 768d0d7106..17a20198cf 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -251,7 +251,7 @@ MemConstructNBBlockON (
   NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
   NBPtr->TechBlockSwitch = MemNTechBlockSwitchON;
   NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-  NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW];
+  NBPtr->TrainingFlow = (VOID (*) (MEM_NB_BLOCK *)) memNTrainFlowControl[DDR3_TRAIN_FLOW];
   NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
   NBPtr->PollBitField = MemNPollBitFieldNb;
   NBPtr->BrdcstCheck = MemNBrdcstCheckON;
@@ -301,13 +301,21 @@ MemConstructNBBlockON (
   NBPtr->IsSupported[AdjustTwr] = TRUE;
   NBPtr->IsSupported[UnifiedNbFence] = TRUE;
   NBPtr->IsSupported[ChannelPDMode] = TRUE;   // Erratum 435
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_C0) != 0) {
+    NBPtr->IsSupported[AdjustTrc] = TRUE;
+  }
 
   NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON;
   NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb;
   NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb;
+  if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
+    // Do not do phase B enforcement for Rev C
   NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON;
+  }
   NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON;
   NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON;
+  NBPtr->FamilySpecificHook[BfAfExcludeDimm] = MemNBfAfExcludeDimmClientNb;
+  NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] = MemNBeforeMemClkFreqValON;
 
   FeatPtr->InitCPG (NBPtr);
   FeatPtr->InitEarlySampleSupport (NBPtr);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
index e5f8683d36..1523cd6218 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem)
- * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -241,6 +241,12 @@ MemNSetDqsODTON (
   );
 
 BOOLEAN
+MemNBeforeMemClkFreqValON (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *OptParam
+  );
+
+BOOLEAN
 MemNResetRxFifoPtrON (
   IN OUT   MEM_NB_BLOCK *NBPtr,
   IN OUT   VOID *OptParam
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
index d8c9c9df59..7f60a98ef9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c
@@ -80,6 +80,11 @@ MemNDetectMemPllErrorON (
  *
  *-----------------------------------------------------------------------------
  */
+VOID
+MemNInitEarlySampleSupportON (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 /* -----------------------------------------------------------------------------*/
 /**
  *
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
index 3f99b2c590..f85e56dc17 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -348,6 +348,7 @@ MemNInitNBRegTableON (
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15,  7, BFDramHoleOffset);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0),  0,  0, BFDramHoleValid);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31,  0, BFDramHoleAddrReg);
 
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31,  0, BFCSBaseAddr0Reg);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31,  0, BFCSBaseAddr1Reg);
@@ -486,6 +487,7 @@ MemNInitNBRegTableON (
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn);
   MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31,  0, BFAcpiPwrStsCtrlHi);
+  MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x1FC), 2, 2,  BFLowPowerDefault);
 
   MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  2,  0, BFCkeDrvStren);
   MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00,  6,  4, BFCsOdtDrvStren);
@@ -561,10 +563,15 @@ MemNInitNBRegTableON (
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F,  4,  3, BFCmdRxVioLvl);
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F,  4,  3, BFAddrRxVioLvl);
 
-  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15,  0, BFPhy0x0D080F0C);
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00,  6,  4, BFDQOdt03);
   MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08,  6,  4, BFDQOdt47);
 
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1E, 14, 12, BFDllCSRBisaTrimDByte);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1E, 14, 12, BFDllCSRBisaTrimClk);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1E, 14, 12, BFDllCSRBisaTrimCsOdt);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FCF1E, 14, 12, BFDllCSRBisaTrimAByte2);
+  MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F38, 14, 13, BFReduceLoop);
+
   MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11,  8, BFTwrrdSD);
   MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06,  3,  0, BFTrdrdSD);
   MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16,  3,  0, BFTwrwrSD);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
index 32d6f2ce3e..ac103497f6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -978,6 +978,10 @@ MemNProgramCycTimingsClientNb (
       Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8;
     }
 
+    if ((BitField == BFTrc) && NBPtr->IsSupported[AdjustTrc]) {
+      Value8 -= 5;
+    }
+
     Value8 = Value8 - TmgAdjTab[j].Bias;
     Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
 
@@ -986,7 +990,7 @@ MemNProgramCycTimingsClientNb (
             (BitField == BFTrp ) ? (Value8 <= 9) :
             (BitField == BFTrtp) ? (Value8 <= 4) :
             (BitField == BFTras) ? (Value8 <= 21) :
-            (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) :
+            (BitField == BFTrc ) ? (NBPtr->IsSupported[AdjustTrc] ? ((Value8 >= 4) && (Value8 <= 38)) : ((Value8 >= 9) && (Value8 <= 38))) :
             (BitField == BFTrrd) ? (Value8 <= 4) :
             (BitField == BFTwtr) ? (Value8 <= 4) :
             (BitField == BFTwrDDR3) ? (Value8 <= 7) :
@@ -1857,6 +1861,7 @@ MemNChangeFrequencyUnb (
     //                                                                         THEN 2 ELSE 3 ENDIF (Ontario)
     NBPtr->ProgramNbPsDependentRegs (NBPtr);
 
+    NBPtr->FamilySpecificHook[BeforeMemClkFreqVal] (NBPtr, NBPtr);
     IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
     // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
     MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
index 0779531ac4..d806fa5544 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c
@@ -87,6 +87,21 @@ RDATA_GROUP (G1_PEICC)
  */
 
 VOID
+MemNInitCPGNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNDisableDqsTrainRcvrEnHwNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
 STATIC
 MemNContWritePatternNb (
   IN OUT   MEM_NB_BLOCK *NBPtr,
@@ -203,6 +218,16 @@ MemNContWritePatternUnb (
   IN       UINT16 ClCount
   );
 
+VOID
+MemNInitCPGClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+VOID
+MemNInitCPGUnb (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
 /*----------------------------------------------------------------------------
  *                            EXPORTED FUNCTIONS
  *
@@ -924,7 +949,7 @@ MemNGenHwRcvEnReadsUnb (
   //
   // Issue Stream of Reads from the Target Rank
   //
-  NBPtr->ReadPattern (NBPtr, DummyPtr, NULL, NBPtr->TechPtr->PatternLength);
+  NBPtr->ReadPattern (NBPtr, DummyPtr, 0, NBPtr->TechPtr->PatternLength);
 }
 
 /* -----------------------------------------------------------------------------*/
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
index c6fe85045d..613aadd936 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/NB)
- * @e \$Revision: 39420 $ @e \$Date: 2010-10-12 00:52:49 +0800 (Tue, 12 Oct 2010) $
+ * @e \$Revision: 48496 $ @e \$Date: 2011-03-09 12:26:48 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -130,7 +130,6 @@ MemNSyncTargetSpeedNb (
 {
   CONST UINT16 DdrMaxRateTab[] = {
     UNSUPPORTED_DDR_FREQUENCY,
-    DDR1866_FREQUENCY,
     DDR1600_FREQUENCY,
     DDR1333_FREQUENCY,
     DDR1066_FREQUENCY,
@@ -185,8 +184,8 @@ MemNSyncTargetSpeedNb (
           Mode[Dct] = ChnlTmgMod[0];
           // Check if input clock value is valid or not
           ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
-            (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
-            (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
+            ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) :
+            ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY));
           MemClkFreq = ChnlTmgMod[1];
         }
       }
@@ -1182,3 +1181,39 @@ MemNGetMaxDdrRateUnb (
   * (UINT16 * ) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate));
   return TRUE;
 }
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *      This function performs the action before and after excluding dimms on CNB
+ *
+ *     @param[in,out]  *NBPtr     - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]  *IsBefore   - If the function is called before excluding dimms
+ *
+ *     @return    TRUE
+ *
+ */
+
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *IsBefore
+  )
+{
+  if (*(BOOLEAN *) IsBefore == TRUE) {
+    NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1);
+    NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  } else {
+    NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1);
+    NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
+  }
+
+  return TRUE;
+}
+
+/*----------------------------------------------------------------------------
+ *                              LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c
index 4aa2969d83..18298b831b 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Ps/ON)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $
  *
  **/
 /*
@@ -131,7 +131,14 @@ MemPConstructPsSON3 (
     return AGESA_UNSUPPORTED;
   }
   PsPtr->MemPDoPs = MemPDoPsSON3;
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
   PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSON3;
+  } else {
+    // Do not force frequency limit for Rev C
+    PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  }
+
   return AGESA_SUCCESS;
 }
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c
index 6e62cc0f08..41f0df01df 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem/Ps/ON)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 46937 $ @e \$Date: 2011-02-11 08:50:58 -0700 (Fri, 11 Feb 2011) $
  *
  **/
 /*
@@ -132,7 +132,14 @@ MemPConstructPsUON3 (
     return AGESA_UNSUPPORTED;
   }
   PsPtr->MemPDoPs = MemPDoPsUON3;
+
+  if ((ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_Cx) == 0) {
   PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3;
+  } else {
+    // Do not force frequency limit for Rev C
+    PsPtr->MemPGetPORFreqLimit = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
+  }
+
   return AGESA_SUCCESS;
 }
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
index 106f501948..21c8ad9261 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c
@@ -59,6 +59,7 @@
 #include "mn.h"
 #include "mu.h"
 #include "mt.h"
+#include "mt3.h"
 #include "mtrci3.h"
 #include "merrhdl.h"
 #include "Filecode.h"
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h
index 6497ea33cc..f8d853726e 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $
  *
  **/
 /*
@@ -229,6 +229,7 @@ typedef enum {
   BFSRT,                                ///< Bit field SRT
   BFTcwl,                               ///< Bit field Tcwl
   BFPchgPDModeSel,                      ///< Bit field PchgPDModeSel
+  BFLowPowerDefault,                    ///< Bit field LowPowerDefault
 
   BFTwrDDR3,                            ///< Bit field TwrDDR3
   BFTcl,                                ///< Bit field Tcl
@@ -665,6 +666,12 @@ typedef enum {
 
   BFFixedErrataSkipPorFreqCap,          ///< Bit field FixedErrataSkipPorFreqCap
 
+  BFDllCSRBisaTrimDByte,                ///< Bit field DllCSRBisaTrimDByte
+  BFDllCSRBisaTrimClk,                  ///< Bit field DllCSRBisaTrimClk
+  BFDllCSRBisaTrimCsOdt,                ///< Bit field DllCSRBisaTrimCsOdt
+  BFDllCSRBisaTrimAByte2,               ///< Bit field DllCSRBisaTrimAByte2
+  BFReduceLoop,                         ///< Bit field ReduceLoop
+
   // Reserved
   BFReserved01,                         ///< Reserved 01
   BFReserved02,                         ///< Reserved 02
@@ -983,11 +990,11 @@ AmdMemInitDataStructDefRecovery (
   IN OUT   MEM_DATA_STRUCT *MemPtr
   );
 
-VOID
-MemRecDefRet (VOID);
+//VOID
+//MemRecDefRet (VOID);
 
-BOOLEAN
-MemRecDefTrue (VOID);
+//BOOLEAN
+//MemRecDefTrue (VOID);
 
 VOID
 SetMemRecError (
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
index 8a06566f18..1f2f0b0497 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project: AGESA
  * @e sub-project: (Mem)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
+ * @e \$Revision: 48803 $ @e \$Date: 2011-03-10 20:18:28 -0700 (Thu, 10 Mar 2011) $
  *
  **/
 /*
@@ -394,6 +394,7 @@ typedef enum {
   WLNegativeDelay,                 ///< Check to determine if the NB can tolerate a negtive WL delay value
   SchedDlySlot1Extra,              ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK
   TwoStageDramInit,                ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init.
+  AdjustTrc,                       ///< Check to determine if we need to adjust Trc
 
   EnumSize                         ///< Size of list
 } NB_SUPPORTED;
@@ -401,6 +402,7 @@ typedef enum {
 /// List for family specific functions that are supported
 typedef enum {
   BeforePhyFenceTraining,          ///< Family specific tasks before Phy Fence Training
+  BeforeMemClkFreqVal,             ///< hook before setting MemClkFreqVal bit
   AfterMemClkFreqVal,              ///< Override PllMult and PllDiv
   OverridePllMult,                 ///< Override PllMult
   OverridePllDiv,                  ///< Override PllDiv
@@ -439,6 +441,7 @@ typedef enum {
   ResetRxFifoPtr,                  ///< Reset RxFifo pointer during Read DQS training
   EnableParityAfterMemRst,         ///< Enable DRAM Address Parity after memory reset.
   FinalizeVDDIO,                   ///< Finalize VDDIO
+  BfAfExcludeDimm,                 ///< Workaround before and after excluding dimms
 
   NumberOfHooks                    ///< Size of list
 } FAMILY_SPECIFIC_FUNC_INDEX;
@@ -502,6 +505,7 @@ typedef struct _MEM_NB_BLOCK {
   BOOLEAN   ClToNbFlag;        ///< is used to restore ClLinesToNbDis bit after memory
   UINT8     NbFreqChgState;    ///< is used as a state index in NB frequency change state machine
   UINT32    NbPsCtlReg;        ///< is used to save/restore NB Pstate control register
+  CONST UINT32 *RecModeDefRegArray;   ///< points to an array of default register values that are set for recovery mode
 
   ///< Determines if code should be executed on a give NB
   BOOLEAN IsSupported[EnumSize];
@@ -1345,6 +1349,15 @@ MemRecNReEnablePhyCompNb (
   IN OUT   VOID *OptParam
   );
 
+UINT32
+MemRecNcmnGetSetTrainDlyClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 IsSet,
+  IN       TRN_DLY_TYPE TrnDly,
+  IN       DRBN DrbnVar,
+  IN       UINT16 Field
+  );
+
 VOID
 MemNSetTxpNb (
   IN OUT   MEM_NB_BLOCK *NBPtr
@@ -1369,6 +1382,12 @@ MemNGetTrainDlyParmsUnb (
   IN OUT   TRN_DLY_PARMS *Parms
   );
 
+BOOLEAN
+MemNBfAfExcludeDimmClientNb (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   VOID *IsBefore
+  );
+
 #endif  /* _MN_H_ */
author	efdesign98 <efdesign98@gmail.com>	2011-08-04 12:09:17 -0600
committer	Patrick Georgi <patrick@georgi-clan.de>	2011-08-06 18:06:18 +0200
commit	84cbce2364cf3e40f24ba37b2f72a711a2e50f58 (patch)
tree	57c26631dd5c9df392e6c515b0855ef403f1e186 /src/vendorcode/amd/agesa/f14/Proc/Mem
parent	0df0e14fb5b613e76ff022359c55d5df5633b40f (diff)
download	coreboot-84cbce2364cf3e40f24ba37b2f72a711a2e50f58.tar.xz