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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-05 14:35:04 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-07 21:22:20 +0100 |
| commit | 0127c6c80865384faa43602bf22b3a70147343d9 (patch) | |
| tree | fc56798fa2d98ff7eb0f248156dd6c2d9e1bb40a /src/vendorcode/amd/agesa/f14/Proc | |
| parent | c13fc15a45560b84da77a9ca74af050d1bc19bec (diff) | |
| download | coreboot-0127c6c80865384faa43602bf22b3a70147343d9.tar.xz | |
AMD: Uniformly define MSRs for TOP_MEM and TOP_MEM2
Make the build tolerate re-definitions.
Change-Id: Ia7505837c70b1f749262508b26576e95c7865576
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8609
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h index 6369bfca48..a6f6c7819e 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuLateInit.h @@ -98,7 +98,7 @@ #define NorthbridgeCapabilities 0xE8 #define DRAMBase0 0x40 #define MMIOBase0 0x80 -#define TOP_MEM 0xC001001A +#define TOP_MEM 0xC001001Aul #define LOW_NODE_DEVICEID 24 #define LOW_APICID 0 |