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| author | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-06-25 14:50:57 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-06-28 01:32:20 +0200 |
| commit | 940ccaa51066e776ceb8fd59157ab93a619a9ef6 (patch) | |
| tree | 1a1349e998e57ff8a054a74fbf96d8526e113da2 /src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR | |
| parent | 673762906b6068d86210873fb681d0694591d4be (diff) | |
| download | coreboot-940ccaa51066e776ceb8fd59157ab93a619a9ef6.tar.xz | |
vendorcode/amd/agesa/f15: Eliminate compiler warnings
This change is mostly type casts to eliminate compile time
warnings. These specific changes are mostly cherry-picked from
AMD Family 14 code and, as such, contain artifacts copied over
from F14. For example, there are a number of UINT64 casts that
are commented out rather than removed. This is to maintain
consistency between AGESA versions. Ultimately, this is in
preparation for turning on warnings as errors for AMD Family 15
server parts.
Change-Id: Ic73d0b6ebab18d97015a9dd1130aff4e5e432fb7
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3525
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c index 2f7a061df0..afcea1ddd8 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c @@ -806,7 +806,7 @@ F15OrEarlySamplesLoadMicrocode ( // Load microcode patch into CPU GetLogicalIdOfCurrentCore (&LogicalId, StdHeader); - PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr; + PatchLoaderMsr.RawData = (UINT64)(intptr_t) MicrocodePatchPtr; PatchLoaderMsr.BitFields.SBZ = 0; // Check if this CPU is OR-B0, expected fix in OR-B1 if ((LogicalId.Revision & AMD_F15_OR_B0) != 0) { |