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author | Martin Roth <martin.roth@se-eng.com> | 2014-12-05 14:55:07 -0700 |
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committer | Martin Roth <gaumless@gmail.com> | 2014-12-06 03:14:02 +0100 |
commit | cf52f9761fef3a8e46ff28d6593e0d573ff1d4ac (patch) | |
tree | 7d81dfde67ed82624d85bbe78e3d05d2cc4d0b50 /src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h | |
parent | d2e5f6815e72ca1e52f5f08aa97dfabbd0ecbf67 (diff) | |
download | coreboot-cf52f9761fef3a8e46ff28d6593e0d573ff1d4ac.tar.xz |
intel/minnowmax: Update devicetree
- Align register values.
- Enable both EHCI and XHCI so the choice of port used can be made
at runtime. When both are enabled in devicetree, XHCI currently gets
disabled by the FSP chipset code. This can be overridden in mainboard
code or by a Kconfig entry, but there's a question about whether or not
that's desired.
- Enable function 1c.0 so the rest of the functions will be
seen, even though the function is not actually used. This is a
short-term fix, as the correct solution is to determine whether or not
any of the other functions are enabled, and not to hide function 0 if
they are. I am working on that, but I want to get this in for now.
Change-Id: I83ae12c2393024b82a55d0b3a5ffa8782e16107e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7663
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Include/OptionC6Install.h')
0 files changed, 0 insertions, 0 deletions