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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 00:26:55 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 23:53:07 +0000 |
| commit | b9bdcaecc1ccf5b8b64daddbd48dff88573251cb (patch) | |
| tree | b6044b127c606c79e939b9aaff9f3ec60c06a082 /src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c | |
| parent | 82ab9ca72c6bf14ab41e145368b219f32e596456 (diff) | |
| download | coreboot-b9bdcaecc1ccf5b8b64daddbd48dff88573251cb.tar.xz | |
vc/amd/agesa/f15tn: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9ceb37186e3622f2eac37393fa7ac5ced8efadf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43258
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c index 60b214a241..bbfe843a01 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnottn.c @@ -80,13 +80,6 @@ RDATA_GROUP (G3_DXE) * *---------------------------------------------------------------------------- */ -#if 0 -UINT32 -STATIC -MemNGetODTDelaysTN ( - IN OUT MEM_NB_BLOCK *NBPtr - ); -#endif /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS @@ -273,49 +266,3 @@ MemNSetOtherTimingTN ( IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd : %02x Twrrd : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd ); IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO ); } - -/* -----------------------------------------------------------------------------*/ -/** - * - * - * This function gets the ODT delays - * - * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK - * - */ -#if 0 -UINT32 -STATIC -MemNGetODTDelaysTN ( - IN OUT MEM_NB_BLOCK *NBPtr - ) -{ - INT8 Ld; - UINT32 ODTDelays; - // - // The BIOS must additionally configure the ODT pattern - // and the ODT switching delays. - // - // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length. - // -Read the Burst Length from F2x[1, 0]84[BurstCtrl]. - // -Value of 2, BL = 4 else assume BL=8. - // -Initialize ODTDelays based on BL value - // -WrOdtOnDuration [14:12] = BL / 2 + 1 - // -WrOdtTrnOnDly [10:8] = 0 - // -RdOdtOnDuration [6:4] = BL / 2 + 1 - // - ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050; - - // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1) - // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0] - Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5); - if (Ld < 0) { - Ld = 0; - } - if (Ld > 7) { - Ld = 7; - } - ODTDelays += Ld; - return ODTDelays; -} -#endif |