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author | Angel Pons <th3fanbus@gmail.com> | 2020-05-22 21:34:10 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-01 17:00:15 +0000 |
commit | db2e11841ad69d52a610577abb0aab288eb094b7 (patch) | |
tree | dd64111d2fed43b9c922a033db0943353c72cabc /src/vendorcode/amd/agesa/f15tn/Proc | |
parent | a81be27dc535f5177cf97ddd88458fa3946c125d (diff) | |
download | coreboot-db2e11841ad69d52a610577abb0aab288eb094b7.tar.xz |
AGESA f14/f15tn/f16kb: Clean up buildOpts.c files
Until now, the buildOpts.c files were primarily made out of copy-pasted
AGESA options, commented-out definitions and several useless comments;
that is, the materialization of technical debt in GCC-parsable form...
Until now.
It is assumed that the boards in the tree still boot. So, by comparing
their settings, we can extract saner defaults to place into AGESA. Many
of the settings were common across all boards of the same family, so we
promote those values to default settings. In some cases flipping a flag
was required, so the macros to alter that option had to be adapted as
well. Since those AGESA versions are expected to never receive updates,
it should not be a problem to change their files to suit our needs.
As a result, all but two buildOpts.c files now have less than 100 lines.
AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require
about 60 or 70 lines in those files. Hopefully, this will make porting
more mainboards using AGESA f14/f15tn/f16kb a substantially easier task.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn/Proc')
-rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h index 3e5137c655..a965a1d7d9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuLateInit.h @@ -236,7 +236,7 @@ CpuLateInitApTask ( #endif #define SCOPE_NAME_VALUE OEM_SCOPE_NAME #else - #define SCOPE_NAME_VALUE SCOPE_NAME_C + #define SCOPE_NAME_VALUE SCOPE_NAME_P #endif // OEM_SCOPE_NAME #ifdef OEM_SCOPE_NAME1 |