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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-07 06:46:46 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-26 10:06:32 +0000 |
| commit | 0f6c0b1a6f062be702fd0b10a6c591c42f982b63 (patch) | |
| tree | f7cb5f0fe9066e36ec8e241fde6a5a5f0c713e3b /src/vendorcode/amd/agesa/f15tn | |
| parent | 63fac81fc80d701a785ed61a3b5738ea0a821169 (diff) | |
| download | coreboot-0f6c0b1a6f062be702fd0b10a6c591c42f982b63.tar.xz | |
AGESA: Drop CAR teardown without POSTCAR_STAGE
Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.
AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.
Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15tn')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/gcccar.inc | 33 |
1 files changed, 3 insertions, 30 deletions
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 8e15503551..b13e02aff7 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1033,13 +1033,6 @@ fam15_enable_stack_hook_exit: * Return any family specific controls to their 'standard' * settings for using cache with main memory. * -* Note: Customized for coreboot: -* A wbinvd is used to send cache to memory. The existing stack is preserved -* at its original location and additional information is preserved (e.g. -* coreboot CAR globals, heap structures, etc.). This implementation should -* NOT be used with S3 resume IF the stack/cache area is not reserved and -* over system memory. -* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -1257,18 +1250,7 @@ fam15_disable_stack_remote_read_exit: _RDMSR btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion _WRMSR - - #-------------------------------------------------------------------------- - # Send cache to memory. Preserve stack and coreboot CAR globals. - # This shouldn't be used with S3 resume IF the stack/cache area is - # not reserved and over system memory. - #-------------------------------------------------------------------------- -#if !IS_ENABLED(CONFIG_POSTCAR_STAGE) - wbinvd -#else - invd -#endif - + invd # Clear the cache tag RAMs #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? cmp $01, %bh jz 4f @@ -1901,17 +1883,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is .endm /***************************************************************************** -* AMD_DISABLE_STACK: Implementation is modified for coreboot from -* the original AMD intent. A WBINVD is used in the HOOK -* to send dirty cache contents to DRAM backing before -* disabling cache-as-ram. This is not safe for S3 resume. -* -* todo: -* * rework PI/AGESA source to set DRAM to UC to send -* writes directly to memory -* * move DCACHE_BASE or use postcar stage for teardown -* to eliminate car_migrated problem that will occur -* after wbinvd is changed back to invd +* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine +* should only be executed on the BSP * * In: * none |