AGESA vendorcode: Move PlatformInstall.h

All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.

Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

37 files changed, 0 insertions, 11073 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionApmInstall.h
deleted file mode 100644
index 1624859e9c..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionApmInstall.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Application Power Management (APM).
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_APM_INSTALL_H_
-#define _OPTION_APM_INSTALL_H_
-
-#include "cpuApm.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_APM_FEAT
-#define F16_APM_SUPPORT
-
-#if OPTION_CPU_APM == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    // Family 16H
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
-        #undef OPTION_CPU_APM_FEAT
-        #define OPTION_CPU_APM_FEAT &CpuFeatureApm,
-        extern CONST APM_FAMILY_SERVICES ROMDATA F16ApmSupport;
-        #undef F16_APM_SUPPORT
-        #define F16_APM_SUPPORT {AMD_FAMILY_16, &F16ApmSupport},
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
-{
-  F16_APM_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
-{
-  (sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &ApmFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_APM_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionC6Install.h
deleted file mode 100644
index 53256edce4..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionC6Install.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: C6 C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_C6_STATE_INSTALL_H_
-#define _OPTION_C6_STATE_INSTALL_H_
-
-#include "cpuC6State.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_C6_STATE_FEAT
-#define F15_TN_C6_STATE_SUPPORT
-#define F16_KB_C6_STATE_SUPPORT
-
-#if OPTION_C6_STATE == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if (OPTION_FAMILY15H_TN == TRUE)
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
-          #undef OPTION_C6_STATE_FEAT
-          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
-          extern CONST C6_FAMILY_SERVICES ROMDATA F15TnC6Support;
-          #undef F15_TN_C6_STATE_SUPPORT
-          #define F15_TN_C6_STATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnC6Support},
-        #endif
-
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
-          #undef OPTION_C6_STATE_FEAT
-          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
-          extern CONST C6_FAMILY_SERVICES ROMDATA F16KbC6Support;
-          #undef F16_KB_C6_STATE_SUPPORT
-          #define F16_KB_C6_STATE_SUPPORT {AMD_FAMILY_16_KB, &F16KbC6Support},
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
-{
-  F15_TN_C6_STATE_SUPPORT
-  F16_KB_C6_STATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
-{
-  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &C6FamilyServiceArray[0]
-};
-
-#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCditInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCditInstall.h
deleted file mode 100644
index 96ee782b82..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCditInstall.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CDIT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_CDIT_INSTALL_H_
-#define _OPTION_CDIT_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-OPTION_CDIT_FEATURE          GetAcpiCditStub;
-#define USER_CDIT_OPTION     &GetAcpiCditStub
-
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_CDIT
-    #error  BLDOPT: Option not defined: "OPTION_CDIT"
-  #endif
-  #if OPTION_CDIT == TRUE
-    OPTION_CDIT_FEATURE        GetAcpiCditMain;
-    #undef USER_CDIT_OPTION
-    #define USER_CDIT_OPTION   &GetAcpiCditMain
-  #endif
-#endif
-
-/*  Declare the instance of the CDIT option configuration structure  */
-CONST OPTION_CDIT_CONFIGURATION ROMDATA OptionCditConfiguration = {
-  CDIT_STRUCT_VERSION,
-  USER_CDIT_OPTION,
-  {CFG_ACPI_SET_OEM_ID},
-  {CFG_ACPI_SET_OEM_TABLE_ID}
-};
-
-#endif  // _OPTION_CDIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpbInstall.h
deleted file mode 100644
index 42a9ff5d45..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpbInstall.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Core Performance Boost
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_CPB_INSTALL_H_
-#define _OPTION_CPB_INSTALL_H_
-
-#include "cpuCpb.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPB_FEAT
-#define F15_TN_CPB_SUPPORT
-#define F16_KB_CPB_SUPPORT
-
-#if OPTION_CPB == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if (OPTION_FAMILY15H_TN == TRUE)
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
-          #undef OPTION_CPB_FEAT
-          #define OPTION_CPB_FEAT &CpuFeatureCpb,
-          extern CONST CPB_FAMILY_SERVICES ROMDATA F15TnCpbSupport;
-          #undef F15_TN_CPB_SUPPORT
-          #define F15_TN_CPB_SUPPORT {AMD_FAMILY_15_TN, &F15TnCpbSupport},
-        #endif
-
-      #endif
-    #endif
-
-
-    // Family 16h
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
-          #undef OPTION_CPB_FEAT
-          #define OPTION_CPB_FEAT &CpuFeatureCpb,
-          extern CONST CPB_FAMILY_SERVICES ROMDATA F16KbCpbSupport;
-          #undef F16_KB_CPB_SUPPORT
-          #define F16_KB_CPB_SUPPORT {AMD_FAMILY_16_KB, &F16KbCpbSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
-{
-  F15_TN_CPB_SUPPORT
-  F16_KB_CPB_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
-{
-  (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CpbFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCacheFlushOnHaltInstall.h
deleted file mode 100644
index 9e094ec10b..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCacheFlushOnHaltInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Cache Flush On Halt
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-
-#include "cpuPostInit.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-#define F15_TN_CPU_CFOH_SUPPORT
-#define F16_KB_CPU_CFOH_SUPPORT
-
-#if OPTION_CPU_CFOH == TRUE
-  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
-        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
-        #if OPTION_FAMILY15H_TN == TRUE
-          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
-          #undef F15_TN_CPU_CFOH_SUPPORT
-          #define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
-        #endif
-
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
-        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F16KbCacheFlushOnHalt;
-          #undef F16_KB_CPU_CFOH_SUPPORT
-          #define F16_KB_CPU_CFOH_SUPPORT {AMD_FAMILY_16_KB, &F16KbCacheFlushOnHalt},
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
-{
-  F16_KB_CPU_CFOH_SUPPORT
-  F15_TN_CPU_CFOH_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
-{
-  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CacheFlushOnHaltFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCoreLevelingInstall.h
deleted file mode 100644
index 4b29b73c5c..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuCoreLevelingInstall.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Core Leveling
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
-#define _OPTION_CPU_CORELEVELING_INSTALL_H_
-
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_CORE_LEVELING_FEAT
-#define F15_TN_CPU_CORELEVELING_SUPPORT
-#define F16_KB_CPU_CORELEVELING_SUPPORT
-
-#if OPTION_CPU_CORELEVELING == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
-    // Family 15h
-    #if OPTION_FAMILY15H == TRUE
-      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
-      #undef OPTION_CPU_CORE_LEVELING_FEAT
-      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
-
-      #if (OPTION_FAMILY15H_TN == TRUE)
-        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
-        #undef F15_TN_CPU_CORELEVELING_SUPPORT
-        #define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
-      #endif
-
-    #endif
-
-    // Family 16h
-    #if OPTION_FAMILY16H == TRUE
-      extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
-      #undef OPTION_CPU_CORE_LEVELING_FEAT
-      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
-
-      #if (OPTION_FAMILY16H_KB == TRUE)
-        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F16KbCoreLeveling;
-        #undef F16_KB_CPU_CORELEVELING_SUPPORT
-        #define F16_KB_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_16_KB, &F16KbCoreLeveling},
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
-{
-  F16_KB_CPU_CORELEVELING_SUPPORT
-  F15_TN_CPU_CORELEVELING_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
-{
-  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CoreLevelingFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFamiliesInstall.h
deleted file mode 100644
index 8e61eff7ae..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFamiliesInstall.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of all appropriate CPU family specific support.
- *
- * This file generates the defaults tables for all family specific
- * combinations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-/*  Default all CPU Specific Service members to off.  They
-    will be enabled as needed by cross referencing families
-    with entry points in the family / model install files.  */
-#define USES_REGISTER_TABLES        FALSE
-#define BASE_FAMILY_PCI             FALSE
-#define MODEL_SPECIFIC_PCI          FALSE
-#define BASE_FAMILY_MSR             FALSE
-#define MODEL_SPECIFIC_MSR          FALSE
-#define BASE_FAMILY_HT_PCI          FALSE
-#define MODEL_SPECIFIC_HT_PCI       FALSE
-#define BASE_FAMILY_WORKAROUNDS     FALSE
-
-/*
- * Pull in family specific services based on entry point
- */
-#if AGESA_ENTRY_INIT_RESET == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RECOVERY == TRUE
-  #undef USES_REGISTER_TABLES
-  #define USES_REGISTER_TABLES        TRUE
-  #undef BASE_FAMILY_PCI
-  #define BASE_FAMILY_PCI             TRUE
-  #undef MODEL_SPECIFIC_PCI
-  #define MODEL_SPECIFIC_PCI          TRUE
-  #undef BASE_FAMILY_MSR
-  #define BASE_FAMILY_MSR             TRUE
-  #undef MODEL_SPECIFIC_MSR
-  #define MODEL_SPECIFIC_MSR          TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #undef USES_REGISTER_TABLES
-  #define USES_REGISTER_TABLES        TRUE
-  #undef BASE_FAMILY_PCI
-  #define BASE_FAMILY_PCI             TRUE
-  #undef MODEL_SPECIFIC_PCI
-  #define MODEL_SPECIFIC_PCI          TRUE
-  #undef BASE_FAMILY_MSR
-  #define BASE_FAMILY_MSR             TRUE
-  #undef MODEL_SPECIFIC_MSR
-  #define MODEL_SPECIFIC_MSR          TRUE
-  #undef BASE_FAMILY_HT_PCI
-  #define BASE_FAMILY_HT_PCI          TRUE
-  #undef MODEL_SPECIFIC_HT_PCI
-  #define MODEL_SPECIFIC_HT_PCI       TRUE
-  #undef BASE_FAMILY_WORKAROUNDS
-  #define BASE_FAMILY_WORKAROUNDS     TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_POST == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_ENV == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_MID == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_S3SAVE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RESUME == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
-#endif
-
-/*
- * Initialize PCI MMIO mask to 0
- */
-#define FAMILY_MMIO_BASE_MASK (0ull)
-
-
-/*
- * Initialize all families to disabled
- */
-#define OPT_F15_TABLE
-#define OPT_F16_TABLE
-
-#define OPT_F15_ID_TABLE
-#define OPT_F16_ID_TABLE
-
-
-/*
- * Install family specific support
- */
-#if (OPTION_FAMILY15H_TN == TRUE)
-  #include  "OptionFamily15hInstall.h"
-#endif
-
-#if (OPTION_FAMILY16H_KB == TRUE)
-  #include  "OptionFamily16hInstall.h"
-#endif
-/*
- * Process PCI MMIO mask
- */
-
-// If size is 0, but base is not, break the build.
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
-  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-#endif
-
-// If base is 0, but size is not, break the build.
-#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
-  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-#endif
-
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
-  // Both are non-zero, begin further processing.
-
-  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
-  #if (CFG_PCI_MMIO_BASE < 0x800000)
-    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-  #endif
-
-  // Break the build if the address is too high for the enabled families.
-  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
-    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
-  #endif
-
-  // If the size parameter is not valid, break the build.
-  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
-    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
-      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-    #endif
-  #endif
-
-  #define PCI_MMIO_ALIGNMENT ((0x100000ul * CFG_PCI_MMIO_SIZE) - 1)
-  // If the base is not aligned according to size, break the build.
-  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
-    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
-  #endif
-  #undef PCI_MMIO_ALIGNMENT
-#endif
-
-/*
- * Process sockets / modules
- */
-#ifndef ADVCFG_PLATFORM_SOCKETS
-  #error BLDOPT Set Family supported sockets.
-#endif
-#ifndef ADVCFG_PLATFORM_MODULES
-  #error BLDOPT Set Family supported modules.
-#endif
-
-CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
-{
-  ADVCFG_PLATFORM_SOCKETS,
-  ADVCFG_PLATFORM_MODULES
-};
-
-/*
- * Instantiate global data needed for processor identification
- */
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
-{
-  OPT_F15_TABLE
-  OPT_F16_TABLE
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
-{
-  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CpuSupportedFamiliesArray[0]
-};
-
-
-CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
-{
-  OPT_F15_ID_TABLE
-  OPT_F16_ID_TABLE
-};
-
-CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
-{
-  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
-  CpuSupportedFamilyIdArray
-};
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFeaturesInstall.h
deleted file mode 100644
index 61c750aafb..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuFeaturesInstall.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of multiple CPU features.
- *
- * Aggregates enabled CPU features into a list for the dispatcher to process.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
-#define _OPTION_CPU_FEATURES_INSTALL_H_
-
-#include "OptionMsgBasedC1eInstall.h"
-#include "OptionL3FeaturesInstall.h"
-#include "OptionCpuCoreLevelingInstall.h"
-#include "OptionIoCstateInstall.h"
-#include "OptionC6Install.h"
-#include "OptionCpbInstall.h"
-#include "OptionApmInstall.h"
-#include "OptionCpuCacheFlushOnHaltInstall.h"
-#include "OptionPstateHpcModeInstall.h"
-#include "OptionLowPwrPstateInstall.h"
-#include "OptionTdpLimitingInstall.h"
-#include "OptionPsiInstall.h"
-#include "OptionHtcInstall.h"
-#include "OptionPrefetchModeInstall.h"
-#include "OptionPreserveMailboxInstall.h"
-
-CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
-{
-  OPTION_MSG_BASED_C1E_FEAT
-  OPTION_L3_FEAT
-  OPTION_CPU_CORE_LEVELING_FEAT
-  OPTION_IO_CSTATE_FEAT
-  OPTION_C6_STATE_FEAT
-  OPTION_CPU_APM_FEAT
-  OPTION_CPB_FEAT
-  OPTION_TDP_LIMIT_FEAT
-  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-  OPTION_CPU_PSTATE_HPC_MODE_FEAT             // this function should be run before low power pstate for prochot
-  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT  // this function should be run before creating ACPI objects and after Pstate initialization
-  OPTION_CPU_PSI_FEAT
-  OPTION_CPU_HTC_FEAT
-  OPTION_PREFETCH_MODE_FEAT
-  OPTION_PRESERVE_MAILBOX_FEAT
-  NULL
-};
-
-
-#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
deleted file mode 100644
index 987677e91a..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCpuSpecificServicesInstall.h
+++ /dev/null
@@ -1,1297 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of CPU specific services support
- *
- * This file generates the CPU specific services tables.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Include
- * @e \$Revision: 85962 $   @e \$Date: 2013-01-14 20:12:29 -0600 (Mon, 14 Jan 2013) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-
-/*
-
-NOTE:
-
-1. This file is designed to be included multiple times in one file. So there's no includsion guard like below.
-
-#ifndef _OPTION_CPU_FAMILY_SERVICE_INSTALL_DEFAULT_H_
-#define _OPTION_CPU_FAMILY_SERVICE_INSTALL_DEFAULT_H_
-#endif // _OPTION_CPU_FAMILY_SERVICE_INSTALL_DEFAULT_H_
-
-
-2. This file is designed to be included in below form.
-
-//
-// 1st family model specific definitions
-//
-#include "OptionCpuSpecificServicesInstallReset.h"
-#define CpuSrvcTableName                                        cpuFamilyModelServices
-// Put your service definitions "CpuSrvc<ServiceName>" here.
-#define CpuSrvcDisablePstate                                    cpuF1stM1stDisablePstate
-#include "OptionCpuSpecificServicesInstall.h"
-INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
-
-//
-// 2nd family model specific definitions
-//
-#include "OptionCpuSpecificServicesInstallReset.h"
-#define CpuSrvcTableName                                        cpuFamilyModelServices
-// Put your service definitions "CpuSrvc<ServiceName>" here.
-#define CpuSrvcDisablePstate                                    cpuF2ndM2ndDisablePstate
-#include "OptionCpuSpecificServicesInstall.h"
-INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
-
-
-Example of CPU specific services definitions:
-
-NOTE: Members with type casting should use OvrdDfltCpuSrvc<ServiceName> instead due to automatical "extern" limitation.
-
-#define CpuSrvcRevision                                        (UINT16)                                           Revision
-#define CpuSrvcDisablePstate                                   (PF_CPU_DISABLE_PSTATE)                            DisablePstate
-#define CpuSrvcTransitionPstate                                (PF_CPU_TRANSITION_PSTATE)                         TransitionPstate
-#define CpuSrvcGetProcIddMax                                   (PF_CPU_GET_IDD_MAX)                               GetProcIddMax
-#define CpuSrvcGetTscRate                                      (PF_CPU_GET_TSC_RATE)                              GetTscRate
-#define CpuSrvcGetCurrentNbFrequency                           (PF_CPU_GET_NB_FREQ)                               GetCurrentNbFrequency
-#define CpuSrvcGetMinMaxNbFrequency                            (PF_CPU_GET_MIN_MAX_NB_FREQ)                       GetMinMaxNbFrequency
-#define CpuSrvcGetNbPstateInfo                                 (PF_CPU_GET_NB_PSTATE_INFO)                        GetNbPstateInfo
-#define CpuSrvcIsNbCofInitNeeded                               (PF_CPU_IS_NBCOF_INIT_NEEDED)                      IsNbCofInitNeeded
-#define CpuSrvcGetNbIddMax                                     (PF_CPU_GET_NB_IDD_MAX)                            GetNbIddMax
-#define CpuSrvcLaunchApCore                                    (PF_CPU_AP_INITIAL_LAUNCH)                         LaunchApCore
-#define CpuSrvcGetNumberOfPhysicalCores                        (PF_CPU_NUMBER_OF_PHYSICAL_CORES)                  GetNumberOfPhysicalCores
-#define CpuSrvcGetApMailboxFromHardware                        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE)          GetApMailboxFromHardware
-#define CpuSrvcSetApCoreNumber                                 (PF_CPU_SET_AP_CORE_NUMBER)                        SetApCoreNumber
-#define CpuSrvcGetApCoreNumber                                 (PF_CPU_GET_AP_CORE_NUMBER)                        GetApCoreNumber
-#define CpuSrvcTransferApCoreNumber                            (PF_CPU_TRANSFER_AP_CORE_NUMBER)                   TransferApCoreNumber
-#define CpuSrvcGetStoredNodeNumber                             (PF_CPU_GET_STORED_NODE_NUMBER)                    GetStoredNodeNumber
-#define CpuSrvcCoreIdPositionInInitialApicId                   (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID)           CoreIdPositionInInitialApicId
-#define CpuSrvcSaveFeatures                                    (PF_CPU_SAVE_FEATURES)                             SaveFeatures
-#define CpuSrvcWriteFeatures                                   (PF_CPU_WRITE_FEATURES)                            WriteFeatures
-#define CpuSrvcSetWarmResetFlag                                (PF_CPU_SET_WARM_RESET_FLAG)                       SetWarmResetFlag
-#define CpuSrvcGetWarmResetFlag                                (PF_CPU_GET_WARM_RESET_FLAG)                       GetWarmResetFlag
-#define CpuSrvcGetBrandString1                                 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetBrandString1
-#define CpuSrvcGetBrandString2                                 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetBrandString2
-#define CpuSrvcGetMicroCodePatchesStruct                       (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetMicroCodePatchesStruct
-#define CpuSrvcGetMicrocodeEquivalenceTable                    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetMicrocodeEquivalenceTable
-#define CpuSrvcGetCacheInfo                                    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetCacheInfo
-#define CpuSrvcGetSysPmTableStruct                             (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetSysPmTableStruct
-#define CpuSrvcGetWheaInitData                                 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY)                 GetWheaInitData
-#define CpuSrvcGetPlatformTypeSpecificInfo                     (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO)           GetPlatformTypeSpecificInfo
-#define CpuSrvcIsNbPstateEnabled                               (PF_IS_NB_PSTATE_ENABLED)                          IsNbPstateEnabled
-#define CpuSrvcNextLinkHasHtPhyFeats                           (PF_NEXT_LINK_HAS_HTFPY_FEATS)                     NextLinkHasHtPhyFeats
-#define CpuSrvcSetHtPhyRegister                                (PF_SET_HT_PHY_REGISTER)                           SetHtPhyRegister
-#define CpuSrvcGetNextHtLinkFeatures                           (PF_GET_NEXT_HT_LINK_FEATURES)                     GetNextHtLinkFeatures
-#define CpuSrvcRegisterTableList                               (REGISTER_TABLE **)                                RegisterTableList
-#define CpuSrvcTableEntryTypeDescriptors                       (TABLE_ENTRY_TYPE_DESCRIPTOR *)                    TableEntryTypeDescriptors
-#define CpuSrvcPackageLinkMap                                  (PACKAGE_HTLINK_MAP)                               PackageLinkMap
-#define CpuSrvcComputeUnitMap                                  (COMPUTE_UNIT_MAP *)                               ComputeUnitMap
-#define CpuSrvcInitCacheDisabled                               (FAMILY_CACHE_INIT_POLICY)                         InitCacheDisabled
-#define CpuSrvcGetEarlyBeforeApLaunchInitOnCoreTable           (PF_GET_EARLY_INIT_TABLE)                          GetEarlyInitBeforeApLaunchOnCoreTable
-#define CpuSrvcGetEarlyAfterApLaunchInitOnCoreTable            (PF_GET_EARLY_INIT_TABLE)                          GetEarlyInitAfterApLaunchOnCoreTable
-#define CpuSrvcPatchLoaderIsSharedByCU                         (BOOLEAN)                                          TRUE
-
-  USAGE MODEL:
-
-  //
-  // If BUILD_CONFIG_SWITCH = TRUE
-  //   If override service is defined, use it as the final service definition.
-  //   If override service is not define, use default service (DlftCpuSrvc) as the final service definition.
-  //
-  // If BUILD_CONFIG_SWITCH = FALSE
-  //   Use default assert service (AssertCpuSrvc) as the final service definition for making a assertion when unsupported service is called.
-  //
-  // "extern" will be used for function pointer (exclude data) type serive members automatically when CpuSrvc<ServiceName> is defined.
-  //
-
-// Member: (MEMBER_TYPE) ServiceName
-#if BUILD_CONFIG_SWITCH == TRUE
-  #ifdef CpuSrvcServiceName
-    #define FinalCpuSrvcServiceName           CpuSrvcServiceName
-    extern  MEMBER_TYPE                       FinalCpuSrvcServiceName;
-  #else
-    #define FinalCpuSrvcServiceName           DfltCpuSrvcServiceName
-    #pragma message( STRING_MACRO_DEFAULT_USED(CpuSrvcServiceName) )
-  #endif
-#else
-  #define FinalCpuSrvcServiceName           DfltAssertCpuSrvcServiceName
-  #pragma message( STRING_MACRO_DEFAULT_ASSERT_USED(CpuSrvcServiceName) )
-#endif
-
-*/
-
-
-#define STRING2(x)                                #x
-#define STRING(x)                                 STRING2(x)
-#define CAT_STRING(a, b)                          a##b
-#define STRING_ARROW                              " --> "
-
-//
-// Verbose control for messaging CPU services at build time
-//
-#ifndef VERBOSE_CPU_SERVICES
-  #define VERBOSE_CPU_SERVICES                    1 // 0 - disable messaging, 1 - enable debugging.
-#endif
-
-#if VERBOSE_CPU_SERVICES
-  #define STRING_MACRO_VALUE(Name)                " " #Name " = " STRING(Name)
-  #define STRING_OVERRIDE_MACRO_VALUE(Name)       "  OVERRIDE: " #Name " : " STRING(Name) STRING_ARROW STRING(Ovrd##Name)
-  #define STRING_MACRO_DEFAULT_USED(Name)         "  NOT DEFINED: "  #Name STRING_ARROW " DEFAULT: " STRING(FinalDflt##Name)
-  #define STRING_MACRO_DEFAULT_ASSERT_USED(Name)  "  DISABLED: " #Name ", assertion is used."
-
-  #define STRING_SEPARATOR1                       "-----------------------------------------------------------------------------------------------"
-  #define STRING_SEPARATOR2                       "==============================================================================================="
-  #define STRING_SEPARATOR_POUND                  "###############################################################################################"
-#else // VERBOSE_CPU_SERVICES
-  #define STRING_MACRO_VALUE(Name)                NULL_STRING
-  #define STRING_OVERRIDE_MACRO_VALUE(Name)       NULL_STRING
-  #define STRING_MACRO_DEFAULT_USED(Name)         NULL_STRING
-  #define STRING_MACRO_DEFAULT_ASSERT_USED(Name)  NULL_STRING
-
-
-  #define NULL_STRING                             ""
-  #define STRING_SEPARATOR1                       NULL_STRING
-  #define STRING_SEPARATOR2                       NULL_STRING
-  #define STRING_SEPARATOR_POUND                  NULL_STRING
-#endif // VERBOSE_CPU_SERVICES
-
-//
-// Handle override definitions on DfltAssertCpuSrvc<ServiceName>
-//
-
-#ifdef OvrdDfltAssertCpuSrvcRevision
-  #define FinalDfltAssertCpuSrvcRevision                              OvrdDfltAssertCpuSrvcRevision
-#else
-  #define FinalDfltAssertCpuSrvcRevision                              DfltAssertCpuSrvcRevision
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcDisablePstate
-  #define FinalDfltAssertCpuSrvcDisablePstate                         OvrdDfltAssertCpuSrvcDisablePstate
-#else
-  #define FinalDfltAssertCpuSrvcDisablePstate                         DfltAssertCpuSrvcDisablePstate
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcTransitionPstate
-  #define FinalDfltAssertCpuSrvcTransitionPstate                      OvrdDfltAssertCpuSrvcTransitionPstate
-#else
-  #define FinalDfltAssertCpuSrvcTransitionPstate                      DfltAssertCpuSrvcTransitionPstate
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetProcIddMax
-  #define FinalDfltAssertCpuSrvcGetProcIddMax                         OvrdDfltAssertCpuSrvcGetProcIddMax
-#else
-  #define FinalDfltAssertCpuSrvcGetProcIddMax                         DfltAssertCpuSrvcGetProcIddMax
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetTscRate
-  #define FinalDfltAssertCpuSrvcGetTscRate                            OvrdDfltAssertCpuSrvcGetTscRate
-#else
-  #define FinalDfltAssertCpuSrvcGetTscRate                            DfltAssertCpuSrvcGetTscRate
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetCurrentNbFrequency
-  #define FinalDfltAssertCpuSrvcGetCurrentNbFrequency                 OvrdDfltAssertCpuSrvcGetCurrentNbFrequency
-#else
-  #define FinalDfltAssertCpuSrvcGetCurrentNbFrequency                 DfltAssertCpuSrvcGetCurrentNbFrequency
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetMinMaxNbFrequency
-  #define FinalDfltAssertCpuSrvcGetMinMaxNbFrequency                  OvrdDfltAssertCpuSrvcGetMinMaxNbFrequency
-#else
-  #define FinalDfltAssertCpuSrvcGetMinMaxNbFrequency                  DfltAssertCpuSrvcGetMinMaxNbFrequency
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetNbPstateInfo
-  #define FinalDfltAssertCpuSrvcGetNbPstateInfo                       OvrdDfltAssertCpuSrvcGetNbPstateInfo
-#else
-  #define FinalDfltAssertCpuSrvcGetNbPstateInfo                       DfltAssertCpuSrvcGetNbPstateInfo
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcIsNbCofInitNeeded
-  #define FinalDfltAssertCpuSrvcIsNbCofInitNeeded                     OvrdDfltAssertCpuSrvcIsNbCofInitNeeded
-#else
-  #define FinalDfltAssertCpuSrvcIsNbCofInitNeeded                     DfltAssertCpuSrvcIsNbCofInitNeeded
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetNbIddMax
-  #define FinalDfltAssertCpuSrvcGetNbIddMax                           OvrdDfltAssertCpuSrvcGetNbIddMax
-#else
-  #define FinalDfltAssertCpuSrvcGetNbIddMax                           DfltAssertCpuSrvcGetNbIddMax
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcLaunchApCore
-  #define FinalDfltAssertCpuSrvcLaunchApCore                          OvrdDfltAssertCpuSrvcLaunchApCore
-#else
-  #define FinalDfltAssertCpuSrvcLaunchApCore                          DfltAssertCpuSrvcLaunchApCore
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetNumberOfPhysicalCores
-  #define FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores              OvrdDfltAssertCpuSrvcGetNumberOfPhysicalCores
-#else
-  #define FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores              DfltAssertCpuSrvcGetNumberOfPhysicalCores
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetApMailboxFromHardware
-  #define FinalDfltAssertCpuSrvcGetApMailboxFromHardware              OvrdDfltAssertCpuSrvcGetApMailboxFromHardware
-#else
-  #define FinalDfltAssertCpuSrvcGetApMailboxFromHardware              DfltAssertCpuSrvcGetApMailboxFromHardware
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcSetApCoreNumber
-  #define FinalDfltAssertCpuSrvcSetApCoreNumber                       OvrdDfltAssertCpuSrvcSetApCoreNumber
-#else
-  #define FinalDfltAssertCpuSrvcSetApCoreNumber                       DfltAssertCpuSrvcSetApCoreNumber
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetApCoreNumber
-  #define FinalDfltAssertCpuSrvcGetApCoreNumber                       OvrdDfltAssertCpuSrvcGetApCoreNumber
-#else
-  #define FinalDfltAssertCpuSrvcGetApCoreNumber                       DfltAssertCpuSrvcGetApCoreNumber
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcTransferApCoreNumber
-  #define FinalDfltAssertCpuSrvcTransferApCoreNumber                  OvrdDfltAssertCpuSrvcTransferApCoreNumber
-#else
-  #define FinalDfltAssertCpuSrvcTransferApCoreNumber                  DfltAssertCpuSrvcTransferApCoreNumber
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetStoredNodeNumber
-  #define FinalDfltAssertCpuSrvcGetStoredNodeNumber                   OvrdDfltAssertCpuSrvcGetStoredNodeNumber
-#else
-  #define FinalDfltAssertCpuSrvcGetStoredNodeNumber                   DfltAssertCpuSrvcGetStoredNodeNumber
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcCoreIdPositionInInitialApicId
-  #define FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId         OvrdDfltAssertCpuSrvcCoreIdPositionInInitialApicId
-#else
-  #define FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId         DfltAssertCpuSrvcCoreIdPositionInInitialApicId
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcSaveFeatures
-  #define FinalDfltAssertCpuSrvcSaveFeatures                          OvrdDfltAssertCpuSrvcSaveFeatures
-#else
-  #define FinalDfltAssertCpuSrvcSaveFeatures                          DfltAssertCpuSrvcSaveFeatures
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcWriteFeatures
-  #define FinalDfltAssertCpuSrvcWriteFeatures                         OvrdDfltAssertCpuSrvcWriteFeatures
-#else
-  #define FinalDfltAssertCpuSrvcWriteFeatures                         DfltAssertCpuSrvcWriteFeatures
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcSetWarmResetFlag
-  #define FinalDfltAssertCpuSrvcSetWarmResetFlag                      OvrdDfltAssertCpuSrvcSetWarmResetFlag
-#else
-  #define FinalDfltAssertCpuSrvcSetWarmResetFlag                      DfltAssertCpuSrvcSetWarmResetFlag
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetWarmResetFlag
-  #define FinalDfltAssertCpuSrvcGetWarmResetFlag                      OvrdDfltAssertCpuSrvcGetWarmResetFlag
-#else
-  #define FinalDfltAssertCpuSrvcGetWarmResetFlag                      DfltAssertCpuSrvcGetWarmResetFlag
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetBrandString1
-  #define FinalDfltAssertCpuSrvcGetBrandString1                       OvrdDfltAssertCpuSrvcGetBrandString1
-#else
-  #define FinalDfltAssertCpuSrvcGetBrandString1                       DfltAssertCpuSrvcGetBrandString1
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetBrandString2
-  #define FinalDfltAssertCpuSrvcGetBrandString2                       OvrdDfltAssertCpuSrvcGetBrandString2
-#else
-  #define FinalDfltAssertCpuSrvcGetBrandString2                       DfltAssertCpuSrvcGetBrandString2
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetMicroCodePatchesStruct
-  #define FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct             OvrdDfltAssertCpuSrvcGetMicroCodePatchesStruct
-#else
-  #define FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct             DfltAssertCpuSrvcGetMicroCodePatchesStruct
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
-  #define FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable          OvrdDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
-#else
-  #define FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable          DfltAssertCpuSrvcGetMicrocodeEquivalenceTable
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetCacheInfo
-  #define FinalDfltAssertCpuSrvcGetCacheInfo                          OvrdDfltAssertCpuSrvcGetCacheInfo
-#else
-  #define FinalDfltAssertCpuSrvcGetCacheInfo                          DfltAssertCpuSrvcGetCacheInfo
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetSysPmTableStruct
-  #define FinalDfltAssertCpuSrvcGetSysPmTableStruct                   OvrdDfltAssertCpuSrvcGetSysPmTableStruct
-#else
-  #define FinalDfltAssertCpuSrvcGetSysPmTableStruct                   DfltAssertCpuSrvcGetSysPmTableStruct
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetWheaInitData
-  #define FinalDfltAssertCpuSrvcGetWheaInitData                       OvrdDfltAssertCpuSrvcGetWheaInitData
-#else
-  #define FinalDfltAssertCpuSrvcGetWheaInitData                       DfltAssertCpuSrvcGetWheaInitData
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
-  #define FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo           OvrdDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
-#else
-  #define FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo           DfltAssertCpuSrvcGetPlatformTypeSpecificInfo
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcIsNbPstateEnabled
-  #define FinalDfltAssertCpuSrvcIsNbPstateEnabled                     OvrdDfltAssertCpuSrvcIsNbPstateEnabled
-#else
-  #define FinalDfltAssertCpuSrvcIsNbPstateEnabled                     DfltAssertCpuSrvcIsNbPstateEnabled
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcNextLinkHasHtPhyFeats
-  #define FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats                 OvrdDfltAssertCpuSrvcNextLinkHasHtPhyFeats
-#else
-  #define FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats                 DfltAssertCpuSrvcNextLinkHasHtPhyFeats
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcSetHtPhyRegister
-  #define FinalDfltAssertCpuSrvcSetHtPhyRegister                      OvrdDfltAssertCpuSrvcSetHtPhyRegister
-#else
-  #define FinalDfltAssertCpuSrvcSetHtPhyRegister                      DfltAssertCpuSrvcSetHtPhyRegister
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetNextHtLinkFeatures
-  #define FinalDfltAssertCpuSrvcGetNextHtLinkFeatures                 OvrdDfltAssertCpuSrvcGetNextHtLinkFeatures
-#else
-  #define FinalDfltAssertCpuSrvcGetNextHtLinkFeatures                 DfltAssertCpuSrvcGetNextHtLinkFeatures
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcRegisterTableList
-  #define FinalDfltAssertCpuSrvcRegisterTableList                     OvrdDfltAssertCpuSrvcRegisterTableList
-#else
-  #define FinalDfltAssertCpuSrvcRegisterTableList                     DfltAssertCpuSrvcRegisterTableList
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcTableEntryTypeDescriptors
-  #define FinalDfltAssertCpuSrvcTableEntryTypeDescriptors             OvrdDfltAssertCpuSrvcTableEntryTypeDescriptors
-#else
-  #define FinalDfltAssertCpuSrvcTableEntryTypeDescriptors             DfltAssertCpuSrvcTableEntryTypeDescriptors
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcPackageLinkMap
-  #define FinalDfltAssertCpuSrvcPackageLinkMap                        OvrdDfltAssertCpuSrvcPackageLinkMap
-#else
-  #define FinalDfltAssertCpuSrvcPackageLinkMap                        DfltAssertCpuSrvcPackageLinkMap
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcComputeUnitMap
-  #define FinalDfltAssertCpuSrvcComputeUnitMap                        OvrdDfltAssertCpuSrvcComputeUnitMap
-#else
-  #define FinalDfltAssertCpuSrvcComputeUnitMap                        DfltAssertCpuSrvcComputeUnitMap
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcInitCacheDisabled
-  #define FinalDfltAssertCpuSrvcInitCacheDisabled                     OvrdDfltAssertCpuSrvcInitCacheDisabled
-#else
-  #define FinalDfltAssertCpuSrvcInitCacheDisabled                     DfltAssertCpuSrvcInitCacheDisabled
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-  #define FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable OvrdDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-#else
-  #define FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable DfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-  #define FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable  OvrdDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-#else
-  #define FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable  DfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-#endif
-
-#ifdef OvrdDfltAssertCpuSrvcPatchLoaderIsSharedByCU
-  #define FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU               OvrdDfltAssertCpuSrvcPatchLoaderIsSharedByCU
-#else
-  #define FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU               DfltAssertCpuSrvcPatchLoaderIsSharedByCU
-#endif
-
-//
-// Handle override definitions on DfltCpuSrvc<ServiceName>
-//
-
-#ifdef OvrdDfltCpuSrvcRevision
-  #define FinalDfltCpuSrvcRevision                                    OvrdDfltCpuSrvcRevision
-#else
-  #define FinalDfltCpuSrvcRevision                                    DfltCpuSrvcRevision
-#endif
-
-#ifdef OvrdDfltCpuSrvcDisablePstate
-  #define FinalDfltCpuSrvcDisablePstate                               OvrdDfltCpuSrvcDisablePstate
-#else
-  #define FinalDfltCpuSrvcDisablePstate                               DfltCpuSrvcDisablePstate
-#endif
-
-#ifdef OvrdDfltCpuSrvcTransitionPstate
-  #define FinalDfltCpuSrvcTransitionPstate                            OvrdDfltCpuSrvcTransitionPstate
-#else
-  #define FinalDfltCpuSrvcTransitionPstate                            DfltCpuSrvcTransitionPstate
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetProcIddMax
-  #define FinalDfltCpuSrvcGetProcIddMax                               OvrdDfltCpuSrvcGetProcIddMax
-#else
-  #define FinalDfltCpuSrvcGetProcIddMax                               DfltCpuSrvcGetProcIddMax
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetTscRate
-  #define FinalDfltCpuSrvcGetTscRate                                  OvrdDfltCpuSrvcGetTscRate
-#else
-  #define FinalDfltCpuSrvcGetTscRate                                  DfltCpuSrvcGetTscRate
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetCurrentNbFrequency
-  #define FinalDfltCpuSrvcGetCurrentNbFrequency                       OvrdDfltCpuSrvcGetCurrentNbFrequency
-#else
-  #define FinalDfltCpuSrvcGetCurrentNbFrequency                       DfltCpuSrvcGetCurrentNbFrequency
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetMinMaxNbFrequency
-  #define FinalDfltCpuSrvcGetMinMaxNbFrequency                        OvrdDfltCpuSrvcGetMinMaxNbFrequency
-#else
-  #define FinalDfltCpuSrvcGetMinMaxNbFrequency                        DfltCpuSrvcGetMinMaxNbFrequency
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetNbPstateInfo
-  #define FinalDfltCpuSrvcGetNbPstateInfo                             OvrdDfltCpuSrvcGetNbPstateInfo
-#else
-  #define FinalDfltCpuSrvcGetNbPstateInfo                             DfltCpuSrvcGetNbPstateInfo
-#endif
-
-#ifdef OvrdDfltCpuSrvcIsNbCofInitNeeded
-  #define FinalDfltCpuSrvcIsNbCofInitNeeded                           OvrdDfltCpuSrvcIsNbCofInitNeeded
-#else
-  #define FinalDfltCpuSrvcIsNbCofInitNeeded                           DfltCpuSrvcIsNbCofInitNeeded
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetNbIddMax
-  #define FinalDfltCpuSrvcGetNbIddMax                                 OvrdDfltCpuSrvcGetNbIddMax
-#else
-  #define FinalDfltCpuSrvcGetNbIddMax                                 DfltCpuSrvcGetNbIddMax
-#endif
-
-#ifdef OvrdDfltCpuSrvcLaunchApCore
-  #define FinalDfltCpuSrvcLaunchApCore                                OvrdDfltCpuSrvcLaunchApCore
-#else
-  #define FinalDfltCpuSrvcLaunchApCore                                DfltCpuSrvcLaunchApCore
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetNumberOfPhysicalCores
-  #define FinalDfltCpuSrvcGetNumberOfPhysicalCores                    OvrdDfltCpuSrvcGetNumberOfPhysicalCores
-#else
-  #define FinalDfltCpuSrvcGetNumberOfPhysicalCores                    DfltCpuSrvcGetNumberOfPhysicalCores
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetApMailboxFromHardware
-  #define FinalDfltCpuSrvcGetApMailboxFromHardware                    OvrdDfltCpuSrvcGetApMailboxFromHardware
-#else
-  #define FinalDfltCpuSrvcGetApMailboxFromHardware                    DfltCpuSrvcGetApMailboxFromHardware
-#endif
-
-#ifdef OvrdDfltCpuSrvcSetApCoreNumber
-  #define FinalDfltCpuSrvcSetApCoreNumber                             OvrdDfltCpuSrvcSetApCoreNumber
-#else
-  #define FinalDfltCpuSrvcSetApCoreNumber                             DfltCpuSrvcSetApCoreNumber
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetApCoreNumber
-  #define FinalDfltCpuSrvcGetApCoreNumber                             OvrdDfltCpuSrvcGetApCoreNumber
-#else
-  #define FinalDfltCpuSrvcGetApCoreNumber                             DfltCpuSrvcGetApCoreNumber
-#endif
-
-#ifdef OvrdDfltCpuSrvcTransferApCoreNumber
-  #define FinalDfltCpuSrvcTransferApCoreNumber                        OvrdDfltCpuSrvcTransferApCoreNumber
-#else
-  #define FinalDfltCpuSrvcTransferApCoreNumber                        DfltCpuSrvcTransferApCoreNumber
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetStoredNodeNumber
-  #define FinalDfltCpuSrvcGetStoredNodeNumber                         OvrdDfltCpuSrvcGetStoredNodeNumber
-#else
-  #define FinalDfltCpuSrvcGetStoredNodeNumber                         DfltCpuSrvcGetStoredNodeNumber
-#endif
-
-#ifdef OvrdDfltCpuSrvcCoreIdPositionInInitialApicId
-  #define FinalDfltCpuSrvcCoreIdPositionInInitialApicId               OvrdDfltCpuSrvcCoreIdPositionInInitialApicId
-#else
-  #define FinalDfltCpuSrvcCoreIdPositionInInitialApicId               DfltCpuSrvcCoreIdPositionInInitialApicId
-#endif
-
-#ifdef OvrdDfltCpuSrvcSaveFeatures
-  #define FinalDfltCpuSrvcSaveFeatures                                OvrdDfltCpuSrvcSaveFeatures
-#else
-  #define FinalDfltCpuSrvcSaveFeatures                                DfltCpuSrvcSaveFeatures
-#endif
-
-#ifdef OvrdDfltCpuSrvcWriteFeatures
-  #define FinalDfltCpuSrvcWriteFeatures                               OvrdDfltCpuSrvcWriteFeatures
-#else
-  #define FinalDfltCpuSrvcWriteFeatures                               DfltCpuSrvcWriteFeatures
-#endif
-
-#ifdef OvrdDfltCpuSrvcSetWarmResetFlag
-  #define FinalDfltCpuSrvcSetWarmResetFlag                            OvrdDfltCpuSrvcSetWarmResetFlag
-#else
-  #define FinalDfltCpuSrvcSetWarmResetFlag                            DfltCpuSrvcSetWarmResetFlag
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetWarmResetFlag
-  #define FinalDfltCpuSrvcGetWarmResetFlag                            OvrdDfltCpuSrvcGetWarmResetFlag
-#else
-  #define FinalDfltCpuSrvcGetWarmResetFlag                            DfltCpuSrvcGetWarmResetFlag
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetBrandString1
-  #define FinalDfltCpuSrvcGetBrandString1                             OvrdDfltCpuSrvcGetBrandString1
-#else
-  #define FinalDfltCpuSrvcGetBrandString1                             DfltCpuSrvcGetBrandString1
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetBrandString2
-  #define FinalDfltCpuSrvcGetBrandString2                             OvrdDfltCpuSrvcGetBrandString2
-#else
-  #define FinalDfltCpuSrvcGetBrandString2                             DfltCpuSrvcGetBrandString2
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetMicroCodePatchesStruct
-  #define FinalDfltCpuSrvcGetMicroCodePatchesStruct                   OvrdDfltCpuSrvcGetMicroCodePatchesStruct
-#else
-  #define FinalDfltCpuSrvcGetMicroCodePatchesStruct                   DfltCpuSrvcGetMicroCodePatchesStruct
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetMicrocodeEquivalenceTable
-  #define FinalDfltCpuSrvcGetMicrocodeEquivalenceTable                OvrdDfltCpuSrvcGetMicrocodeEquivalenceTable
-#else
-  #define FinalDfltCpuSrvcGetMicrocodeEquivalenceTable                DfltCpuSrvcGetMicrocodeEquivalenceTable
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetCacheInfo
-  #define FinalDfltCpuSrvcGetCacheInfo                                OvrdDfltCpuSrvcGetCacheInfo
-#else
-  #define FinalDfltCpuSrvcGetCacheInfo                                DfltCpuSrvcGetCacheInfo
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetSysPmTableStruct
-  #define FinalDfltCpuSrvcGetSysPmTableStruct                         OvrdDfltCpuSrvcGetSysPmTableStruct
-#else
-  #define FinalDfltCpuSrvcGetSysPmTableStruct                         DfltCpuSrvcGetSysPmTableStruct
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetWheaInitData
-  #define FinalDfltCpuSrvcGetWheaInitData                             OvrdDfltCpuSrvcGetWheaInitData
-#else
-  #define FinalDfltCpuSrvcGetWheaInitData                             DfltCpuSrvcGetWheaInitData
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetPlatformTypeSpecificInfo
-  #define FinalDfltCpuSrvcGetPlatformTypeSpecificInfo                 OvrdDfltCpuSrvcGetPlatformTypeSpecificInfo
-#else
-  #define FinalDfltCpuSrvcGetPlatformTypeSpecificInfo                 DfltCpuSrvcGetPlatformTypeSpecificInfo
-#endif
-
-#ifdef OvrdDfltCpuSrvcIsNbPstateEnabled
-  #define FinalDfltCpuSrvcIsNbPstateEnabled                           OvrdDfltCpuSrvcIsNbPstateEnabled
-#else
-  #define FinalDfltCpuSrvcIsNbPstateEnabled                           DfltCpuSrvcIsNbPstateEnabled
-#endif
-
-#ifdef OvrdDfltCpuSrvcNextLinkHasHtPhyFeats
-  #define FinalDfltCpuSrvcNextLinkHasHtPhyFeats                       OvrdDfltCpuSrvcNextLinkHasHtPhyFeats
-#else
-  #define FinalDfltCpuSrvcNextLinkHasHtPhyFeats                       DfltCpuSrvcNextLinkHasHtPhyFeats
-#endif
-
-#ifdef OvrdDfltCpuSrvcSetHtPhyRegister
-  #define FinalDfltCpuSrvcSetHtPhyRegister                            OvrdDfltCpuSrvcSetHtPhyRegister
-#else
-  #define FinalDfltCpuSrvcSetHtPhyRegister                            DfltCpuSrvcSetHtPhyRegister
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetNextHtLinkFeatures
-  #define FinalDfltCpuSrvcGetNextHtLinkFeatures                       OvrdDfltCpuSrvcGetNextHtLinkFeatures
-#else
-  #define FinalDfltCpuSrvcGetNextHtLinkFeatures                       DfltCpuSrvcGetNextHtLinkFeatures
-#endif
-
-#ifdef OvrdDfltCpuSrvcRegisterTableList
-  #define FinalDfltCpuSrvcRegisterTableList                           OvrdDfltCpuSrvcRegisterTableList
-#else
-  #define FinalDfltCpuSrvcRegisterTableList                           DfltCpuSrvcRegisterTableList
-#endif
-
-#ifdef OvrdDfltCpuSrvcTableEntryTypeDescriptors
-  #define FinalDfltCpuSrvcTableEntryTypeDescriptors                   OvrdDfltCpuSrvcTableEntryTypeDescriptors
-#else
-  #define FinalDfltCpuSrvcTableEntryTypeDescriptors                   DfltCpuSrvcTableEntryTypeDescriptors
-#endif
-
-#ifdef OvrdDfltCpuSrvcPackageLinkMap
-  #define FinalDfltCpuSrvcPackageLinkMap                              OvrdDfltCpuSrvcPackageLinkMap
-#else
-  #define FinalDfltCpuSrvcPackageLinkMap                              DfltCpuSrvcPackageLinkMap
-#endif
-
-#ifdef OvrdDfltCpuSrvcComputeUnitMap
-  #define FinalDfltCpuSrvcComputeUnitMap                              OvrdDfltCpuSrvcComputeUnitMap
-#else
-  #define FinalDfltCpuSrvcComputeUnitMap                              DfltCpuSrvcComputeUnitMap
-#endif
-
-#ifdef OvrdDfltCpuSrvcInitCacheDisabled
-  #define FinalDfltCpuSrvcInitCacheDisabled                           OvrdDfltCpuSrvcInitCacheDisabled
-#else
-  #define FinalDfltCpuSrvcInitCacheDisabled                           DfltCpuSrvcInitCacheDisabled
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-  #define FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable       OvrdDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-#else
-  #define FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable       DfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-#endif
-
-#ifdef OvrdDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-  #define FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable        OvrdDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-#else
-  #define FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable        DfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-#endif
-
-#ifdef OvrdDfltCpuSrvcPatchLoaderIsSharedByCU
-  #define FinalDfltCpuSrvcPatchLoaderIsSharedByCU                     OvrdDfltCpuSrvcPatchLoaderIsSharedByCU
-#else
-  #define FinalDfltCpuSrvcPatchLoaderIsSharedByCU                     DfltCpuSrvcPatchLoaderIsSharedByCU
-#endif
-
-
-//
-// Make final service definition with considerations of below:
-// 1. Common build config swich control
-// 2. Override service definition
-//
-
-// Member: (UINT16) Revision
-#ifdef CpuSrvcRevision
-  #define FinalCpuSrvcRevision                                CpuSrvcRevision
-#else
-  #define FinalCpuSrvcRevision                                FinalDfltCpuSrvcRevision
-#endif
-
-// Member: (PF_CPU_DISABLE_PSTATE) DisablePstate
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcDisablePstate
-    #define FinalCpuSrvcDisablePstate                           CpuSrvcDisablePstate
-    #ifndef EXTERN_FINALCPUSRVCDISABLEPSTATE
-    #define EXTERN_FINALCPUSRVCDISABLEPSTATE
-        extern  F_CPU_DISABLE_PSTATE                                FinalCpuSrvcDisablePstate;
-    #endif
-  #else
-    #define FinalCpuSrvcDisablePstate                           FinalDfltCpuSrvcDisablePstate
-  #endif
-#else
-  #define FinalCpuSrvcDisablePstate                           FinalDfltAssertCpuSrvcDisablePstate
-#endif
-
-// Member: (PF_CPU_TRANSITION_PSTATE) TransitionPstate
-#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcTransitionPstate
-    #define FinalCpuSrvcTransitionPstate                        CpuSrvcTransitionPstate
-    #ifndef EXTERN_FINALCPUSRVCTRANSITIONPSTATE
-    #define EXTERN_FINALCPUSRVCTRANSITIONPSTATE
-        extern  F_CPU_TRANSITION_PSTATE                             FinalCpuSrvcTransitionPstate;
-    #endif
-  #else
-    #define FinalCpuSrvcTransitionPstate                        FinalDfltCpuSrvcTransitionPstate
-  #endif
-#else
-  #define FinalCpuSrvcTransitionPstate                        FinalDfltAssertCpuSrvcTransitionPstate
-#endif
-
-// Member: (PF_CPU_GET_IDD_MAX) GetProcIddMax
-#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
-  #ifdef CpuSrvcGetProcIddMax
-    #define FinalCpuSrvcGetProcIddMax                           CpuSrvcGetProcIddMax
-    extern  F_CPU_GET_IDD_MAX                                   FinalCpuSrvcGetProcIddMax;
-  #else
-    #define FinalCpuSrvcGetProcIddMax                           FinalDfltCpuSrvcGetProcIddMax
-  #endif
-#else
-  #define FinalCpuSrvcGetProcIddMax                           FinalDfltAssertCpuSrvcGetProcIddMax
-#endif
-
-// Member: (PF_CPU_GET_TSC_RATE) GetTscRate
-#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcGetTscRate
-    #define FinalCpuSrvcGetTscRate                              CpuSrvcGetTscRate
-    #ifndef EXTERN_FINALCPUSRVCGETTSCRATE
-    #define EXTERN_FINALCPUSRVCGETTSCRATE
-        extern  F_CPU_GET_TSC_RATE                                  FinalCpuSrvcGetTscRate;
-    #endif
-  #else
-    #define FinalCpuSrvcGetTscRate                              FinalDfltCpuSrvcGetTscRate
-  #endif
-#else
-  #define FinalCpuSrvcGetTscRate                              FinalDfltAssertCpuSrvcGetTscRate
-#endif
-
-// Member: (PF_CPU_GET_NB_FREQ) GetCurrentNbFrequency
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetCurrentNbFrequency
-    #define FinalCpuSrvcGetCurrentNbFrequency                   CpuSrvcGetCurrentNbFrequency
-    extern  F_CPU_GET_NB_FREQ                                   FinalCpuSrvcGetCurrentNbFrequency;
-  #else
-    #define FinalCpuSrvcGetCurrentNbFrequency                   FinalDfltCpuSrvcGetCurrentNbFrequency
-  #endif
-#else
-  #define FinalCpuSrvcGetCurrentNbFrequency                   FinalDfltAssertCpuSrvcGetCurrentNbFrequency
-#endif
-
-
-// Member: (PF_CPU_GET_MIN_MAX_NB_FREQ) GetMinMaxNbFrequency
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetMinMaxNbFrequency
-    #define FinalCpuSrvcGetMinMaxNbFrequency                    CpuSrvcGetMinMaxNbFrequency
-    extern  F_CPU_GET_MIN_MAX_NB_FREQ                           FinalCpuSrvcGetMinMaxNbFrequency;
-  #else
-    #define FinalCpuSrvcGetMinMaxNbFrequency                    FinalDfltCpuSrvcGetMinMaxNbFrequency
-  #endif
-#else
-  #define FinalCpuSrvcGetMinMaxNbFrequency                    FinalDfltAssertCpuSrvcGetMinMaxNbFrequency
-#endif
-
-// Member: (PF_CPU_GET_NB_PSTATE_INFO) GetNbPstateInfo
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetNbPstateInfo
-    #define FinalCpuSrvcGetNbPstateInfo                         CpuSrvcGetNbPstateInfo
-    extern  F_CPU_GET_NB_PSTATE_INFO                            FinalCpuSrvcGetNbPstateInfo;
-  #else
-    #define FinalCpuSrvcGetNbPstateInfo                         FinalDfltCpuSrvcGetNbPstateInfo
-  #endif
-#else
-  #define FinalCpuSrvcGetNbPstateInfo                         FinalDfltAssertCpuSrvcGetNbPstateInfo
-#endif
-
-// Member: (PF_CPU_IS_NBCOF_INIT_NEEDED) IsNbCofInitNeeded
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcIsNbCofInitNeeded
-    #define FinalCpuSrvcIsNbCofInitNeeded                       CpuSrvcIsNbCofInitNeeded
-    extern  F_CPU_IS_NBCOF_INIT_NEEDED                          FinalCpuSrvcIsNbCofInitNeeded;
-  #else
-    #define FinalCpuSrvcIsNbCofInitNeeded                       FinalDfltCpuSrvcIsNbCofInitNeeded
-  #endif
-#else
-  #define FinalCpuSrvcIsNbCofInitNeeded                       FinalDfltAssertCpuSrvcIsNbCofInitNeeded
-#endif
-
-// Member:    (PF_CPU_GET_NB_IDD_MAX) GetNbIddMax
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetNbIddMax
-    #define FinalCpuSrvcGetNbIddMax                             CpuSrvcGetNbIddMax
-    extern  F_CPU_GET_NB_IDD_MAX                                FinalCpuSrvcGetNbIddMax;
-  #else
-    #define FinalCpuSrvcGetNbIddMax                             FinalDfltCpuSrvcGetNbIddMax
-  #endif
-#else
-  #define FinalCpuSrvcGetNbIddMax                             FinalDfltAssertCpuSrvcGetNbIddMax
-#endif
-
-// Member:  (PF_CPU_AP_INITIAL_LAUNCH) LaunchApCore
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcLaunchApCore
-    #define FinalCpuSrvcLaunchApCore                            CpuSrvcLaunchApCore
-    #ifndef EXTERN_FINALCPUSRVCLAUNCHAPCORE
-    #define EXTERN_FINALCPUSRVCLAUNCHAPCORE
-        extern  F_CPU_AP_INITIAL_LAUNCH                             FinalCpuSrvcLaunchApCore;
-    #endif
-  #else
-    #define FinalCpuSrvcLaunchApCore                            FinalDfltCpuSrvcLaunchApCore
-  #endif
-#else
-  #define FinalCpuSrvcLaunchApCore                            FinalDfltAssertCpuSrvcLaunchApCore
-#endif
-
-// Member:(PF_CPU_NUMBER_OF_PHYSICAL_CORES) GetNumberOfPhysicalCores
-#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcGetNumberOfPhysicalCores
-    #define FinalCpuSrvcGetNumberOfPhysicalCores                CpuSrvcGetNumberOfPhysicalCores
-    extern  F_CPU_NUMBER_OF_PHYSICAL_CORES                      FinalCpuSrvcGetNumberOfPhysicalCores;
-  #else
-    #define FinalCpuSrvcGetNumberOfPhysicalCores                FinalDfltCpuSrvcGetNumberOfPhysicalCores
-  #endif
-#else
-  #define FinalCpuSrvcGetNumberOfPhysicalCores                FinalDfltAssertCpuSrvcGetNumberOfPhysicalCores
-#endif
-
-// Member: (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) GetApMailboxFromHardware
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcGetApMailboxFromHardware
-    #define FinalCpuSrvcGetApMailboxFromHardware                CpuSrvcGetApMailboxFromHardware
-    extern  F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE              FinalCpuSrvcGetApMailboxFromHardware;
-  #else
-    #define FinalCpuSrvcGetApMailboxFromHardware                FinalDfltCpuSrvcGetApMailboxFromHardware
-  #endif
-#else
-  #define FinalCpuSrvcGetApMailboxFromHardware                FinalDfltAssertCpuSrvcGetApMailboxFromHardware
-#endif
-
-// Member: (PF_CPU_SET_AP_CORE_NUMBER) SetApCoreNumber
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcSetApCoreNumber
-    #define FinalCpuSrvcSetApCoreNumber                         CpuSrvcSetApCoreNumber
-    extern  F_CPU_SET_AP_CORE_NUMBER                            FinalCpuSrvcSetApCoreNumber;
-  #else
-    #define FinalCpuSrvcSetApCoreNumber                         FinalDfltCpuSrvcSetApCoreNumber
-  #endif
-#else
-  #define FinalCpuSrvcSetApCoreNumber                         FinalDfltAssertCpuSrvcSetApCoreNumber
-#endif
-
-// Member: (PF_CPU_GET_AP_CORE_NUMBER) GetApCoreNumber
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || \
-    (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcGetApCoreNumber
-    #define FinalCpuSrvcGetApCoreNumber                         CpuSrvcGetApCoreNumber
-    extern  F_CPU_GET_AP_CORE_NUMBER                            FinalCpuSrvcGetApCoreNumber;
-  #else
-    #define FinalCpuSrvcGetApCoreNumber                         FinalDfltCpuSrvcGetApCoreNumber
-  #endif
-#else
-  #define FinalCpuSrvcGetApCoreNumber                         FinalDfltAssertCpuSrvcGetApCoreNumber
-#endif
-
-// Member: (PF_CPU_TRANSFER_AP_CORE_NUMBER) TransferApCoreNumber
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcTransferApCoreNumber
-    #define FinalCpuSrvcTransferApCoreNumber                    CpuSrvcTransferApCoreNumber
-    extern  F_CPU_TRANSFER_AP_CORE_NUMBER                       FinalCpuSrvcTransferApCoreNumber;
-  #else
-    #define FinalCpuSrvcTransferApCoreNumber                    FinalDfltCpuSrvcTransferApCoreNumber
-  #endif
-#else
-  #define FinalCpuSrvcTransferApCoreNumber                    FinalDfltAssertCpuSrvcTransferApCoreNumber
-#endif
-
-// Member: (PF_CPU_GET_STORED_NODE_NUMBER) GetStoredNodeNumber
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || \
-    (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || \
-    (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || \
-    (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) || (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-  #ifdef CpuSrvcGetStoredNodeNumber
-    #define FinalCpuSrvcGetStoredNodeNumber                     CpuSrvcGetStoredNodeNumber
-    extern  F_CPU_GET_STORED_NODE_NUMBER                        FinalCpuSrvcGetStoredNodeNumber;
-  #else
-    #define FinalCpuSrvcGetStoredNodeNumber                     FinalDfltCpuSrvcGetStoredNodeNumber
-  #endif
-#else
-  #define FinalCpuSrvcGetStoredNodeNumber                     FinalDfltAssertCpuSrvcGetStoredNodeNumber
-#endif
-
-// Member: (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CoreIdPositionInInitialApicId
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || \
-    (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-  #ifdef CpuSrvcCoreIdPositionInInitialApicId
-    #define FinalCpuSrvcCoreIdPositionInInitialApicId           CpuSrvcCoreIdPositionInInitialApicId
-    #ifndef EXTERN_FINALCPUSRVCCOREIDPOSITIONININITIALAPICID
-    #define EXTERN_FINALCPUSRVCCOREIDPOSITIONININITIALAPICID
-        extern  F_CORE_ID_POSITION_IN_INITIAL_APIC_ID               FinalCpuSrvcCoreIdPositionInInitialApicId;
-    #endif
-  #else
-    #define FinalCpuSrvcCoreIdPositionInInitialApicId           FinalDfltCpuSrvcoreIdPositionInInitialApicId
-  #endif
-#else
-  #define FinalCpuSrvcCoreIdPositionInInitialApicId           FinalDfltAssertCpuSrvcCoreIdPositionInInitialApicId
-#endif
-
-// Member: (PF_CPU_SAVE_FEATURES) SaveFeatures
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-  #ifdef CpuSrvcSaveFeatures
-    #define FinalCpuSrvcSaveFeatures                            CpuSrvcSaveFeatures
-    extern  F_CPU_SAVE_FEATURES                                 FinalCpuSrvcSaveFeatures;
-  #else
-    #define FinalCpuSrvcSaveFeatures                            FinalDfltCpuSrvcSaveFeatures
-  #endif
-#else
-  #define FinalCpuSrvcSaveFeatures                            FinalDfltAssertCpuSrvcSaveFeatures
-#endif
-
-// Member: (PF_CPU_WRITE_FEATURES) WriteFeatures
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-  #ifdef CpuSrvcWriteFeatures
-    #define FinalCpuSrvcWriteFeatures                           CpuSrvcWriteFeatures
-    extern  F_CPU_WRITE_FEATURES                                FinalCpuSrvcWriteFeatures;
-  #else
-    #define FinalCpuSrvcWriteFeatures                           FinalDfltCpuSrvcWriteFeatures
-  #endif
-#else
-  #define FinalCpuSrvcWriteFeatures                           FinalDfltAssertCpuSrvcWriteFeatures
-#endif
-
-// Member: (PF_CPU_SET_WARM_RESET_FLAG) SetWarmResetFlag
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
-  #ifdef CpuSrvcSetWarmResetFlag
-    #define FinalCpuSrvcSetWarmResetFlag                        CpuSrvcSetWarmResetFlag
-    #ifndef EXTERN_FINALCPUSRVCSETWARMRESETFLAG
-    #define EXTERN_FINALCPUSRVCSETWARMRESETFLAG
-        extern  F_CPU_SET_WARM_RESET_FLAG                           FinalCpuSrvcSetWarmResetFlag;
-    #endif
-  #else
-    #define FinalCpuSrvcSetWarmResetFlag                        FinalDfltCpuSrvcSetWarmResetFlag
-  #endif
-#else
-  #define FinalCpuSrvcSetWarmResetFlag                        FinalDfltAssertCpuSrvcSetWarmResetFlag
-#endif
-
-// Member: (PF_CPU_GET_WARM_RESET_FLAG) GetWarmResetFlag
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
-  #ifdef CpuSrvcGetWarmResetFlag
-    #define FinalCpuSrvcGetWarmResetFlag                        CpuSrvcGetWarmResetFlag
-    #ifndef EXTERN_FINALCPUSRVCGETWARMRESETFLAG
-    #define EXTERN_FINALCPUSRVCGETWARMRESETFLAG
-        extern  F_CPU_GET_WARM_RESET_FLAG                           FinalCpuSrvcGetWarmResetFlag;
-    #endif
-  #else
-    #define FinalCpuSrvcGetWarmResetFlag                        FinalDfltCpuSrvcGetWarmResetFlag
-  #endif
-#else
-  #define FinalCpuSrvcGetWarmResetFlag                        FinalDfltAssertCpuSrvcGetWarmResetFlag
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetBrandString1
-#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcGetBrandString1
-    #define FinalCpuSrvcGetBrandString1                         CpuSrvcGetBrandString1
-    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetBrandString1;
-  #else
-    #define FinalCpuSrvcGetBrandString1                         FinalDfltCpuSrvcGetBrandString1
-  #endif
-#else
-  #define FinalCpuSrvcGetBrandString1                         FinalDfltAssertCpuSrvcGetBrandString1
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetBrandString2
-#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcGetBrandString2
-    #define FinalCpuSrvcGetBrandString2                         CpuSrvcGetBrandString2
-    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetBrandString2;
-  #else
-    #define FinalCpuSrvcGetBrandString2                         FinalDfltCpuSrvcGetBrandString2
-  #endif
-#else
-  #define FinalCpuSrvcGetBrandString2                         FinalDfltAssertCpuSrvcGetBrandString2
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetMicroCodePatchesStruct
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcGetMicroCodePatchesStruct
-    #define FinalCpuSrvcGetMicroCodePatchesStruct               CpuSrvcGetMicroCodePatchesStruct
-    #ifndef EXTERN_FINALCPUSRVCGETMICROCODEPATCHESSTRUCT
-    #define EXTERN_FINALCPUSRVCGETMICROCODEPATCHESSTRUCT
-        extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetMicroCodePatchesStruct;
-    #endif
-  #else
-    #define FinalCpuSrvcGetMicroCodePatchesStruct               FinalDfltCpuSrvcGetMicroCodePatchesStruct
-  #endif
-#else
-  #define FinalCpuSrvcGetMicroCodePatchesStruct               FinalDfltAssertCpuSrvcGetMicroCodePatchesStruct
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetMicrocodeEquivalenceTable
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcGetMicrocodeEquivalenceTable
-    #define FinalCpuSrvcGetMicrocodeEquivalenceTable            CpuSrvcGetMicrocodeEquivalenceTable
-    #ifndef EXTERN_FINALCPUSRVCGETMICROCODEEQUIVALENCETABLE
-    #define EXTERN_FINALCPUSRVCGETMICROCODEEQUIVALENCETABLE
-        extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetMicrocodeEquivalenceTable;
-    #endif
-  #else
-    #define FinalCpuSrvcGetMicrocodeEquivalenceTable            FinalDfltCpuSrvcGetMicrocodeEquivalenceTable
-  #endif
-#else
-  #define FinalCpuSrvcGetMicrocodeEquivalenceTable            FinalDfltAssertCpuSrvcGetMicrocodeEquivalenceTable
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetCacheInfo
-#if (AGESA_ENTRY_INIT_RESET == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcGetCacheInfo
-    #define FinalCpuSrvcGetCacheInfo                            CpuSrvcGetCacheInfo
-    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetCacheInfo;
-  #else
-    #define FinalCpuSrvcGetCacheInfo                            FinalDfltCpuSrvcGetCacheInfo
-  #endif
-#else
-  #define FinalCpuSrvcGetCacheInfo                            FinalDfltAssertCpuSrvcGetCacheInfo
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetSysPmTableStruct
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetSysPmTableStruct
-    #define FinalCpuSrvcGetSysPmTableStruct                     CpuSrvcGetSysPmTableStruct
-    extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetSysPmTableStruct;
-  #else
-    #define FinalCpuSrvcGetSysPmTableStruct                     FinalDfltCpuSrvcGetSysPmTableStruct
-  #endif
-#else
-  #define FinalCpuSrvcGetSysPmTableStruct                     FinalDfltAssertCpuSrvcGetSysPmTableStruct
-#endif
-
-// Member: (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) GetWheaInitData
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifdef CpuSrvcGetWheaInitData
-    #define FinalCpuSrvcGetWheaInitData                         CpuSrvcGetWheaInitData
-    #ifndef EXTERN_FINALCPUSRVCGETWHEAINITDATA
-    #define EXTERN_FINALCPUSRVCGETWHEAINITDATA
-        extern  F_CPU_GET_FAMILY_SPECIFIC_ARRAY                     FinalCpuSrvcGetWheaInitData;
-    #endif
-  #else
-    #define FinalCpuSrvcGetWheaInitData                         FinalDfltCpuSrvcGetWheaInitData
-  #endif
-#else
-  #define FinalCpuSrvcGetWheaInitData                         FinalDfltAssertCpuSrvcGetWheaInitData
-#endif
-
-// Member: (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) GetPlatformTypeSpecificInfo
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-  #ifdef CpuSrvcGetPlatformTypeSpecificInfo
-    #define FinalCpuSrvcGetPlatformTypeSpecificInfo             CpuSrvcGetPlatformTypeSpecificInfo
-    extern  F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO               FinalCpuSrvcGetPlatformTypeSpecificInfo;
-  #else
-    #define FinalCpuSrvcGetPlatformTypeSpecificInfo             FinalDfltCpuSrvcGetPlatformTypeSpecificInfo
-  #endif
-#else
-  #define FinalCpuSrvcGetPlatformTypeSpecificInfo             FinalDfltAssertCpuSrvcGetPlatformTypeSpecificInfo
-#endif
-
-// Member: (PF_IS_NB_PSTATE_ENABLED) IsNbPstateEnabled
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE)
-  #ifdef CpuSrvcIsNbPstateEnabled
-    #define FinalCpuSrvcIsNbPstateEnabled                       CpuSrvcIsNbPstateEnabled
-    extern  F_IS_NB_PSTATE_ENABLED                              FinalCpuSrvcIsNbPstateEnabled;
-  #else
-    #define FinalCpuSrvcIsNbPstateEnabled                       FinalDfltCpuSrvcIsNbPstateEnabled
-  #endif
-#else
-  #define FinalCpuSrvcIsNbPstateEnabled                       FinalDfltAssertCpuSrvcIsNbPstateEnabled
-#endif
-
-// Member: (PF_NEXT_LINK_HAS_HTFPY_FEATS) NextLinkHasHtPhyFeats
-#if BASE_FAMILY_HT_PCI == TRUE
-  #ifdef CpuSrvcNextLinkHasHtPhyFeats
-    #define FinalCpuSrvcNextLinkHasHtPhyFeats                   CpuSrvcNextLinkHasHtPhyFeats
-    extern  F_NEXT_LINK_HAS_HTPHY_FEATS                         FinalCpuSrvcNextLinkHasHtPhyFeats;
-  #else
-    #define FinalCpuSrvcNextLinkHasHtPhyFeats                   FinalDfltCpuSrvcNextLinkHasHtPhyFeats
-  #endif
-#else
-  #define FinalCpuSrvcNextLinkHasHtPhyFeats                   FinalDfltAssertCpuSrvcNextLinkHasHtPhyFeats
-#endif
-
-// Member: (PF_SET_HT_PHY_REGISTER) SetHtPhyRegister
-#if BASE_FAMILY_HT_PCI == TRUE
-  #ifdef CpuSrvcSetHtPhyRegister
-    #define FinalCpuSrvcSetHtPhyRegister                        CpuSrvcSetHtPhyRegister
-    extern  F_SET_HT_PHY_REGISTER                               FinalCpuSrvcSetHtPhyRegister;
-  #else
-    #define FinalCpuSrvcSetHtPhyRegister                        FinalDfltCpuSrvcSetHtPhyRegister
-  #endif
-#else
-  #define FinalCpuSrvcSetHtPhyRegister                        FinalDfltAssertCpuSrvcSetHtPhyRegister
-#endif
-
-// Member: (PF_GET_NEXT_HT_LINK_FEATURES) GetNextHtLinkFeatures
-#if BASE_FAMILY_PCI == TRUE
-  #ifdef CpuSrvcGetNextHtLinkFeatures
-    #define FinalCpuSrvcGetNextHtLinkFeatures                   CpuSrvcGetNextHtLinkFeatures
-    extern  F_GET_NEXT_HT_LINK_FEATURES                         FinalCpuSrvcGetNextHtLinkFeatures;
-  #else
-    #define FinalCpuSrvcGetNextHtLinkFeatures                   FinalDfltCpuSrvcGetNextHtLinkFeatures
-  #endif
-#else
-  #define FinalCpuSrvcGetNextHtLinkFeatures                   FinalDfltAssertCpuSrvcGetNextHtLinkFeatures
-#endif
-
-// Member: (REGISTER_TABLE **) RegisterTableList
-#if USES_REGISTER_TABLES == TRUE // (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcRegisterTableList
-    #define FinalCpuSrvcRegisterTableList                       CpuSrvcRegisterTableList
-  #else
-    #define FinalCpuSrvcRegisterTableList                       FinalDfltCpuSrvcRegisterTableList
-  #endif
-#else
-  #define FinalCpuSrvcRegisterTableList                       FinalDfltAssertCpuSrvcRegisterTableList
-#endif
-
-// Member: (TABLE_ENTRY_TYPE_DESCRIPTOR *) TableEntryTypeDescriptors
-#if USES_REGISTER_TABLES == TRUE // (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcTableEntryTypeDescriptors
-    #define FinalCpuSrvcTableEntryTypeDescriptors               CpuSrvcTableEntryTypeDescriptors
-  #else
-    #define FinalCpuSrvcTableEntryTypeDescriptors               FinalDfltCpuSrvcTableEntryTypeDescriptors
-  #endif
-#else
-  #define FinalCpuSrvcTableEntryTypeDescriptors               FinalDfltAssertCpuSrvcTableEntryTypeDescriptors
-#endif
-
-// Member: (PACKAGE_HTLINK_MAP) PackageLinkMap
-#if MODEL_SPECIFIC_HT_PCI == TRUE
-  #ifdef CpuSrvcPackageLinkMap
-    #define FinalCpuSrvcPackageLinkMap                          CpuSrvcPackageLinkMap
-  #else
-    #define FinalCpuSrvcPackageLinkMap                          FinalDfltCpuSrvcPackageLinkMap
-  #endif
-#else
-  #define FinalCpuSrvcPackageLinkMap                          FinalDfltAssertCpuSrvcPackageLinkMap
-#endif
-
-// Member: (COMPUTE_UNIT_MAP *) ComputeUnitMap
-#ifdef CpuSrvcComputeUnitMap
-  #define FinalCpuSrvcComputeUnitMap                            CpuSrvcComputeUnitMap
-#else
-  #define FinalCpuSrvcComputeUnitMap                            FinalDfltCpuSrvcComputeUnitMap
-#endif
-
-// Member: (FAMILY_CACHE_INIT_POLICY) InitCacheDisabled
-#ifdef CpuSrvcInitCacheDisabled
-  #define FinalCpuSrvcInitCacheDisabled                         CpuSrvcInitCacheDisabled
-#else
-  #define FinalCpuSrvcInitCacheDisabled                         FinalDfltCpuSrvcInitCacheDisabled
-#endif
-
-// Member: (PF_GET_EARLY_INIT_TABLE) GetEarlyInitBeforeApLaunchOnCoreTable
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-    #define FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable                 CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-    extern  F_GET_EARLY_INIT_TABLE                              FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable;
-  #else
-    #define FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable                 FinalDfltCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-  #endif
-#else
-  #define FinalCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable                   FinalDfltAssertCpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable
-#endif
-
-// Member: (PF_GET_EARLY_INIT_TABLE) GetEarlyInitAfterApLaunchOnCoreTable
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #ifdef CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-    #define FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable                 CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-    extern  F_GET_EARLY_INIT_TABLE                              FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable;
-  #else
-    #define FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable                 FinalDfltCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-  #endif
-#else
-  #define FinalCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable                   FinalDfltAssertCpuSrvcGetEarlyInitAfterApLaunchOnCoreTable
-#endif
-
-// Member: (BOOLEAN) PatchLoaderIsSharedByCU
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-  #ifdef CpuSrvcPatchLoaderIsSharedByCU
-    #define FinalCpuSrvcPatchLoaderIsSharedByCU                 CpuSrvcPatchLoaderIsSharedByCU
-  #else
-    #define FinalCpuSrvcPatchLoaderIsSharedByCU                 FinalDfltCpuSrvcPatchLoaderIsSharedByCU
-  #endif
-#else
-  #define FinalCpuSrvcPatchLoaderIsSharedByCU                 FinalDfltAssertCpuSrvcPatchLoaderIsSharedByCU
-#endif
-
-//
-// NOTE: All CPU family specific service members should be all defined now.
-//
-
-//
-// Define CPU specific services installation macro
-//
-#ifndef _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME_
-  #define _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME_
-
-  #define INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME(MacroPrefix, TableName) \
-  CONST CPU_SPECIFIC_SERVICES ROMDATA TableName =           \
-  {                                                         \
-    MacroPrefix##CpuSrvcRevision,                           \
-    MacroPrefix##CpuSrvcDisablePstate,                      \
-    MacroPrefix##CpuSrvcTransitionPstate,                   \
-    MacroPrefix##CpuSrvcGetProcIddMax,                      \
-    MacroPrefix##CpuSrvcGetTscRate,                         \
-    MacroPrefix##CpuSrvcGetCurrentNbFrequency,              \
-    MacroPrefix##CpuSrvcGetMinMaxNbFrequency,               \
-    MacroPrefix##CpuSrvcGetNbPstateInfo,                    \
-    MacroPrefix##CpuSrvcIsNbCofInitNeeded,                  \
-    MacroPrefix##CpuSrvcGetNbIddMax,                        \
-    MacroPrefix##CpuSrvcLaunchApCore,                       \
-    MacroPrefix##CpuSrvcGetNumberOfPhysicalCores,           \
-    MacroPrefix##CpuSrvcGetApMailboxFromHardware,           \
-    MacroPrefix##CpuSrvcSetApCoreNumber,                    \
-    MacroPrefix##CpuSrvcGetApCoreNumber,                    \
-    MacroPrefix##CpuSrvcTransferApCoreNumber,               \
-    MacroPrefix##CpuSrvcGetStoredNodeNumber,                \
-    MacroPrefix##CpuSrvcCoreIdPositionInInitialApicId,      \
-    MacroPrefix##CpuSrvcSaveFeatures,                       \
-    MacroPrefix##CpuSrvcWriteFeatures,                      \
-    MacroPrefix##CpuSrvcSetWarmResetFlag,                   \
-    MacroPrefix##CpuSrvcGetWarmResetFlag,                   \
-    MacroPrefix##CpuSrvcGetBrandString1,                    \
-    MacroPrefix##CpuSrvcGetBrandString2,                    \
-    MacroPrefix##CpuSrvcGetMicroCodePatchesStruct,          \
-    MacroPrefix##CpuSrvcGetMicrocodeEquivalenceTable,       \
-    MacroPrefix##CpuSrvcGetCacheInfo,                       \
-    MacroPrefix##CpuSrvcGetSysPmTableStruct,                \
-    MacroPrefix##CpuSrvcGetWheaInitData,                    \
-    MacroPrefix##CpuSrvcGetPlatformTypeSpecificInfo,        \
-    MacroPrefix##CpuSrvcIsNbPstateEnabled,                  \
-    MacroPrefix##CpuSrvcNextLinkHasHtPhyFeats,              \
-    MacroPrefix##CpuSrvcSetHtPhyRegister,                   \
-    MacroPrefix##CpuSrvcGetNextHtLinkFeatures,              \
-    MacroPrefix##CpuSrvcRegisterTableList,                  \
-    MacroPrefix##CpuSrvcTableEntryTypeDescriptors,          \
-    MacroPrefix##CpuSrvcPackageLinkMap,                     \
-    MacroPrefix##CpuSrvcComputeUnitMap,                     \
-    MacroPrefix##CpuSrvcInitCacheDisabled,                  \
-    MacroPrefix##CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable, \
-    MacroPrefix##CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable, \
-    MacroPrefix##CpuSrvcPatchLoaderIsSharedByCU             \
-  }
-#endif // _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME_
-
-#ifndef _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_
-  #define _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_
-
-  #define INSTALL_CPU_SPECIFIC_SERVICES_TABLE(TableName) \
-            INSTALL_CPU_SPECIFIC_SERVICES_TABLE_NAME (Final, TableName)
-#endif // _INSTALL_CPU_SPECIFIC_SERVICES_TABLE_
-
-//
-// Message out the final table definitions
-//
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
deleted file mode 100644
index 2b47e15de9..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionCratInstall.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CRAT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_CRAT_INSTALL_H_
-#define _OPTION_CRAT_INSTALL_H_
-
-OPTION_CRAT_FEATURE          GetAcpiCratStub;
-#define USER_CRAT_OPTION     &GetAcpiCratStub
-
-#define F15_CRAT_SUPPORT
-#define F16_CRAT_SUPPORT
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_CRAT
-    #error  BLDOPT: Option not defined: "OPTION_CRAT"
-  #endif
-  #if OPTION_CRAT == TRUE
-    OPTION_CRAT_FEATURE          GetAcpiCratMain;
-    #undef USER_CRAT_OPTION
-    #define USER_CRAT_OPTION     &GetAcpiCratMain
-    /*
-     * Family service start
-     */
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if ((OPTION_FAMILY15H_TN == TRUE)
-          extern CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport;
-          #undef F15_CRAT_SUPPORT
-          #define F15_CRAT_SUPPORT {AMD_FAMILY_15, &F15CratSupport},
-        #endif
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        extern CONST CRAT_FAMILY_SERVICES ROMDATA F16CratSupport;
-        #undef F16_CRAT_SUPPORT
-        #define F16_CRAT_SUPPORT {AMD_FAMILY_16, &F16CratSupport},
-      #endif
-    #endif
-    /*
-     * Family service end
-     */
-  #endif
-#endif
-
-/*  Declare the instance of the CRAT option configuration structure  */
-CONST OPTION_CRAT_CONFIGURATION ROMDATA OptionCratConfiguration = {
-  CRAT_STRUCT_VERSION,
-  USER_CRAT_OPTION,
-  {CFG_ACPI_SET_OEM_ID},
-  {CFG_ACPI_SET_OEM_TABLE_ID}
-};
-
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CratFamilyServiceArray[] =
-{
-  F16_CRAT_SUPPORT
-  F15_CRAT_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CratFamilyServiceTable =
-{
-  (sizeof (CratFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &CratFamilyServiceArray[0]
-};
-
-
-/// All entries that CRAT needs
-CONST S_MAKE_CRAT_ENTRY ROMDATA MakeCratEntryTable[] =
-{
-  {MakeHSAProcUnitEntry},
-  {MakeMemoryEntry},
-  {MakeCacheEntry},
-  {MakeTLBEntry},
-  /// @todo
-  //MakeFPUEntry,
-  //MakeIOEntry,
-  {NULL}
-};
-#endif  // _OPTION_CRAT_INSTALL_H_
-
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
deleted file mode 100644
index e0b09b3b6a..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: DMI
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_DMI_INSTALL_H_
-#define _OPTION_DMI_INSTALL_H_
-
-#include "cpuLateInit.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-OPTION_DMI_FEATURE                  GetDmiInfoStub;
-OPTION_DMI_RELEASE_BUFFER           ReleaseDmiBufferStub;
-#define USER_DMI_OPTION             GetDmiInfoStub
-#define USER_DMI_RELEASE_BUFFER     ReleaseDmiBufferStub
-#define CPU_DMI_AP_GET_TYPE4_TYPE7
-
-#define  FAM15_TN_DMI_TABLE
-#define  FAM16_KB_DMI_TABLE
-
-#ifndef OPTION_DMI
-  #error  BLDOPT: Option not defined: "OPTION_DMI"
-#endif
-
-#if OPTION_DMI == TRUE
-  #if AGESA_ENTRY_INIT_LATE == TRUE
-    OPTION_DMI_FEATURE          GetDmiInfoMain;
-    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
-    #undef USER_DMI_OPTION
-    #define USER_DMI_OPTION     &GetDmiInfoMain
-    #undef USER_DMI_RELEASE_BUFFER
-    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
-
-    // This additional check keeps AP launch routines from being unnecessarily included
-    // in single socket systems.
-    #if OPTION_MULTISOCKET == TRUE
-      #undef CPU_DMI_AP_GET_TYPE4_TYPE7
-      #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
-    #endif
-
-    // Family 15
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_TN == TRUE
-          extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
-          #undef FAM15_TN_DMI_TABLE
-          #define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
-        #endif
-      #endif
-    #endif
-
-    // Family 16
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        #if OPTION_FAMILY16H_KB
-          extern PROC_FAMILY_TABLE ProcFamily16KbDmiTable;
-          #undef FAM16_KB_DMI_TABLE
-          #define FAM16_KB_DMI_TABLE &ProcFamily16KbDmiTable,
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-/*  Declare the Family List. An array of pointers to tables that each describe a family  */
-CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
-  FAM15_TN_DMI_TABLE
-  FAM16_KB_DMI_TABLE
-  NULL
-};
-
-/*  Declare the instance of the DMI option configuration structure  */
-CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
-  DMI_STRUCT_VERSION,
-  USER_DMI_OPTION,
-  USER_DMI_RELEASE_BUFFER,
-  ((sizeof (ProcTables) / sizeof (PROC_FAMILY_TABLE *)) - 1),  // Including 'NULL' in above ProcTables would
-                                        // cause one more entry is counted.
-  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
-};
-
-#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h
deleted file mode 100644
index ae9e3ad352..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 16h support
- *
- * This file generates the defaults tables for family 16h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 87264 $   @e \$Date: 2013-01-31 09:26:23 -0600 (Thu, 31 Jan 2013) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_FAMILY_16H_INSTALL_H_
-#define _OPTION_FAMILY_16H_INSTALL_H_
-
-#include "OptionFamily16hEarlySample.h"
-#include "cpuFamilyTranslation.h"
-
-
-/*
- * Pull in family specific services based on entry point
- */
-
-/*
- * Common Family 16h routines
- */
-
-/*
- * Install family 16h model 00h - 0Fh support
- */
-#ifdef OPTION_FAMILY16H_KB
-  #if OPTION_FAMILY16H_KB == TRUE
-    extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableBeforeApLaunch;
-    extern CONST REGISTER_TABLE ROMDATA F16KbPciRegisterTableAfterApLaunch;
-    extern CONST REGISTER_TABLE ROMDATA F16KbPciWorkaroundTable;
-    extern CONST REGISTER_TABLE ROMDATA F16KbMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F16KbMsrWorkaroundTable;
-    extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrRegisterTable;
-    extern CONST REGISTER_TABLE ROMDATA F16KbSharedMsrWorkaroundTable;
-
-    /**
-     * Compute unit and Compute unit primary determination table.
-     *
-     * The four fields from the compute unit status hardware register can be used to determine whether
-     * even number cores are primary or all cores are primary.  It can be extended if it is
-     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
-     * but they are currently not supported by the processor.
-     */
-    CONST COMPUTE_UNIT_MAP ROMDATA HtFam16KbComputeUnitMapping[] =
-    {
-      {1, 'x', 'x', 1, QuadCoresMapping},                            ///< 1 Compute Unit with 4 Cores
-      {1, 'x',  1,  0, TripleCoresMapping},                          ///< 1 Compute Unit with 3 Cores
-      {1,  1,   0,  0, EvenCoresMapping},                            ///< 1 Compute Unit with 2 cores
-      {1,  0,   0,  0, AllCoresMapping},                             ///< 1 Compute Unit with 1 Cores
-      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
-    };
-
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F16KbRegisterTables[] =
-      {
-        #if MODEL_SPECIFIC_PCI == TRUE
-          &F16KbPciRegisterTableBeforeApLaunch,
-          &F16KbPciRegisterTableAfterApLaunch,
-          &F16KbPciWorkaroundTable,
-        #endif
-        #if MODEL_SPECIFIC_MSR == TRUE
-          &F16KbMsrRegisterTable,
-          &F16KbMsrWorkaroundTable,
-          &F16KbSharedMsrRegisterTable,
-          &F16KbSharedMsrWorkaroundTable,
-        #endif
-        // the end.
-        NULL
-      };
-    #endif
-
-    #if USES_REGISTER_TABLES == TRUE
-      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16KbTableEntryTypeDescriptors[] =
-      {
-        {MsrRegister, SetRegisterForMsrEntry},
-        {PciRegister, SetRegisterForPciEntry},
-        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
-        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
-        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
-        // End
-        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-      };
-    #endif
-
-    /**
-     * Early Init Tables
-     *
-     */
-    extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesBeforeApLaunch;
-    extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAfterApLaunch;
-    extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly;
-    extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
-    extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
-    extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly;
-
-    CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] =
-    {
-      {SetRegistersFromTablesBeforeApLaunch, PERFORM_EARLY_ANY_CONDITION},
-      {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
-      #if OPTION_EARLY_SAMPLES == TRUE
-        {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
-      #endif
-      {NULL, 0}
-    };
-
-    CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitAfterApLaunchOnCoreTable[] =
-    {
-      {SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION},
-      {F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
-      #if OPTION_EARLY_SAMPLES == FALSE
-        {F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
-      #endif
-      {NULL, 0}
-    };
-
-    #include "OptionCpuSpecificServicesInstallReset.h"
-    #define CpuSrvcTableName                            cpuF16KbServices
-
-    #define CpuSrvcDisablePstate                        F16DisablePstate
-    #define CpuSrvcTransitionPstate                     F16TransitionPstate
-    #define CpuSrvcGetProcIddMax                        F16KbGetProcIddMax
-    #define CpuSrvcGetTscRate                           F16GetTscRate
-    #define CpuSrvcGetCurrentNbFrequency                F16KbGetCurrentNbFrequency
-    #define CpuSrvcGetMinMaxNbFrequency                 F16KbGetMinMaxNbFrequency
-    #define CpuSrvcGetNbPstateInfo                      F16KbGetNbPstateInfo
-    #define CpuSrvcIsNbCofInitNeeded                    F16GetNbCofVidUpdate
-    #define CpuSrvcGetNbIddMax                          F16KbGetNbIddMax
-    #define CpuSrvcLaunchApCore                         F16LaunchApCore
-    #define CpuSrvcGetNumberOfPhysicalCores             F16KbGetNumberOfPhysicalCores
-    #define CpuSrvcGetApMailboxFromHardware             F16KbGetApMailboxFromHardware
-    #define CpuSrvcGetApCoreNumber                      F16KbGetApCoreNumber
-    #define CpuSrvcCoreIdPositionInInitialApicId        F16CpuAmdCoreIdPositionInInitialApicId
-    #define CpuSrvcSetWarmResetFlag                     F16SetAgesaWarmResetFlag
-    #define CpuSrvcGetWarmResetFlag                     F16GetAgesaWarmResetFlag
-    #define CpuSrvcGetMicroCodePatchesStruct            GetF16KbMicroCodePatchesStruct
-    #define CpuSrvcGetMicrocodeEquivalenceTable         GetF16KbMicrocodeEquivalenceTable
-    #define CpuSrvcGetCacheInfo                         GetF16CacheInfo
-    #define CpuSrvcGetSysPmTableStruct                  GetF16KbSysPmTable
-    #define CpuSrvcGetWheaInitData                      GetF16WheaInitData
-    #define CpuSrvcIsNbPstateEnabled                    F16KbIsNbPstateEnabled
-    #define CpuSrvcRegisterTableList                    (REGISTER_TABLE **) F16KbRegisterTables
-    #define CpuSrvcTableEntryTypeDescriptors            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16KbTableEntryTypeDescriptors
-    #define CpuSrvcComputeUnitMap                       (COMPUTE_UNIT_MAP *) &HtFam16KbComputeUnitMapping
-    #define CpuSrvcInitCacheDisabled                    InitCacheEnabled
-    #define CpuSrvcGetEarlyInitBeforeApLaunchOnCoreTable GetF16KbEarlyInitBeforeApLaunchOnCoreTable
-    #define CpuSrvcGetEarlyInitAfterApLaunchOnCoreTable GetF16KbEarlyInitAfterApLaunchOnCoreTable
-    #define CpuSrvcPatchLoaderIsSharedByCU              FALSE
-
-    #include "OptionCpuSpecificServicesInstall.h"
-    INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
-
-    #define KB_SOCKETS 1
-    #define KB_MODULES 1
-    #define KB_RECOVERY_SOCKETS 1
-    #define KB_RECOVERY_MODULES 1
-    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF16KbLogicalIdAndRev;
-    #define OPT_F16_KB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF16KbLogicalIdAndRev,
-    #ifndef ADVCFG_PLATFORM_SOCKETS
-      #define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS
-    #else
-      #if ADVCFG_PLATFORM_SOCKETS < KB_SOCKETS
-        #undef ADVCFG_PLATFORM_SOCKETS
-        #define ADVCFG_PLATFORM_SOCKETS KB_SOCKETS
-      #endif
-    #endif
-    #ifndef ADVCFG_PLATFORM_MODULES
-      #define ADVCFG_PLATFORM_MODULES KB_MODULES
-    #else
-      #if ADVCFG_PLATFORM_MODULES < KB_MODULES
-        #undef ADVCFG_PLATFORM_MODULES
-        #define ADVCFG_PLATFORM_MODULES KB_MODULES
-      #endif
-    #endif
-
-    #if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
-      #define F16_KB_UCODE_7000
-      #define F16_KB_UCODE_7001
-
-      #if AGESA_ENTRY_INIT_EARLY == TRUE
-        #if OPTION_EARLY_SAMPLES == TRUE
-          extern  CONST UINT8 ROMDATA  CpuF16KbId7000MicrocodePatch[];
-          #undef F16_KB_UCODE_7000
-          #define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch,
-        #endif
-        extern  CONST UINT8 ROMDATA  CpuF16KbId7001MicrocodePatch[];
-        #undef F16_KB_UCODE_7001
-        #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch,
-      #endif
-
-      CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] =
-      {
-        F16_KB_UCODE_7001
-        F16_KB_UCODE_7000
-        NULL
-      };
-
-      CONST UINT8 ROMDATA CpuF16KbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF16KbMicroCodePatchArray) / sizeof (CpuF16KbMicroCodePatchArray[0])) - 1);
-    #endif
-
-    #define OPT_F16_KB_CPU {AMD_FAMILY_16_KB, &cpuF16KbServices},
-
-  #else  //  OPTION_FAMILY16H_KB == TRUE
-    #define OPT_F16_KB_CPU
-    #define OPT_F16_KB_ID
-  #endif  //  OPTION_FAMILY16H_KB == TRUE
-#else  //  defined (OPTION_FAMILY16H_KB)
-  #define OPT_F16_KB_CPU
-  #define OPT_F16_KB_ID
-#endif  //  defined (OPTION_FAMILY16H_KB)
-
-
-/*
- * Install unknown family 16h support
- */
-
-
-#if USES_REGISTER_TABLES == TRUE
-  extern CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable;
-  extern CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable;
-  CONST REGISTER_TABLE ROMDATA *F16UnknownRegisterTables[] =
-  {
-    &F16PciUnknownRegisterTable,
-    &F16MsrUnknownRegisterTable
-    // the end.
-  };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
-  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F16UnknownTableEntryTypeDescriptors[] =
-  {
-    {MsrRegister, SetRegisterForMsrEntry},
-    {PciRegister, SetRegisterForPciEntry},
-    // End
-    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
-  };
-#endif
-
-
-
-#include "OptionCpuSpecificServicesInstallReset.h"
-#define CpuSrvcTableName                            cpuF16UnknownServices
-
-#define CpuSrvcDisablePstate                        F16DisablePstate
-#define CpuSrvcTransitionPstate                     F16TransitionPstate
-#define CpuSrvcGetTscRate                           F16GetTscRate
-#define CpuSrvcLaunchApCore                         F16LaunchApCore
-#define CpuSrvcCoreIdPositionInInitialApicId        F16CpuAmdCoreIdPositionInInitialApicId
-#define CpuSrvcSetWarmResetFlag                     F16SetAgesaWarmResetFlag
-#define CpuSrvcGetWarmResetFlag                     F16GetAgesaWarmResetFlag
-#define CpuSrvcGetMicroCodePatchesStruct            GetEmptyArray
-#define CpuSrvcGetMicrocodeEquivalenceTable         GetEmptyArray
-#define CpuSrvcGetWheaInitData                      GetF16WheaInitData
-#define CpuSrvcIsNbPstateEnabled                    F16IsNbPstateEnabled
-#define CpuSrvcRegisterTableList                    (REGISTER_TABLE **) F16UnknownRegisterTables
-#define CpuSrvcTableEntryTypeDescriptors            (TABLE_ENTRY_TYPE_DESCRIPTOR *) F16UnknownTableEntryTypeDescriptors
-#define CpuSrvcInitCacheDisabled                    InitCacheEnabled
-#define CpuSrvcPatchLoaderIsSharedByCU              FALSE
-
-#include "OptionCpuSpecificServicesInstall.h"
-INSTALL_CPU_SPECIFIC_SERVICES_TABLE (CpuSrvcTableName);
-
-// Family 16h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
-
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
-
-  #undef  FAMILY_MMIO_BASE_MASK
-
-  #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
-
-#endif
-
-
-
-#undef OPT_F16_ID_TABLE
-
-#define OPT_F16_ID_TABLE {0x16, {AMD_FAMILY_16, AMD_F16_UNKNOWN}, F16LogicalIdTable, (sizeof (F16LogicalIdTable) / sizeof (F16LogicalIdTable[0]))},
-
-#define OPT_F16_UNKNOWN_CPU {AMD_FAMILY_16, &cpuF16UnknownServices},
-
-
-#undef OPT_F16_TABLE
-
-#define OPT_F16_TABLE   OPT_F16_KB_CPU OPT_F16_UNKNOWN_CPU
-
-
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F16LogicalIdTable[] =
-
-{
-
-  OPT_F16_KB_ID
-
-};
-
-
-#endif  // _OPTION_FAMILY_16H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h
deleted file mode 100644
index 4725504159..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h
+++ /dev/null
@@ -1,1036 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 15h support
- *
- * This file generates the defaults tables for family 15h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*********************************************************************************
-;
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*********************************************************************************/
-
-#ifndef _OPTION_FCH_INSTALL_H_
-#define _OPTION_FCH_INSTALL_H_
-
-#include "AmdFch.h"
-
-#ifndef  FCH_SUPPORT
-  #define  FCH_SUPPORT   FALSE
-#endif
-
-
-/* ACPI block register offset definitions */
-#define PM1_STATUS_OFFSET              0x00
-#define PM1_ENABLE_OFFSET              0x02
-#define PM_CONTROL_OFFSET              0x04
-#define PM_TIMER_OFFSET                0x08
-#define CPU_CONTROL_OFFSET             0x10
-#define EVENT_STATUS_OFFSET            0x20
-#define EVENT_ENABLE_OFFSET            0x24
-
-
-#if  FCH_SUPPORT == TRUE
-  /*
-   * FCH subfunctions
-   */
-  #ifdef AGESA_ENTRY_INIT_RESET
-    #if AGESA_ENTRY_INIT_RESET == TRUE
-      extern FCH_TASK_ENTRY    FchInitResetHwAcpiP;
-      extern FCH_TASK_ENTRY    FchInitResetHwAcpi;
-      extern FCH_TASK_ENTRY    FchInitResetAb;
-      extern FCH_TASK_ENTRY    FchInitResetSpi;
-      extern FCH_TASK_ENTRY    FchInitResetGec;
-      extern FCH_TASK_ENTRY    FchInitResetSata;
-      extern FCH_TASK_ENTRY    FchInitResetLpc;
-      extern FCH_TASK_ENTRY    FchInitResetPcib;
-      extern FCH_TASK_ENTRY    FchInitResetPcie;
-      extern FCH_TASK_ENTRY    FchInitResetGpp;
-      extern FCH_TASK_ENTRY    FchInitAllinoneGpp;
-      extern FCH_TASK_ENTRY    FchInitResetUsb;
-      extern FCH_TASK_ENTRY    FchInitResetEhci;
-      extern FCH_TASK_ENTRY    FchInitResetOhci;
-      extern FCH_TASK_ENTRY    FchInitResetXhci;
-      extern FCH_TASK_ENTRY    FchInitResetImc;
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_ENV
-    #if AGESA_ENTRY_INIT_ENV == TRUE
-      extern FCH_TASK_ENTRY    FchInitEnvUsbXhci;
-      extern FCH_TASK_ENTRY    FchInitEnvUsbOhci;
-      extern FCH_TASK_ENTRY    FchInitEnvUsbEhci;
-      extern FCH_TASK_ENTRY    FchInitEnvUsb;
-      extern FCH_TASK_ENTRY    FchInitEnvAb;
-      extern FCH_TASK_ENTRY    FchInitEnvGpp;
-      extern FCH_TASK_ENTRY    FchInitEnvGppPhaseII;
-      extern FCH_TASK_ENTRY    FchInitEnvPcie;
-      extern FCH_TASK_ENTRY    FchInitEnvPcib;
-      extern FCH_TASK_ENTRY    FchInitEnvHwAcpiP;
-      extern FCH_TASK_ENTRY    FchInitEnvHwAcpi;
-      extern FCH_TASK_ENTRY    FchInitEnvAbSpecial;
-      extern FCH_TASK_ENTRY    FchInitEnvSpi;
-      extern FCH_TASK_ENTRY    FchInitEnvGec;
-      extern FCH_TASK_ENTRY    FchInitEnvSata;
-      extern FCH_TASK_ENTRY    FchInitEnvIde;
-      extern FCH_TASK_ENTRY    FchInitEnvSd;
-      extern FCH_TASK_ENTRY    FchInitEnvIr;
-      extern FCH_TASK_ENTRY    FchInitEnvAzalia;
-      extern FCH_TASK_ENTRY    FchInitEnvHwm;
-      extern FCH_TASK_ENTRY    FchInitEnvImc;
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_MID
-    #if AGESA_ENTRY_INIT_MID == TRUE
-      extern FCH_TASK_ENTRY    FchInitMidHwm;
-      extern FCH_TASK_ENTRY    FchInitMidAzalia;
-      extern FCH_TASK_ENTRY    FchInitMidGec;
-      extern FCH_TASK_ENTRY    FchInitMidSata;
-      extern FCH_TASK_ENTRY    FchInitMidIde;
-      extern FCH_TASK_ENTRY    FchInitMidAb;
-      extern FCH_TASK_ENTRY    FchInitMidUsb;
-      extern FCH_TASK_ENTRY    FchInitMidUsbEhci;
-      extern FCH_TASK_ENTRY    FchInitMidUsbOhci;
-      extern FCH_TASK_ENTRY    FchInitMidUsbXhci;
-      extern FCH_TASK_ENTRY    FchInitMidImc;
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_LATE
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      extern FCH_TASK_ENTRY    FchInitLateHwAcpi;
-      extern FCH_TASK_ENTRY    FchInitLateSpi;
-      extern FCH_TASK_ENTRY    FchInitLateGec;
-      extern FCH_TASK_ENTRY    FchInitLateSata;
-      extern FCH_TASK_ENTRY    FchInitLateIde;
-      extern FCH_TASK_ENTRY    FchInitLatePcib;
-      extern FCH_TASK_ENTRY    FchInitLateAb;
-      extern FCH_TASK_ENTRY    FchInitLatePcie;
-      extern FCH_TASK_ENTRY    FchInitLateGpp;
-      extern FCH_TASK_ENTRY    FchInitLateUsb;
-      extern FCH_TASK_ENTRY    FchInitLateUsbEhci;
-      extern FCH_TASK_ENTRY    FchInitLateUsbOhci;
-      extern FCH_TASK_ENTRY    FchInitLateUsbXhci;
-      extern FCH_TASK_ENTRY    FchInitLateImc;
-      extern FCH_TASK_ENTRY    FchInitLateAzalia;
-      extern FCH_TASK_ENTRY    FchInitLateHwm;
-    #endif
-  #endif
-
-  extern FCH_TASK_ENTRY    FchTaskDummy;
-  extern FCH_TASK_ENTRY    FchGppHotplugSmiCallback;
-  /* FCH Interface entries */
-  extern  FCH_INIT     CommonFchInitStub;
-
-  /* FCH Interface entries */
-  #ifdef AGESA_ENTRY_INIT_RESET
-    #if AGESA_ENTRY_INIT_RESET == TRUE
-      extern  FCH_INIT      FchInitReset;
-      extern  FCH_INIT      FchResetConstructor;
-
-      #define FP_FCH_INIT_RESET              &FchInitReset
-      #define FP_FCH_INIT_RESET_CONSTRUCT    &FchResetConstructor
-    #else
-      #define FP_FCH_INIT_RESET              &CommonFchInitStub
-      #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_ENV
-    #if AGESA_ENTRY_INIT_ENV == TRUE
-      extern  FCH_INIT      FchInitEnv;
-      extern  FCH_INIT      FchEnvConstructor;
-
-      #define FP_FCH_INIT_ENV                &FchInitEnv
-      #define FP_FCH_INIT_ENV_CONSTRUCT      &FchEnvConstructor
-    #else
-      #define FP_FCH_INIT_ENV                &CommonFchInitStub
-      #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_MID
-    #if AGESA_ENTRY_INIT_MID == TRUE
-      extern  FCH_INIT      FchInitMid;
-      extern  FCH_INIT      FchMidConstructor;
-
-      #define FP_FCH_INIT_MID                &FchInitMid
-      #define FP_FCH_INIT_MID_CONSTRUCT      &FchMidConstructor
-    #else
-      #define FP_FCH_INIT_MID                &CommonFchInitStub
-      #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_LATE
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      extern  FCH_INIT      FchInitLate;
-      extern  FCH_INIT      FchLateConstructor;
-
-      #define FP_FCH_INIT_LATE               &FchInitLate
-      #define FP_FCH_INIT_LATE_CONSTRUCT     &FchLateConstructor
-    #else
-      #define FP_FCH_INIT_LATE               &CommonFchInitStub
-      #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
-    #endif
-  #endif
-
-  /* FCH subcomponent build options */
-  #undef  FCH_NO_HWACPI_SUPPORT
-  #undef  FCH_NO_AB_SUPPORT
-  #undef  FCH_NO_SPI_SUPPORT
-  #undef  FCH_NO_GEC_SUPPORT
-  #undef  FCH_NO_SATA_SUPPORT
-  #undef  FCH_NO_IDE_SUPPORT
-  #undef  FCH_NO_LPC_SUPPORT
-  #undef  FCH_NO_PCIB_SUPPORT
-  #undef  FCH_NO_PCIE_SUPPORT
-  #undef  FCH_NO_GPP_SUPPORT
-  #undef  FCH_NO_USB_SUPPORT
-  #undef  FCH_NO_EHCI_SUPPORT
-  #undef  FCH_NO_OHCI_SUPPORT
-  #undef  FCH_NO_XHCI_SUPPORT
-  #undef  FCH_NO_IMC_SUPPORT
-  #undef  FCH_NO_SD_SUPPORT
-  #undef  FCH_NO_IR_SUPPORT
-  #undef  FCH_NO_AZALIA_SUPPORT
-  #undef  FCH_NO_HWM_SUPPORT
-
-  #define FCH_NO_GEC_SUPPORT        TRUE
-
-  // Following are determined by silicon characteristics
-  #if (FALSE)
-    #define FCH_NO_GPP_SUPPORT        TRUE
-    #define FCH_NO_PCIB_SUPPORT       TRUE
-    #define FCH_NO_PCIE_SUPPORT       TRUE
-
-    //#define FCH_NO_GEC_SUPPORT        TRUE
-  #elif (OPTION_FAMILY15H_TN == TRUE)
-    //#define FCH_NO_GEC_SUPPORT        TRUE
-  #elif (OPTION_FAMILY16H_MODEL_0x == TRUE)
-    #define FCH_NO_GPP_SUPPORT        TRUE
-    #define FCH_NO_PCIB_SUPPORT       TRUE
-    #define FCH_NO_PCIE_SUPPORT       TRUE
-    #define BLDOPT_RTC_WORKAROUND     TRUE
-  #else
-    #error FCH_SUPPORT: No chip type selected.
-  #endif
-
-
-  //
-  // Installable blocks depending on build switches
-  //
-  #ifndef FCH_NO_HWACPI_SUPPORT
-    #define BLOCK_HWACPI_SIZE           sizeof (FCH_ACPI)
-    #define InstallFchInitResetHwAcpiP  &FchInitResetHwAcpiP
-    #define InstallFchInitResetHwAcpi   &FchInitResetHwAcpi
-    #define InstallFchInitEnvHwAcpiP    &FchInitEnvHwAcpiP
-    #define InstallFchInitEnvHwAcpi     &FchInitEnvHwAcpi
-    #define InstallFchInitMidHwAcpi     &FchTaskDummy
-    #define InstallFchInitLateHwAcpi    &FchInitLateHwAcpi
-  #else
-    #define BLOCK_HWACPI_SIZE           0
-    #define InstallFchInitResetHwAcpiP  &FchTaskDummy
-    #define InstallFchInitResetHwAcpi   &FchTaskDummy
-    #define InstallFchInitEnvHwAcpi     &FchTaskDummy
-    #define InstallFchInitMidHwAcpi     &FchTaskDummy
-    #define InstallFchInitLateHwAcpi    &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_AB_SUPPORT
-    #define BLOCK_AB_SIZE               sizeof (FCH_AB)
-    #define InstallFchInitResetAb       &FchInitResetAb
-    #define InstallFchInitEnvAb         &FchInitEnvAb
-    #define InstallFchInitEnvAbS        &FchInitEnvAbSpecial
-    #define InstallFchInitMidAb         &FchInitMidAb
-    #define InstallFchInitLateAb        &FchInitLateAb
-  #else
-    #define BLOCK_AB_SIZE               0
-    #define InstallFchInitResetAb       &FchTaskDummy
-    #define InstallFchInitEnvAb         &FchTaskDummy
-    #define InstallFchInitEnvAbS        &FchTaskDummy
-    #define InstallFchInitMidAb         &FchTaskDummy
-    #define InstallFchInitLateAb        &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_SPI_SUPPORT
-    #define BLOCK_SPI_SIZE              sizeof (FCH_SPI)
-    #define InstallFchInitResetSpi      &FchInitResetSpi
-    #define InstallFchInitEnvSpi        &FchInitEnvSpi
-    #define InstallFchInitMidSpi        &FchTaskDummy
-    #define InstallFchInitLateSpi       &FchInitLateSpi
-  #else
-    #define BLOCK_SPI_SIZE              0
-    #define InstallFchInitResetSpi      &FchTaskDummy
-    #define InstallFchInitEnvSpi        &FchTaskDummy
-    #define InstallFchInitMidSpi        &FchTaskDummy
-    #define InstallFchInitLateSpi       &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_GEC_SUPPORT
-    #define BLOCK_GEC_SIZE              sizeof (FCH_GEC)
-    #define InstallFchInitResetGec      &FchInitResetGec
-    #define InstallFchInitEnvGec        &FchInitEnvGec
-    #define InstallFchInitMidGec        &FchInitMidGec
-    #define InstallFchInitLateGec       &FchInitLateGec
-  #else
-    #define BLOCK_GEC_SIZE              0
-    #define InstallFchInitResetGec      &FchTaskDummy
-    #define InstallFchInitEnvGec        &FchTaskDummy
-    #define InstallFchInitMidGec        &FchTaskDummy
-    #define InstallFchInitLateGec       &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_SATA_SUPPORT
-    #define BLOCK_SATA_SIZE             sizeof (FCH_SATA)
-    #define InstallFchInitResetSata     &FchInitResetSata
-    #define InstallFchInitEnvSata       &FchInitEnvSata
-    #define InstallFchInitMidSata       &FchInitMidSata
-    #define InstallFchInitLateSata      &FchInitLateSata
-  #else
-    #define BLOCK_SATA_SIZE             0
-    #define InstallFchInitResetSata     &FchTaskDummy
-    #define InstallFchInitEnvSata       &FchTaskDummy
-    #define InstallFchInitMidSata       &FchTaskDummy
-    #define InstallFchInitLateSata      &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_IDE_SUPPORT
-    #define BLOCK_IDE_SIZE              sizeof (FCH_IDE)
-    #define InstallFchInitResetIde      &FchTaskDummy
-    #define InstallFchInitEnvIde        &FchInitEnvIde
-    #define InstallFchInitMidIde        &FchInitMidIde
-    #define InstallFchInitLateIde       &FchInitLateIde
-  #else
-    #define BLOCK_IDE_SIZE              0
-    #define InstallFchInitResetIde      &FchTaskDummy
-    #define InstallFchInitEnvIde        &FchTaskDummy
-    #define InstallFchInitMidIde        &FchTaskDummy
-    #define InstallFchInitLateIde       &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_LPC_SUPPORT
-    #define BLOCK_LPC_SIZE              sizeof (FCH_LPC)
-    #define InstallFchInitResetLpc      &FchInitResetLpc
-    #define InstallFchInitEnvLpc        &FchTaskDummy
-    #define InstallFchInitMidLpc        &FchTaskDummy
-    #define InstallFchInitLateLpc       &FchTaskDummy
-  #else
-    #define BLOCK_LPC_SIZE              0
-    #define InstallFchInitResetLpc      &FchTaskDummy
-    #define InstallFchInitEnvLpc        &FchTaskDummy
-    #define InstallFchInitMidLpc        &FchTaskDummy
-    #define InstallFchInitLateLpc       &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_PCIB_SUPPORT
-    #define BLOCK_PCIB_SIZE             sizeof (FCH_PCIB)
-    #define InstallFchInitResetPcib     &FchInitResetPcib
-    #define InstallFchInitEnvPcib       &FchInitEnvPcib
-    #define InstallFchInitMidPcib       &FchTaskDummy
-    #define InstallFchInitLatePcib      &FchInitLatePcib
-  #else
-    #define BLOCK_PCIB_SIZE             0
-    #define InstallFchInitResetPcib     &FchTaskDummy
-    #define InstallFchInitEnvPcib       &FchTaskDummy
-    #define InstallFchInitMidPcib       &FchTaskDummy
-    #define InstallFchInitLatePcib      &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_PCIE_SUPPORT
-    #define InstallFchInitResetPcie     &FchInitResetPcie
-    #define InstallFchInitEnvPcie       &FchInitEnvPcie
-    #define InstallFchInitMidPcie       &FchTaskDummy
-    #define InstallFchInitLatePcie      &FchInitLatePcie
-  #else
-    #define InstallFchInitResetPcie     &FchTaskDummy
-    #define InstallFchInitEnvPcie       &FchTaskDummy
-    #define InstallFchInitMidPcie       &FchTaskDummy
-    #define InstallFchInitLatePcie      &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_GPP_SUPPORT
-    #define BLOCK_GPP_SIZE              sizeof (FCH_GPP)
-    #define InstallFchInitResetGpp      &FchInitResetGpp
-    #define InstallFchInitAllinoneGPP   &FchTaskDummy
-    #define InstallFchInitEnvGpp        &FchInitEnvGpp
-    #define InstallFchInitEnvGppPhaseII &FchInitEnvGppPhaseII
-    #define InstallFchInitMidGpp        &FchTaskDummy
-    #define InstallFchInitLateGpp       &FchInitLateGpp
-    #define InstallHpSmiCallback        &FchGppHotplugSmiCallback
-  #else
-    #define BLOCK_GPP_SIZE              0
-    #define InstallFchInitResetGpp      &FchTaskDummy
-      #define InstallFchInitAllinoneGPP &FchTaskDummy
-    #define InstallFchInitEnvGpp        &FchTaskDummy
-    #define InstallFchInitEnvGppPhaseII &FchTaskDummy
-    #define InstallFchInitMidGpp        &FchTaskDummy
-    #define InstallFchInitLateGpp       &FchTaskDummy
-      #define InstallHpSmiCallback      &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_USB_SUPPORT
-    #define BLOCK_USB_SIZE              sizeof (FCH_USB)
-    #define InstallFchInitResetUsb      &FchInitResetUsb
-    #define InstallFchInitEnvUsb        &FchInitEnvUsb
-    #define InstallFchInitMidUsb        &FchInitMidUsb
-    #define InstallFchInitLateUsb       &FchInitLateUsb
-  #else
-    #define BLOCK_USB_SIZE              0
-    #define InstallFchInitResetUsb      &FchTaskDummy
-    #define InstallFchInitEnvUsb        &FchTaskDummy
-    #define InstallFchInitMidUsb        &FchTaskDummy
-    #define InstallFchInitLateUsb       &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_EHCI_SUPPORT
-    #define InstallFchInitResetUsbEhci  &FchInitResetEhci
-    #define InstallFchInitEnvUsbEhci    &FchInitEnvUsbEhci
-    #define InstallFchInitMidUsbEhci    &FchInitMidUsbEhci
-    #define InstallFchInitLateUsbEhci   &FchInitLateUsbEhci
-  #else
-    #define InstallFchInitResetUsbEhci  &FchTaskDummy
-    #define InstallFchInitEnvUsbEhci    &FchTaskDummy
-    #define InstallFchInitMidUsbEhci    &FchTaskDummy
-    #define InstallFchInitLateUsbEhci   &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_OHCI_SUPPORT
-    #define InstallFchInitResetUsbOhci  &FchInitResetOhci
-    #define InstallFchInitEnvUsbOhci    &FchInitEnvUsbOhci
-    #define InstallFchInitMidUsbOhci    &FchInitMidUsbOhci
-    #define InstallFchInitLateUsbOhci   &FchInitLateUsbOhci
-  #else
-    #define InstallFchInitResetUsbOhci  &FchTaskDummy
-    #define InstallFchInitEnvUsbOhci    &FchTaskDummy
-    #define InstallFchInitMidUsbOhci    &FchTaskDummy
-    #define InstallFchInitLateUsbOhci   &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_XHCI_SUPPORT
-    #define InstallFchInitResetUsbXhci  &FchInitResetXhci
-    #define InstallFchInitEnvUsbXhci    &FchInitEnvUsbXhci
-    #define InstallFchInitMidUsbXhci    &FchInitMidUsbXhci
-    #define InstallFchInitLateUsbXhci   &FchInitLateUsbXhci
-  #else
-    #define InstallFchInitResetUsbXhci  &FchTaskDummy
-    #define InstallFchInitEnvUsbXhci    &FchTaskDummy
-    #define InstallFchInitMidUsbXhci    &FchTaskDummy
-    #define InstallFchInitLateUsbXhci   &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_IMC_SUPPORT
-    #define BLOCK_IMC_SIZE              sizeof (FCH_IMC)
-    #define InstallFchInitResetImc      &FchInitResetImc
-    #define InstallFchInitEnvImc        &FchInitEnvImc
-    #define InstallFchInitMidImc        &FchInitMidImc
-    #define InstallFchInitLateImc       &FchInitLateImc
-  #else
-    #define BLOCK_IMC_SIZE              0
-    #define InstallFchInitResetImc      &FchTaskDummy
-    #define InstallFchInitEnvImc        &FchTaskDummy
-    #define InstallFchInitMidImc        &FchTaskDummy
-    #define InstallFchInitLateImc       &FchTaskDummy
-  #endif
-
-
-  #ifndef FCH_NO_SD_SUPPORT
-    #define BLOCK_SD_SIZE               sizeof (FCH_SD)
-    #define InstallFchInitResetSd       &FchTaskDummy
-    #define InstallFchInitEnvSd         &FchInitEnvSd
-    #define InstallFchInitMidSd         &FchTaskDummy
-    #define InstallFchInitLateSd        &FchTaskDummy
-  #else
-    #define BLOCK_SD_SIZE               0
-    #define InstallFchInitResetSd       &FchTaskDummy
-    #define InstallFchInitEnvSd         &FchTaskDummy
-    #define InstallFchInitMidSd         &FchTaskDummy
-    #define InstallFchInitLateSd        &FchTaskDummy
-  #endif
-
-    #define BLOCK_IR_SIZE               0
-    #define InstallFchInitResetIr       &FchTaskDummy
-    #define InstallFchInitEnvIr         &FchTaskDummy
-    #define InstallFchInitMidIr         &FchTaskDummy
-    #define InstallFchInitLateIr        &FchTaskDummy
-
-  #ifndef FCH_NO_AZALIA_SUPPORT
-    #define BLOCK_AZALIA_SIZE           sizeof (FCH_AZALIA)
-    #define InstallFchInitResetAzalia   &FchTaskDummy
-    #define InstallFchInitEnvAzalia     &FchInitEnvAzalia
-    #define InstallFchInitMidAzalia     &FchInitMidAzalia
-    #define InstallFchInitLateAzalia    &FchInitLateAzalia
-  #else
-    #define BLOCK_AZALIA_SIZE           0
-    #define InstallFchInitResetAzalia   &FchTaskDummy
-    #define InstallFchInitEnvAzalia     &FchTaskDummy
-    #define InstallFchInitMidAzalia     &FchTaskDummy
-    #define InstallFchInitLateAzalia    &FchTaskDummy
-  #endif
-
-  #ifndef FCH_NO_HWM_SUPPORT
-    #define BLOCK_HWM_SIZE              sizeof (FCH_HWM)
-    #define InstallFchInitResetHwm      &FchTaskDummy
-    #define InstallFchInitEnvHwm        &FchTaskDummy
-    #define InstallFchInitMidHwm        &FchTaskDummy
-    #define InstallFchInitLateHwm       &FchInitLateHwm
-  #else
-    #define InstallFchInitResetHwm      &FchTaskDummy
-    #define InstallFchInitEnvHwm        &FchTaskDummy
-    #define InstallFchInitMidHwm        &FchTaskDummy
-    #define InstallFchInitLateHwm       &FchTaskDummy
-  #endif
-
-
-  #define BLOCK_SMBUS_SIZE      sizeof (FCH_SMBUS)
-  #define BLOCK_HPET_SIZE       sizeof (FCH_HPET)
-  #define BLOCK_GCPU_SIZE       sizeof (FCH_GCPU)
-  #define BLOCK_SDB_SIZE        sizeof (FCH_SERIALDB)
-  #define BLOCK_MISC_SIZE       sizeof (FCH_MISC)
-
-
-  // Optionally declare OEM hooks after each phase
-  #ifndef FCH_INIT_RESET_HOOK
-    #define InstallFchInitResetHook     FchTaskDummy
-  #else
-    #define InstallFchInitResetHook     OemFchInitResetHook
-  #endif
-
-
-  //
-  // Define FCH build time options and configurations
-  //
-  #ifdef BLDCFG_SMBUS0_BASE_ADDRESS
-    #define CFG_SMBUS0_BASE_ADDRESS           BLDCFG_SMBUS0_BASE_ADDRESS
-  #else
-    #define CFG_SMBUS0_BASE_ADDRESS           DFLT_SMBUS0_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_SMBUS1_BASE_ADDRESS
-    #define CFG_SMBUS1_BASE_ADDRESS           BLDCFG_SMBUS1_BASE_ADDRESS
-  #else
-    #define CFG_SMBUS1_BASE_ADDRESS           DFLT_SMBUS1_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_SIO_PME_BASE_ADDRESS
-    #define CFG_SIO_PME_BASE_ADDRESS          BLDCFG_SIO_PME_BASE_ADDRESS
-  #else
-    #define CFG_SIO_PME_BASE_ADDRESS          DFLT_SIO_PME_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
-    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
-  #else
-    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
-  #endif
-  #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
-    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
-  #else
-    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
-  #endif
-  #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
-    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
-  #else
-    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
-  #endif
-  #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
-    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
-  #else
-    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
-  #endif
-  #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
-    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
-  #else
-    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       DFLT_ACPI_GPE0_BLOCK_ADDRESS
-  #endif
-
-
-  #ifdef BLDCFG_WATCHDOG_TIMER_BASE
-    #define CFG_WATCHDOG_TIMER_BASE           BLDCFG_WATCHDOG_TIMER_BASE
-  #else
-    #define CFG_WATCHDOG_TIMER_BASE           DFLT_WATCHDOG_TIMER_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
-    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       BLDCFG_ACPI_PMA_BLK_ADDRESS
-  #else
-    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       DFLT_ACPI_PMA_CNT_BLK_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
-    #define CFG_SMI_CMD_PORT_ADDRESS          BLDCFG_SMI_CMD_PORT_ADDRESS
-  #else
-    #define CFG_SMI_CMD_PORT_ADDRESS          DFLT_SMI_CMD_PORT
-  #endif
-
-  #ifdef BLDCFG_ROM_BASE_ADDRESS
-    #define CFG_SPI_ROM_BASE_ADDRESS          BLDCFG_ROM_BASE_ADDRESS
-  #else
-    #define CFG_SPI_ROM_BASE_ADDRESS          DFLT_SPI_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_GEC_SHADOW_ROM_BASE
-    #define CFG_GEC_SHADOW_ROM_BASE           BLDCFG_GEC_SHADOW_ROM_BASE
-  #else
-    #define CFG_GEC_SHADOW_ROM_BASE           DFLT_GEC_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_HPET_BASE_ADDRESS
-    #define CFG_HPET_BASE_ADDRESS           BLDCFG_HPET_BASE_ADDRESS
-  #else
-    #define CFG_HPET_BASE_ADDRESS           DFLT_HPET_BASE_ADDRESS
-  #endif
-
-  #ifdef BLDCFG_AZALIA_SSID
-    #define CFG_AZALIA_SSID                 BLDCFG_AZALIA_SSID
-  #else
-    #define CFG_AZALIA_SSID                 DFLT_AZALIA_SSID
-  #endif
-
-  #ifdef BLDCFG_SMBUS_SSID
-    #define CFG_SMBUS_SSID                  BLDCFG_SMBUS_SSID
-  #else
-    #define CFG_SMBUS_SSID                  DFLT_SMBUS_SSID
-  #endif
-
-  #ifdef BLDCFG_IDE_SSID
-    #define CFG_IDE_SSID                    BLDCFG_IDE_SSID
-  #else
-    #define CFG_IDE_SSID                    DFLT_IDE_SSID
-  #endif
-
-  #ifdef BLDCFG_SATA_AHCI_SSID
-    #define CFG_SATA_AHCI_SSID              BLDCFG_SATA_AHCI_SSID
-  #else
-    #define CFG_SATA_AHCI_SSID              DFLT_SATA_AHCI_SSID
-  #endif
-
-  #ifdef BLDCFG_SATA_IDE_SSID
-    #define CFG_SATA_IDE_SSID               BLDCFG_SATA_IDE_SSID
-  #else
-    #define CFG_SATA_IDE_SSID               DFLT_SATA_IDE_SSID
-  #endif
-
-  #ifdef BLDCFG_SATA_RAID5_SSID
-    #define CFG_SATA_RAID5_SSID             BLDCFG_SATA_RAID5_SSID
-  #else
-    #define CFG_SATA_RAID5_SSID             DFLT_SATA_RAID5_SSID
-  #endif
-
-  #ifdef BLDCFG_SATA_RAID_SSID
-    #define CFG_SATA_RAID_SSID              BLDCFG_SATA_RAID_SSID
-  #else
-    #define CFG_SATA_RAID_SSID              DFLT_SATA_RAID_SSID
-  #endif
-
-  #ifdef BLDCFG_EHCI_SSID
-    #define CFG_EHCI_SSID                   BLDCFG_EHCI_SSID
-  #else
-    #define CFG_EHCI_SSID                   DFLT_EHCI_SSID
-  #endif
-
-  #ifdef BLDCFG_OHCI_SSID
-    #define CFG_OHCI_SSID                   BLDCFG_OHCI_SSID
-  #else
-    #define CFG_OHCI_SSID                   DFLT_OHCI_SSID
-  #endif
-
-  #ifdef BLDCFG_LPC_SSID
-    #define CFG_LPC_SSID                    BLDCFG_LPC_SSID
-  #else
-    #define CFG_LPC_SSID                    DFLT_LPC_SSID
-  #endif
-
-  #ifdef BLDCFG_SD_SSID
-    #define CFG_SD_SSID                     BLDCFG_SD_SSID
-  #else
-    #define CFG_SD_SSID                     DFLT_SD_SSID
-  #endif
-
-  #ifdef BLDCFG_XHCI_SSID
-    #define CFG_XHCI_SSID                   BLDCFG_XHCI_SSID
-  #else
-    #define CFG_XHCI_SSID                   DFLT_XHCI_SSID
-  #endif
-
-  #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB
-    #define CFG_FCH_PORT80_BEHIND_PCIB      BLDCFG_FCH_PORT80_BEHIND_PCIB
-  #else
-    #define CFG_FCH_PORT80_BEHIND_PCIB      DFLT_FCH_PORT80_BEHIND_PCIB
-  #endif
-
-  #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
-    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
-  #else
-    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_LINK_CONFIG
-    #define CFG_FCH_GPP_LINK_CONFIG         BLDCFG_FCH_GPP_LINK_CONFIG
-  #else
-    #define CFG_FCH_GPP_LINK_CONFIG         DFLT_FCH_GPP_LINK_CONFIG
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
-    #define CFG_FCH_GPP_PORT0_PRESENT       BLDCFG_FCH_GPP_PORT0_PRESENT
-  #else
-    #define CFG_FCH_GPP_PORT0_PRESENT       DFLT_FCH_GPP_PORT0_PRESENT
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
-    #define CFG_FCH_GPP_PORT1_PRESENT       BLDCFG_FCH_GPP_PORT1_PRESENT
-  #else
-    #define CFG_FCH_GPP_PORT1_PRESENT       DFLT_FCH_GPP_PORT1_PRESENT
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
-    #define CFG_FCH_GPP_PORT2_PRESENT       BLDCFG_FCH_GPP_PORT2_PRESENT
-  #else
-    #define CFG_FCH_GPP_PORT2_PRESENT       DFLT_FCH_GPP_PORT2_PRESENT
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
-    #define CFG_FCH_GPP_PORT3_PRESENT       BLDCFG_FCH_GPP_PORT3_PRESENT
-  #else
-    #define CFG_FCH_GPP_PORT3_PRESENT       DFLT_FCH_GPP_PORT3_PRESENT
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
-    #define CFG_FCH_GPP_PORT0_HOTPLUG       BLDCFG_FCH_GPP_PORT0_HOTPLUG
-  #else
-    #define CFG_FCH_GPP_PORT0_HOTPLUG       DFLT_FCH_GPP_PORT0_HOTPLUG
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
-    #define CFG_FCH_GPP_PORT1_HOTPLUG       BLDCFG_FCH_GPP_PORT1_HOTPLUG
-  #else
-    #define CFG_FCH_GPP_PORT1_HOTPLUG       DFLT_FCH_GPP_PORT1_HOTPLUG
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
-    #define CFG_FCH_GPP_PORT2_HOTPLUG       BLDCFG_FCH_GPP_PORT2_HOTPLUG
-  #else
-    #define CFG_FCH_GPP_PORT2_HOTPLUG       DFLT_FCH_GPP_PORT2_HOTPLUG
-  #endif
-
-  #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
-    #define CFG_FCH_GPP_PORT3_HOTPLUG       BLDCFG_FCH_GPP_PORT3_HOTPLUG
-  #else
-    #define CFG_FCH_GPP_PORT3_HOTPLUG       DFLT_FCH_GPP_PORT3_HOTPLUG
-  #endif
-
-  #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP
-    #define CFG_FCH_ESATA_PORT_BITMAP       BLDCFG_FCH_ESATA_PORT_BITMAP
-  #else
-    #define CFG_FCH_ESATA_PORT_BITMAP       0
-  #endif
-
-  #ifdef BLDCFG_FCH_IR_PIN_CONTROL
-    #define CFG_FCH_IR_PIN_CONTROL          BLDCFG_FCH_IR_PIN_CONTROL
-  #else
-    #define CFG_FCH_IR_PIN_CONTROL          (BIT5 | BIT1 | BIT0)
-  #endif
-
-  #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL
-    #define CFG_FCH_SD_CLOCK_CONTROL        BLDCFG_FCH_SD_CLOCK_CONTROL
-  #else
-    #define CFG_FCH_SD_CLOCK_CONTROL        Sd50MhzTraceCableLengthWithinSixInches
-  #endif
-
-  #ifdef BLDCFG_FCH_SCI_MAP_LIST
-    #define CFG_FCH_SCI_MAP_LIST            BLDCFG_FCH_SCI_MAP_LIST
-  #else
-    #define CFG_FCH_SCI_MAP_LIST            NULL
-  #endif
-
-  #ifdef BLDCFG_FCH_SATA_PHY_LIST
-    #define CFG_FCH_SATA_PHY_LIST           BLDCFG_FCH_SATA_PHY_LIST
-  #else
-    #define CFG_FCH_SATA_PHY_LIST           NULL
-  #endif
-
-  #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST
-    #define CFG_FCH_GPIO_CONTROL_LIST       BLDCFG_FCH_GPIO_CONTROL_LIST
-  #else
-    #define CFG_FCH_GPIO_CONTROL_LIST       NULL
-  #endif
-
-
-  #ifdef AGESA_ENTRY_INIT_RESET
-    #if AGESA_ENTRY_INIT_RESET == TRUE
-      //
-      // Define task list for InitReset phase
-      //
-      FCH_TASK_ENTRY ROMDATA  *FchInitResetTaskTable[] = {
-        InstallFchInitResetHwAcpiP,
-        InstallFchInitResetAb,
-        InstallFchInitResetSpi,
-        InstallFchInitResetGec,
-        InstallFchInitResetHwAcpi,
-        InstallFchInitResetSata,
-        InstallFchInitResetLpc,
-        InstallFchInitResetPcib,
-        InstallFchInitResetPcie,
-        InstallFchInitResetGpp,
-        InstallFchInitAllinoneGPP,
-        InstallFchInitResetUsb,
-        InstallFchInitResetUsbEhci,
-        InstallFchInitResetUsbOhci,
-        InstallFchInitResetUsbXhci,
-        InstallFchInitResetImc,
-        NULL
-      };
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_ENV
-    #if AGESA_ENTRY_INIT_ENV == TRUE
-      //
-      // Define task list for InitEnv phase
-      //
-      FCH_TASK_ENTRY ROMDATA  *FchInitEnvTaskTable[] = {
-        InstallFchInitEnvHwAcpiP,
-        InstallFchInitEnvPcib,
-        InstallFchInitEnvPcie,
-        InstallFchInitEnvGpp,
-        InstallFchInitEnvIr,
-        InstallFchInitEnvHwAcpi,
-        InstallFchInitEnvSpi,
-        InstallFchInitEnvSd,
-        InstallFchInitEnvImc,
-        InstallFchInitEnvUsb,
-        InstallFchInitEnvUsbEhci,
-        InstallFchInitEnvUsbOhci,
-        InstallFchInitEnvUsbXhci,
-        InstallFchInitEnvSata,
-        InstallFchInitEnvIde,
-        InstallFchInitEnvGec,
-        InstallFchInitEnvAzalia,
-        InstallFchInitEnvAb,
-        InstallFchInitEnvHwm,
-        InstallFchInitEnvGppPhaseII,
-        InstallFchInitEnvAbS,
-        NULL
-      };
-    #endif
-  #endif
-
-
-  #ifdef AGESA_ENTRY_INIT_MID
-    #if AGESA_ENTRY_INIT_MID == TRUE
-      //
-      // Define task list for InitMid phase
-      //
-      FCH_TASK_ENTRY ROMDATA  *FchInitMidTaskTable[] = {
-        InstallFchInitMidImc,
-        InstallFchInitMidUsb,
-        InstallFchInitMidUsbEhci,
-        InstallFchInitMidUsbOhci,
-        InstallFchInitMidUsbXhci,
-        InstallFchInitMidSata,
-        InstallFchInitMidIde,
-        InstallFchInitMidGec,
-        InstallFchInitMidAzalia,
-        InstallFchInitMidHwm,
-        NULL
-      };
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_LATE
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      //
-      // Define task list for InitLate phase
-      //
-      FCH_TASK_ENTRY ROMDATA  *FchInitLateTaskTable[] = {
-        InstallFchInitLatePcie,
-        InstallFchInitLatePcib,
-        InstallFchInitLateSpi,
-        InstallFchInitLateUsb,
-        InstallFchInitLateUsbEhci,
-        InstallFchInitLateUsbOhci,
-        InstallFchInitLateUsbXhci,
-        InstallFchInitLateSata,
-        InstallFchInitLateIde,
-        InstallFchInitLateGec,
-        InstallFchInitLateAzalia,
-        InstallFchInitLateImc,
-        InstallFchInitLateHwm,
-        InstallFchInitLateGpp,
-        InstallFchInitLateHwAcpi,
-        NULL
-      };
-    #endif
-  #endif
-
-
-  #ifdef AGESA_ENTRY_INIT_ENV
-    #if AGESA_ENTRY_INIT_ENV == TRUE
-      //
-      // Define task list for S3 resume before PCI phase
-      //
-      FCH_TASK_ENTRY ROMDATA  *FchInitS3EarlyTaskTable[] = {
-        InstallFchInitEnvPcie,
-        InstallFchInitEnvPcib,
-        InstallFchInitEnvGpp,
-        InstallFchInitEnvIr,
-        InstallFchInitEnvHwAcpi,
-        InstallFchInitEnvSpi,
-        InstallFchInitEnvSd,
-        InstallFchInitEnvUsb,
-        InstallFchInitEnvUsbXhci,
-        InstallFchInitEnvSata,
-        InstallFchInitEnvIde,
-        InstallFchInitEnvGec,
-        InstallFchInitEnvAzalia,
-        InstallFchInitEnvAb,
-        InstallFchInitEnvGppPhaseII,
-        InstallFchInitEnvAbS,
-        NULL
-      };
-    #endif
-  #endif
-
-  #ifdef AGESA_ENTRY_INIT_LATE
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      //
-      // Define task list for S3 resume after PCI phase
-      //
-      FCH_TASK_ENTRY ROMDATA  *FchInitS3LateTaskTable[] = {
-        InstallFchInitLatePcie,
-        InstallFchInitLatePcib,
-        InstallFchInitLateSpi,
-        InstallFchInitMidUsbEhci,
-        InstallFchInitLateUsb,
-        InstallFchInitLateUsbEhci,
-        InstallFchInitLateUsbOhci,
-        InstallFchInitLateUsbXhci,
-        InstallFchInitMidSata,
-        InstallFchInitMidIde,
-        InstallFchInitMidGec,
-        InstallFchInitMidAzalia,
-        InstallFchInitLateSata,
-        InstallFchInitLateIde,
-        InstallFchInitLateHwAcpi,
-        InstallFchInitLateGpp,
-        InstallFchInitEnvHwm,
-        InstallFchInitLateGpp,
-        InstallFchInitLateHwm,
-        NULL
-      };
-    #endif
-  #endif
-  FCH_TASK_ENTRY   *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
-
-
-#else   // FCH_SUPPORT == FALSE
-  /* FCH Interface entries */
-  extern  FCH_INIT     CommonFchInitStub;
-
-  #define FP_FCH_INIT_RESET              &CommonFchInitStub
-  #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
-  #define FP_FCH_INIT_ENV                &CommonFchInitStub
-  #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
-  #define FP_FCH_INIT_MID                &CommonFchInitStub
-  #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
-  #define FP_FCH_INIT_LATE               &CommonFchInitStub
-  #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
-
-  #define CFG_SMBUS0_BASE_ADDRESS            0
-  #define CFG_SMBUS1_BASE_ADDRESS            0
-  #define CFG_SIO_PME_BASE_ADDRESS           0
-  #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0
-  #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0
-  #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS      0
-  #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0
-  #define CFG_ACPI_GPE0_BLOCK_ADDRESS        0
-  #define CFG_SPI_ROM_BASE_ADDRESS           0
-  #define CFG_WATCHDOG_TIMER_BASE            0
-  #define CFG_HPET_BASE_ADDRESS              0
-  #define CFG_SMI_CMD_PORT_ADDRESS           0
-  #define CFG_ACPI_PMA_CNTBLK_ADDRESS        0
-  #define CFG_GEC_SHADOW_ROM_BASE            0
-  #define CFG_AZALIA_SSID                    0
-  #define CFG_SMBUS_SSID                     0
-  #define CFG_IDE_SSID                       0
-  #define CFG_SATA_AHCI_SSID                 0
-  #define CFG_SATA_IDE_SSID                  0
-  #define CFG_SATA_RAID5_SSID                0
-  #define CFG_SATA_RAID_SSID                 0
-  #define CFG_EHCI_SSID                      0
-  #define CFG_OHCI_SSID                      0
-  #define CFG_LPC_SSID                       0
-  #define CFG_SD_SSID                        0
-  #define CFG_XHCI_SSID                      0
-  #define CFG_FCH_PORT80_BEHIND_PCIB         0
-  #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP     0
-  #define CFG_FCH_GPP_LINK_CONFIG            0
-  #define CFG_FCH_GPP_PORT0_PRESENT          0
-  #define CFG_FCH_GPP_PORT1_PRESENT          0
-  #define CFG_FCH_GPP_PORT2_PRESENT          0
-  #define CFG_FCH_GPP_PORT3_PRESENT          0
-  #define CFG_FCH_GPP_PORT0_HOTPLUG          0
-  #define CFG_FCH_GPP_PORT1_HOTPLUG          0
-  #define CFG_FCH_GPP_PORT2_HOTPLUG          0
-  #define CFG_FCH_GPP_PORT3_HOTPLUG          0
-
-  #define CFG_FCH_ESATA_PORT_BITMAP          0
-  #define CFG_FCH_IR_PIN_CONTROL             0
-  #define CFG_FCH_SD_CLOCK_CONTROL           0
-  #define CFG_FCH_SCI_MAP_LIST               0
-  #define CFG_FCH_SATA_PHY_LIST              0
-  #define CFG_FCH_GPIO_CONTROL_LIST          0
-
-#endif
-
-#define DFLT_RTC_WORKAROUND         FALSE
-#ifdef BLDOPT_RTC_WORKAROUND
-  #undef  CFG_FCH_RTC_WORKAROUND
-  #define CFG_FCH_RTC_WORKAROUND      BLDOPT_RTC_WORKAROUND
-#else
-  #undef  CFG_FCH_RTC_WORKAROUND
-  #define CFG_FCH_RTC_WORKAROUND      DFLT_RTC_WORKAROUND
-#endif
-
-CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
-  FP_FCH_INIT_RESET,
-  FP_FCH_INIT_RESET_CONSTRUCT,
-  FP_FCH_INIT_ENV,
-  FP_FCH_INIT_ENV_CONSTRUCT,
-  FP_FCH_INIT_MID,
-  FP_FCH_INIT_MID_CONSTRUCT,
-  FP_FCH_INIT_LATE,
-  FP_FCH_INIT_LATE_CONSTRUCT,
-};
-
-#endif  // _OPTION_FCH_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecoveryInstall.h
deleted file mode 100644
index 75ae37e184..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionGfxRecoveryInstall.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GfxRecovery
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
-#define _OPTION_GFX_RECOVERY_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-
-#endif  // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionGnbInstall.h
deleted file mode 100644
index a648cc4ec3..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionGnbInstall.h
+++ /dev/null
@@ -1,932 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GNB
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 87849 $   @e \$Date: 2013-02-11 15:37:58 -0600 (Mon, 11 Feb 2013) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_GNB_INSTALL_H_
-#define _OPTION_GNB_INSTALL_H_
-
-#include "S3SaveState.h"
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-//---------------------------------------------------------------------------------------------------
-// Family installation
-//---------------------------------------------------------------------------------------------------
-
-
-
-#define GNB_TYPE_TN   FALSE
-#define GNB_TYPE_BK   FALSE
-#define GNB_TYPE_KV   FALSE
-#define GNB_TYPE_KB   FALSE
-#define GNB_TYPE_BK   FALSE
-#define GNB_TYPE_ML   FALSE
-
-#if (OPTION_FAMILY15H_TN == TRUE)
-  #undef  GNB_TYPE_TN
-  #define GNB_TYPE_TN  TRUE
-#endif
-
-
-#if (OPTION_FAMILY16H_KB == TRUE)
-  #undef  GNB_TYPE_KB
-  #define GNB_TYPE_KB  TRUE
-#endif
-
-
-#if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE)
-//---------------------------------------------------------------------------------------------------
-// Service installation
-//---------------------------------------------------------------------------------------------------
-
-  #include "Gnb.h"
-  #include "GnbPcie.h"
-  #include "GnbGfx.h"
-
-  #define SERVICES_POINTER  NULL
-  #if (GNB_TYPE_TN == TRUE)
-    #include "GnbInitTNInstall.h"
-  #endif
-  #if (GNB_TYPE_KB == TRUE)
-    #include "GnbInitKBInstall.h"
-  #endif
-  GNB_SERVICE   *ServiceTable = SERVICES_POINTER;
-
-//---------------------------------------------------------------------------------------------------
-// BUILD options
-//---------------------------------------------------------------------------------------------------
-
-  #ifndef CFG_IGFX_AS_PCIE_EP
-    #define CFG_IGFX_AS_PCIE_EP                           TRUE
-  #endif
-
-  #ifndef CFG_LCLK_DEEP_SLEEP_EN
-    #if (GNB_TYPE_TN == TRUE)
-      #define  CFG_LCLK_DEEP_SLEEP_EN                       FALSE
-    #else
-      #define  CFG_LCLK_DEEP_SLEEP_EN                       TRUE
-    #endif
-  #endif
-
-  #ifndef CFG_LCLK_DPM_EN
-    #define CFG_LCLK_DPM_EN                                 TRUE
-  #endif
-
-  #ifndef CFG_GMC_POWER_GATING
-    #if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE))
-      #define CFG_GMC_POWER_GATING                          GmcPowerGatingWithStutter
-    #else
-      #define CFG_GMC_POWER_GATING                          GmcPowerGatingDisabled
-    #endif
-  #endif
-
-  #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
-    #if (GNB_TYPE_TN == TRUE)
-      #define  CFG_SMU_SCLK_CLOCK_GATING_ENABLE           TRUE
-    #else
-      #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE            FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
-    #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE               TRUE
-  #endif
-
-  #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
-    #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT      FALSE
-  #endif
-
-  #ifndef CFG_GNB_LOAD_REAL_FUSE
-    #define  CFG_GNB_LOAD_REAL_FUSE                       TRUE
-  #endif
-
-  #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
-    #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING  (60 * 1000)
-  #endif
-
-  #ifndef CFG_GNB_PCIE_LINK_L0_POOLING
-    #define CFG_GNB_PCIE_LINK_L0_POOLING                  (60 * 1000)
-  #endif
-
-  #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
-    #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME      (2 * 1000)
-  #endif
-
-  #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
-    #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME      (2 * 1000)
-  #endif
-
-  #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
-    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
-  #else
-    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
-  #endif
-
-  #ifndef CFG_GNB_FORCE_CABLESAFE_OFF
-    #define CFG_GNB_FORCE_CABLESAFE_OFF                   FALSE
-  #endif
-
-  #ifndef CFG_ORB_CLOCK_GATING_ENABLE
-      #define CFG_ORB_CLOCK_GATING_ENABLE                 TRUE
-  #endif
-
-  #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
-    #define CFG_GNB_PCIE_POWERGATING_FLAGS                0x0
-  #endif
-
-
-  #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
-    #if (GNB_TYPE_TN == TRUE)
-      #define  CFG_IOC_SCLK_CLOCK_GATING_ENABLE           TRUE
-    #else
-      #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE            FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
-    #if (GNB_TYPE_TN == TRUE)
-      #define  CFG_IOMMU_L1_CLOCK_GATING_ENABLE           TRUE
-    #else
-      #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE            FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
-    #if (GNB_TYPE_TN == TRUE)
-      #define  CFG_IOMMU_L2_CLOCK_GATING_ENABLE           TRUE
-    #else
-      #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE            FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_GNB_ALTVDDNB_SUPPORT
-    #define CFG_GNB_ALTVDDNB_SUPPORT                      TRUE
-  #endif
-
-  #ifndef CFG_GNB_BAPM_SUPPORT
-    #if ((GNB_TYPE_TN == TRUE) || (GNB_TYPE_KB == TRUE))
-      #define CFG_GNB_BAPM_SUPPORT                        TRUE
-    #else
-      #define CFG_GNB_BAPM_SUPPORT                        FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_GNB_LHTC_SUPPORT
-    #if (GNB_TYPE_KB == TRUE)
-      #define CFG_GNB_LHTC_SUPPORT                        TRUE
-    #else
-      #define CFG_GNB_LHTC_SUPPORT                        FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
-    #define CFG_UNUSED_SIMD_POWERGATING_ENABLE            TRUE
-  #endif
-
-  #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
-    #define CFG_UNUSED_RB_POWERGATING_ENABLE              FALSE
-  #endif
-
-  #ifndef CFG_NBDPM_ENABLE
-    #if ((GNB_TYPE_KB == TRUE))
-      #define CFG_NBDPM_ENABLE                              FALSE
-    #else
-      #define CFG_NBDPM_ENABLE                              TRUE
-    #endif
-  #endif
-
-  #ifndef CFG_MAX_PAYLOAD_ENABLE
-    #define CFG_MAX_PAYLOAD_ENABLE                        TRUE
-  #endif
-
-
-  #ifndef CFG_ORB_DYN_WAKE_ENABLE
-    #if (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      #define  CFG_ORB_DYN_WAKE_ENABLE                    TRUE
-    #else
-      #define CFG_ORB_DYN_WAKE_ENABLE                     TRUE
-    #endif
-  #endif
-
-  #ifndef CFG_LOADLINE_ENABLE
-    #define CFG_LOADLINE_ENABLE                           TRUE
-  #endif
-
-  #ifndef CFG_PCIE_PHY_ISOLATION_SUPPORT
-    #if (GNB_TYPE_KB == TRUE)
-      #define CFG_PCIE_PHY_ISOLATION_SUPPORT             TRUE
-    #else
-      #define CFG_PCIE_PHY_ISOLATION_SUPPORT             FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_SVI_REVISION
-    #if (GNB_TYPE_KB == TRUE || GNB_TYPE_TN == TRUE)
-      #define CFG_SVI_REVISION             2
-    #else
-      #define CFG_SVI_REVISION             1
-    #endif
-  #endif
-
-  #ifndef CFG_SCS_SUPPORT
-    #if ((GNB_TYPE_KB == TRUE))
-      #define CFG_SCS_SUPPORT             TRUE
-    #else
-      #define CFG_SCS_SUPPORT             FALSE
-    #endif
-  #endif
-
-  #ifndef CFG_SAMU_PATCH_ENABLED
-    #define CFG_SAMU_PATCH_ENABLED      TRUE
-  #endif
-
-  #ifndef CFG_GNB_TDC_SUPPORT
-    #define CFG_GNB_TDC_SUPPORT          TRUE
-  #endif
-  #ifndef CFG_NATIVE_GEN1_PLL_ENABLE
-    #define CFG_NATIVE_GEN1_PLL_ENABLE   TRUE
-  #endif
-
-  #ifndef CFG_UMA_STEERING
-    #define CFG_UMA_STEERING             0
-  #endif
-
-  GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
-    CFG_IGFX_AS_PCIE_EP,
-    CFG_LCLK_DEEP_SLEEP_EN,
-    CFG_LCLK_DPM_EN,
-    CFG_GMC_POWER_GATING,
-    CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
-    CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
-    CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
-    CFG_GNB_LOAD_REAL_FUSE,
-    CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
-    CFG_GNB_PCIE_LINK_L0_POOLING,
-    CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
-    CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
-    CFG_GNB_PCIE_TRAINING_ALGORITHM,
-    CFG_GNB_FORCE_CABLESAFE_OFF,
-    CFG_ORB_CLOCK_GATING_ENABLE,
-    CFG_GNB_PCIE_POWERGATING_FLAGS,
-    TRUE,
-    CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
-    CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
-    CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
-    CFG_GNB_ALTVDDNB_SUPPORT,
-    CFG_GNB_BAPM_SUPPORT,
-    CFG_UNUSED_SIMD_POWERGATING_ENABLE,
-    CFG_UNUSED_RB_POWERGATING_ENABLE,
-    CFG_NBDPM_ENABLE,
-    TRUE,
-    CFG_MAX_PAYLOAD_ENABLE,
-    CFG_ORB_DYN_WAKE_ENABLE,
-    CFG_LOADLINE_ENABLE,
-    CFG_PCIE_PHY_ISOLATION_SUPPORT,
-    CFG_GNB_LHTC_SUPPORT,
-    CFG_SVI_REVISION,
-    CFG_SCS_SUPPORT,
-    CFG_SAMU_PATCH_ENABLED,
-    {CFG_ACPI_SET_OEM_ID},
-    {CFG_ACPI_SET_OEM_TABLE_ID},
-    CFG_GNB_TDC_SUPPORT,
-    TRUE,
-    CFG_NATIVE_GEN1_PLL_ENABLE,
-    CFG_UMA_STEERING
-  };
-
-  //---------------------------------------------------------------------------------------------------
-  // SMU Firmware
-  //---------------------------------------------------------------------------------------------------
-
-
-
-  //---------------------------------------------------------------------------------------------------
-  // Module entries
-  //---------------------------------------------------------------------------------------------------
-
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_NB_EARLY_INIT
-      #define OPTION_NB_EARLY_INIT TRUE
-    #endif
-    #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbEarlyInterfaceTN;
-      #define OPTION_GNBEARLYINTERFACETN_ENTRY            {AMD_FAMILY_TN, GnbEarlyInterfaceTN, TpGnbEarlyInterface},
-    #else
-      #define OPTION_GNBEARLYINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GnbEarlyInterfaceKB;
-      #define OPTION_GNBEARLYINTERFACEKB_ENTRY            {AMD_FAMILY_KB, GnbEarlyInterfaceKB, TpGnbEarlyInterface},
-    #else
-      #define OPTION_GNBEARLYINTERFACEKB_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_CONFIG_MAP
-      #define OPTION_PCIE_CONFIG_MAP TRUE
-    #endif
-    #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                 PcieConfigurationMap;
-      #define OPTION_PCIECONFIGURATIONMAP_ENTRY          {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationMap, TpGnbPcieConfigurationMap},
-    #else
-      #define OPTION_PCIECONFIGURATIONMAP_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_EARLY_INIT
-      #define OPTION_PCIE_EARLY_INIT TRUE
-    #endif
-    #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  PcieEarlyInterfaceTN;
-      #define OPTION_PCIEEARLYINTERFACETN_ENTRY           {AMD_FAMILY_TN, PcieEarlyInterfaceTN, TpGnbPcieEarlyInterface},
-    #else
-      #define  OPTION_PCIEEARLYINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieEarlyInterfaceKB;
-      #define OPTION_PCIEEARLYINTERFACEKB_ENTRY           {AMD_FAMILY_KB, PcieEarlyInterfaceKB, TpGnbPcieEarlyInterface},
-    #else
-      #define OPTION_PCIEEARLYINTERFACEKB_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
-      OPTION_GNBEARLYINTERFACETN_ENTRY
-      OPTION_GNBEARLYINTERFACEKB_ENTRY
-      OPTION_PCIECONFIGURATIONMAP_ENTRY
-      OPTION_PCIEEARLYINTERFACETN_ENTRY
-      OPTION_PCIEEARLYINTERFACEKB_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_CONFIG_INIT
-      #define OPTION_PCIE_CONFIG_INIT TRUE
-    #endif
-    #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieConfigurationInit;
-      #define OPTION_PCIECONFIGURATIONINIT_ENTRY          {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieConfigurationInit, TpGnbEarlierPcieConfigurationInit},
-    #else
-      #define OPTION_PCIECONFIGURATIONINIT_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_NB_EARLIER_INIT
-      #define OPTION_NB_EARLIER_INIT TRUE
-    #endif
-    #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbEarlierInterfaceTN;
-      #define OPTION_GNBEARLIERINTERFACETN_ENTRY          {AMD_FAMILY_TN, GnbEarlierInterfaceTN, TpGnbEarlierInterface},
-    #else
-      #define OPTION_GNBEARLIERINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GnbEarlierInterfaceKB;
-      #define OPTION_GNBEARLIERINTERFACEKB_ENTRY          {AMD_FAMILY_KB, GnbEarlierInterfaceKB, TpGnbEarlierInterface},
-    #else
-      #define OPTION_GNBEARLIERINTERFACEKB_ENTRY
-    #endif
-
-    #if (OPTION_NB_EARLIER_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  OptionGnbInstall581;
-      #define OPTION_GNBSCSINTERFACEKB_ENTRY          {AMD_FAMILY_KB, OptionGnbInstall581, TpGnbEarlierInterface},
-    #else
-      #define OPTION_GNBSCSINTERFACEKB_ENTRY
-    #endif
-
-
-    OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
-      OPTION_PCIECONFIGURATIONINIT_ENTRY
-      OPTION_GNBEARLIERINTERFACETN_ENTRY
-      OPTION_GNBEARLIERINTERFACEKB_ENTRY
-      OPTION_GNBSCSINTERFACEKB_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-  #endif
-
-  #if (AGESA_ENTRY_INIT_POST == TRUE)
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_CONFIG_POST_INIT
-      #define OPTION_GFX_CONFIG_POST_INIT TRUE
-    #endif
-    #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxConfigPostInterface;
-      #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY         {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigPostInterface, TpGnbGfxConfigPostInterface},
-    #else
-      #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_POST_INIT
-      #define OPTION_GFX_POST_INIT TRUE
-    #endif
-    #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GfxPostInterfaceTN;
-      #define OPTION_GFXPOSTINTERFACETN_ENTRY             {AMD_FAMILY_TN, GfxPostInterfaceTN, TpGnbGfxPostInterface},
-    #else
-      #define OPTION_GFXPOSTINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxPostInterfaceKB;
-      #define OPTION_GFXPOSTINTERFACEKB_ENTRY             {AMD_FAMILY_KB, GfxPostInterfaceKB, TpGnbGfxPostInterface},
-    #else
-      #define OPTION_GFXPOSTINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_NB_POST_INIT
-      #define OPTION_NB_POST_INIT TRUE
-    #endif
-    #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbPostInterfaceTN;
-      #define OPTION_GNBPOSTINTERFACETN_ENTRY             {AMD_FAMILY_TN, GnbPostInterfaceTN, TpGnbPostInterface},
-    #else
-      #define OPTION_GNBPOSTINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GnbPostInterfaceKB;
-      #define OPTION_GNBPOSTINTERFACEKB_ENTRY             {AMD_FAMILY_KB, GnbPostInterfaceKB, TpGnbPostInterface},
-    #else
-      #define OPTION_GNBPOSTINTERFACEKB_ENTRY
-    #endif
-
-    //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_POST_EARLY_INIT
-      #define OPTION_PCIE_POST_EARLY_INIT TRUE
-    #endif
-    #if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  PciePostEarlyInterfaceTN;
-      #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY       {AMD_FAMILY_TN, PciePostEarlyInterfaceTN, TpGnbPciePostEarlyInterface},
-    #else
-      #define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_PCIE_POST_EARLY_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PciePostEarlyInterfaceKB;
-      #define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY       {AMD_FAMILY_KB, PciePostEarlyInterfaceKB, TpGnbPciePostEarlyInterface},
-    #else
-      #define OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_POST_INIT
-      #define OPTION_PCIE_POST_INIT TRUE
-    #endif
-    #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  PciePostInterfaceTN;
-      #define OPTION_PCIEPOSTINTERFACETN_ENTRY            {AMD_FAMILY_TN, PciePostInterfaceTN, TpGnbPciePostInterface},
-    #else
-      #define OPTION_PCIEPOSTINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PciePostInterfaceKB;
-      #define OPTION_PCIEPOSTINTERFACEKB_ENTRY            {AMD_FAMILY_KB, PciePostInterfaceKB, TpGnbPciePostInterface},
-    #else
-      #define OPTION_PCIEPOSTINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
-      OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
-      OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
-      OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
-      OPTION_GFXPOSTINTERFACETN_ENTRY
-      OPTION_GFXPOSTINTERFACEKB_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-
-    OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
-      OPTION_GNBPOSTINTERFACETN_ENTRY
-      OPTION_GNBPOSTINTERFACEKB_ENTRY
-      OPTION_PCIEPOSTINTERFACETN_ENTRY
-      OPTION_PCIEPOSTINTERFACEKB_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-  #endif
-
-  #if (AGESA_ENTRY_INIT_ENV == TRUE)
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_NB_ENV_INIT
-      #define OPTION_NB_ENV_INIT TRUE
-    #endif
-    #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbEnvInterfaceTN;
-      #define OPTION_GNBENVINTERFACETN_ENTRY              {AMD_FAMILY_TN, GnbEnvInterfaceTN, TpGnbEnvInterface},
-    #else
-      #define OPTION_GNBENVINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GnbEnvInterfaceKB;
-      #define OPTION_GNBENVINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GnbEnvInterfaceKB, TpGnbEnvInterface},
-    #else
-      #define OPTION_GNBENVINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_CONFIG_ENV_INIT
-      #define OPTION_GFX_CONFIG_ENV_INIT TRUE
-    #endif
-    #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                   GfxConfigEnvInterface;
-      #define OPTION_GFXCONFIGENVINTERFACE_ENTRY          {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigEnvInterface, TpGnbGfxConfigEnvInterface},
-    #else
-      #define  OPTION_GFXCONFIGENVINTERFACE_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_ENV_INIT
-      #define OPTION_GFX_ENV_INIT TRUE
-    #endif
-    #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GfxEnvInterfaceTN;
-      #define OPTION_GFXENVINTERFACETN_ENTRY              {AMD_FAMILY_TN, GfxEnvInterfaceTN, TpGnbGfxEnvInterface},
-    #else
-      #define OPTION_GFXENVINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxEnvInterfaceKB;
-      #define OPTION_GFXENVINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GfxEnvInterfaceKB, TpGnbGfxEnvInterface},
-    #else
-      #define OPTION_GFXENVINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_ENV_INIT
-      #define OPTION_PCIE_ENV_INIT TRUE
-    #endif
-    #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE PcieEnvInterfaceTN;
-      #define OPTION_PCIEENVINTERFACETN_ENTRY             {AMD_FAMILY_TN, PcieEnvInterfaceTN, TpGnbPcieEnvInterface},
-    #else
-      #define OPTION_PCIEENVINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieEnvInterfaceKB;
-      #define OPTION_PCIEENVINTERFACEKB_ENTRY             {AMD_FAMILY_KB, PcieEnvInterfaceKB, TpGnbPcieEnvInterface},
-    #else
-      #define OPTION_PCIEENVINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-
-    OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
-      OPTION_GNBENVINTERFACETN_ENTRY
-      OPTION_GNBENVINTERFACEKB_ENTRY
-      OPTION_PCIEENVINTERFACETN_ENTRY
-      OPTION_PCIEENVINTERFACEKB_ENTRY
-      OPTION_GFXCONFIGENVINTERFACE_ENTRY
-      OPTION_GFXENVINTERFACETN_ENTRY
-      OPTION_GFXENVINTERFACEKB_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-  #endif
-
-  #if (AGESA_ENTRY_INIT_MID == TRUE)
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_MID_INIT
-      #define OPTION_GFX_MID_INIT TRUE
-    #endif
-    #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GfxMidInterfaceTN;
-      #define OPTION_GFXMIDINTERFACETN_ENTRY              {AMD_FAMILY_TN, GfxMidInterfaceTN, TpGnbGfxMidInterface},
-    #else
-      #define OPTION_GFXMIDINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxMidInterfaceKB;
-      #define OPTION_GFXMIDINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GfxMidInterfaceKB, TpGnbGfxMidInterface},
-    #else
-      #define OPTION_GFXMIDINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
-      #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
-    #endif
-    #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GfxIntInfoTableInterfaceTN;
-      #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY     {AMD_FAMILY_TN, GfxIntInfoTableInterfaceTN},
-    #else
-      #define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxIntInfoTableInterfaceKB;
-      #define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY     {AMD_FAMILY_KB, GfxIntInfoTableInterfaceKB},
-    #else
-      #define OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIe_MID_INIT
-      #define OPTION_PCIe_MID_INIT TRUE
-    #endif
-    #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  PcieMidInterfaceTN;
-      #define OPTION_PCIEMIDINTERFACETN_ENTRY             {AMD_FAMILY_TN, PcieMidInterfaceTN, TpPcieMidInterface},
-    #else
-      #define OPTION_PCIEMIDINTERFACETN_ENTRY
-    #endif
-    #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieMidInterfaceKB;
-      #define OPTION_PCIEMIDINTERFACEKB_ENTRY             {AMD_FAMILY_KB, PcieMidInterfaceKB, TpPcieMidInterface},
-    #else
-      #define OPTION_PCIEMIDINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_NB_MID_INIT
-      #define OPTION_NB_MID_INIT TRUE
-    #endif
-    #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbMidInterfaceTN;
-      #define OPTION_GNBMIDINTERFACETN_ENTRY              {AMD_FAMILY_TN, GnbMidInterfaceTN, TpGnbMidInterface},
-    #else
-      #define OPTION_GNBMIDINTERFACETN_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_CONFIG_POST_INIT
-      #define OPTION_GFX_CONFIG_POST_INIT TRUE
-    #endif
-    #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxConfigMidInterface;
-      #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY         {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxConfigMidInterface, TpGnbGfxConfigMidInterface},
-    #else
-      #define OPTION_GFXCONFIGMIDINTERFACE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GnbMidInterfaceKB;
-      #define OPTION_GNBMIDINTERFACEKB_ENTRY              {AMD_FAMILY_KB, GnbMidInterfaceKB, TpGnbMidInterface},
-    #else
-      #define OPTION_GNBMIDINTERFACEKB_ENTRY
-    #endif
-
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_MAXPAYLOAD_INTERFACE
-      #define OPTION_PCIE_MAXPAYLOAD_INTERFACE TRUE
-    #endif
-    #if (OPTION_PCIE_MAXPAYLOAD_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieMaxPayloadInterface;
-      #define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY        {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieMaxPayloadInterface, TpGnbPcieMaxPayloadInterface},
-    #else
-      #define OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_CLK_PM_INTERFACE
-      #define OPTION_PCIE_CLK_PM_INTERFACE FALSE
-      #if (GNB_TYPE_TN == TRUE  &&  (OPTION_FS1_SOCKET_SUPPORT == TRUE || OPTION_FP1_SOCKET_SUPPORT == TRUE))
-        #undef  OPTION_PCIE_CLK_PM_INTERFACE
-        #define OPTION_PCIE_CLK_PM_INTERFACE TRUE
-      #endif
-      #if (GNB_TYPE_KB == TRUE)
-        #undef  OPTION_PCIE_CLK_PM_INTERFACE
-        #define OPTION_PCIE_CLK_PM_INTERFACE TRUE
-      #endif
-    #endif
-
-    #if (OPTION_PCIE_CLK_PM_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieClkPmInterface;
-      #define OPTION_PCIECLKPMINTERFACE_ENTRY             {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieClkPmInterface, TpGnbPcieClkPmInterface},
-    #else
-      #define OPTION_PCIECLKPMINTERFACE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_PCIE_ASPM_INTERFACE
-      #define OPTION_PCIE_ASPM_INTERFACE TRUE
-    #endif
-    #if (OPTION_PCIE_ASPM_INTERFACE == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  PcieAspmInterface;
-      #define OPTION_PCIEASPMINTERFACE_ENTRY              {AMD_FAMILY_TN | AMD_FAMILY_KB, PcieAspmInterface, TpGnbPcieAspmInterface},
-    #else
-      #define OPTION_PCIEASPMINTERFACE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GNB_IOAPIC_INTERFACE
-      #define OPTION_GNB_IOAPIC_INTERFACE TRUE
-    #endif
-    #if (OPTION_GNB_IOAPIC_INTERFACE == TRUE) && (GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GnbNbIoapicInterface;
-      #define OPTION_GNBNBIOAPICINTERFACE_ENTRY          {AMD_FAMILY_KB, GnbNbIoapicInterface, TpGnbNbIoapicInterface},
-    #else
-      #define OPTION_GNBNBIOAPICINTERFACE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
-      OPTION_GFXCONFIGMIDINTERFACE_ENTRY
-      OPTION_GFXMIDINTERFACETN_ENTRY
-      OPTION_GFXMIDINTERFACEKB_ENTRY
-      OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
-      OPTION_GFXINTINFOTABLEINTERFACEKB_ENTRY
-      OPTION_PCIEMIDINTERFACETN_ENTRY
-      OPTION_PCIEMIDINTERFACEKB_ENTRY
-      OPTION_GNBMIDINTERFACETN_ENTRY
-      OPTION_GNBMIDINTERFACEKB_ENTRY
-      OPTION_PCIEMAXPAYLOADINTERFACE_ENTRY
-      OPTION_PCIECLKPMINTERFACE_ENTRY
-      OPTION_PCIEASPMINTERFACE_ENTRY
-      OPTION_GNBNBIOAPICINTERFACE_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-  #endif
-
-  #if (AGESA_ENTRY_INIT_LATE == TRUE)
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_ALIB
-      #define OPTION_ALIB FALSE
-    #endif
-    #if (OPTION_ALIB == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      #define ALIB_CALL_TABLE
-      #define ALIB_CALL_TABLEV2
-      #if (GNB_TYPE_TN == TRUE)
-        #if ((OPTION_FM2_SOCKET_SUPPORT == TRUE) || (OPTION_FM2r2_SOCKET_SUPPORT == TRUE))
-          extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
-          extern F_ALIB_GET PcieAlibGetBaseTableTNFM2;
-          F_ALIB_GET  *AlibGetBaseTable = PcieAlibGetBaseTableTNFM2;
-          #undef ALIB_CALL_TABLE
-          #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo,
-        #else
-          extern F_ALIB_UPDATE PcieAlibUpdatePcieMmioInfo;
-          extern F_ALIB_GET PcieAlibGetBaseTableTNFS1;
-          F_ALIB_GET  *AlibGetBaseTable = PcieAlibGetBaseTableTNFS1;
-          extern F_ALIB_UPDATE PcieAlibUpdateVoltageInfo;
-          extern F_ALIB_UPDATE PcieAlibUpdatePcieInfo;
-          #undef ALIB_CALL_TABLE
-          #define ALIB_CALL_TABLE PcieAlibUpdatePcieMmioInfo, \
-                                  PcieAlibUpdateVoltageInfo, \
-                                  PcieAlibUpdatePcieInfo,
-
-        #endif
-      #endif
-
-
-      #if (GNB_TYPE_KB == TRUE)
-        extern F_ALIB_GET PcieAlibGetBaseTableKB;
-        F_ALIB_GET  *AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
-        extern F_ALIB_UPDATE PcieAlibUpdateVoltageData;
-        extern F_ALIB_UPDATE PcieAlibUpdatePcieData;
-        #undef ALIB_CALL_TABLEV2
-        #define ALIB_CALL_TABLEV2 PcieAlibUpdateVoltageData, \
-                                  PcieAlibUpdatePcieData,
-      #endif
-
-
-      F_ALIB_UPDATE* AlibDispatchTable [] = {
-        ALIB_CALL_TABLE
-        NULL
-      };
-      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
-        ALIB_CALL_TABLEV2
-        NULL
-      };
-      #if (GNB_TYPE_TN == TRUE)
-        OPTION_GNB_FEATURE                                  PcieAlibFeature;
-        #define OPTION_PCIEALIBFEATURE_ENTRY                {AMD_FAMILY_TN, PcieAlibFeature, TpGnbPcieAlibFeature},
-      #endif
-      #if ((GNB_TYPE_KB == TRUE))
-        OPTION_GNB_FEATURE                                  PcieAlibV2Feature;
-        #define OPTION_PCIEALIBV2FEATURE_ENTRY              {AMD_FAMILY_KB, PcieAlibV2Feature, TpGnbPcieAlibFeature},
-      #endif
-    #else
-      F_ALIB_GET  *AlibGetBaseTable = NULL;
-      F_ALIB_GET  *AlibGetBaseTableV2 = NULL;
-      F_ALIB_UPDATE* AlibDispatchTable [] = {
-        NULL
-      };
-      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
-        NULL
-      };
-      #define OPTION_PCIEALIBFEATURE_ENTRY
-      #define OPTION_PCIEALIBV2FEATURE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_IOMMU_ACPI_IVRS
-      #if (CFG_IOMMU_SUPPORT == TRUE)
-        #define OPTION_IOMMU_ACPI_IVRS TRUE
-      #else
-        #define OPTION_IOMMU_ACPI_IVRS FALSE
-      #endif
-    #endif
-    #if (OPTION_IOMMU_ACPI_IVRS == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbIommuIvrsTable;
-      #define OPTIONIOMMUACPIIVRSLATE_ENTRY               {AMD_FAMILY_TN, GnbIommuIvrsTable},
-    #else
-      #define OPTIONIOMMUACPIIVRSLATE_ENTRY
-    #endif
-    #if (CFG_IOMMU_SUPPORT == TRUE) && (GNB_TYPE_TN == TRUE)
-      OPTION_GNB_FEATURE                                  GnbIommuScratchMemoryRangeInterface;
-      #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY          {AMD_FAMILY_TN, GnbIommuScratchMemoryRangeInterface, TpGnbIommuIvrsTable},
-    #else
-      #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
-    #endif
-  //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
-      #if (GNB_TYPE_TN == TRUE)
-        OPTION_PCIEALIBFEATURE_ENTRY
-      #endif
-      #if ((GNB_TYPE_KB == TRUE))
-        OPTION_PCIEALIBV2FEATURE_ENTRY
-      #endif
-      OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
-      OPTIONIOMMUACPIIVRSLATE_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-  #endif
-
-  #if (AGESA_ENTRY_INIT_S3SAVE == TRUE)
-  //---------------------------------------------------------------------------------------------------
-    #ifndef OPTION_GFX_INIT_SVIEW
-      #define OPTION_GFX_INIT_SVIEW TRUE
-    #endif
-    #if (OPTION_GFX_INIT_SVIEW == TRUE) && (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-      OPTION_GNB_FEATURE                                  GfxInitSview;
-      #define OPTION_GFXINITSVIEW_ENTRY                   {AMD_FAMILY_TN | AMD_FAMILY_KB, GfxInitSview},
-    #else
-      #define OPTION_GFXINITSVIEW_ENTRY
-    #endif
-
-    OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[] = {
-      OPTION_GFXINITSVIEW_ENTRY
-      {0, NULL, EndGnbTestPoints}
-    };
-  #endif
-
-  #if  (GNB_TYPE_TN == TRUE || GNB_TYPE_KB == TRUE)
-    #define GNBS3RESTOREV4
-    #define GNBS3RESTOREV7
-    #if (GNB_TYPE_TN == TRUE)
-      S3_DISPATCH_FUNCTION  GnbSmuServiceRequestV4S3Script;
-      #undef  GNBS3RESTOREV4
-      #define GNBS3RESTOREV4 {GnbSmuServiceRequestV4S3Script_ID, GnbSmuServiceRequestV4S3Script},
-    #endif
-    #if (GNB_TYPE_KB == TRUE)
-      S3_DISPATCH_FUNCTION  GnbSmuServiceRequestV7S3Script;
-      #undef  GNBS3RESTOREV7
-      #define GNBS3RESTOREV7 {GnbSmuServiceRequestV7S3Script_ID, GnbSmuServiceRequestV7S3Script},
-    #endif
-    S3_DISPATCH_FUNCTION  GnbLibStallS3Script;
-    #define PCIELATERESTORETN
-    #define PCIELATERESTOREKB
-    #define GFXSCLKRESTORETN
-    #if (GNB_TYPE_TN == TRUE)
-      S3_DISPATCH_FUNCTION  PcieLateRestoreInitTNS3Script;
-      S3_DISPATCH_FUNCTION  GfxRequestSclkTNS3Script;
-      #undef  PCIELATERESTORETN
-      #define PCIELATERESTORETN {PcieLateRestoreTNS3Script_ID, PcieLateRestoreInitTNS3Script},
-      #undef  GFXSCLKRESTORETN
-      #define GFXSCLKRESTORETN  {GfxRequestSclkTNS3Script_ID,  GfxRequestSclkTNS3Script     },
-    #endif
-    #if (GNB_TYPE_KB == TRUE)
-      S3_DISPATCH_FUNCTION  PcieLateRestoreInitKBS3Script;
-      #undef  PCIELATERESTOREKB
-      #define PCIELATERESTOREKB {PcieLateRestoreKBS3Script_ID, PcieLateRestoreInitKBS3Script},
-    #endif
-    #define GNB_S3_DISPATCH_FUNCTION_TABLE \
-    GNBS3RESTOREV4      \
-    GNBS3RESTOREV7      \
-    PCIELATERESTORETN \
-    GFXSCLKRESTORETN  \
-    PCIELATERESTOREKB \
-    {GnbLibStallS3Script_ID, GnbLibStallS3Script},
-
-
-
-#endif
-
-#endif
-#endif  // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionHtInstall.h
deleted file mode 100644
index 06c5463e28..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionHtInstall.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Ht
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84154 $   @e \$Date: 2012-12-12 17:02:37 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_HT_INSTALL_H_
-#define _OPTION_HT_INSTALL_H_
-
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htTopologies.h"
-/*
- * Advanced Option only, hardware socket naming is the preferred method.
- */
-#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
-  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
-#else
-  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
-#endif
-
-/*
- * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
- */
-#ifndef OPTION_IS_RECOVERY_HT
-  #define OPTION_IS_RECOVERY_HT TRUE
-#endif
-
-/*
- * Macros will generate the correct item reference based on options
- */
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  // Select the interface and features
-  #if ((OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY16H_KB == TRUE))
-    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-    #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
-    #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
-  #endif
-  // Select Northbridge components
-  #if OPTION_FAMILY15H == TRUE
-    #if OPTION_FAMILY15H_TN == TRUE
-      #define INTERNAL_HT_OPTION_FAM15TN_NB     &HtFam15Mod1xNb,
-    #else
-      #define INTERNAL_HT_OPTION_FAM15TN_NB
-    #endif
-  #else
-    #define INTERNAL_HT_OPTION_FAM15TN_NB
-  #endif
-
-  #if OPTION_FAMILY16H == TRUE
-    #if OPTION_FAMILY16H_KB == TRUE
-      #define INTERNAL_HT_OPTION_FAM16KB_NB     &HtFam16Nb,
-    #else
-      #define INTERNAL_HT_OPTION_FAM16KB_NB
-    #endif
-  #else
-    #define INTERNAL_HT_OPTION_FAM16KB_NB
-  #endif
-
-  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
-  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
-    #undef INTERNAL_ONLY_NB_LIST_ITEM
-    #define INTERNAL_ONLY_NB_LIST_ITEM
-  #endif
-
-  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
-   * is ok to have a comma because the final item (NULL) is added below.
-   */
-  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
-                                             INTERNAL_ONLY_NB_LIST_ITEM \
-                                             INTERNAL_HT_OPTION_FAM15TN_NB \
-                                             INTERNAL_HT_OPTION_FAM16KB_NB
-
-
-
-
-#else
-  // Not Init Early
-  #define INTERNAL_HT_OPTION_FEATURES     NULL
-  #define INTERNAL_HT_OPTION_INTERFACE    NULL
-  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
-  #define HT_OPTIONS_PLATFORM             NULL
-  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-#endif
-
-#ifdef AGESA_ENTRY_INIT_EARLY
-  #if AGESA_ENTRY_INIT_EARLY == TRUE
-
-    extern HT_FEATURES HtFeaturesDefault;
-    extern HT_FEATURES HtFeaturesCoherentOnly;
-    extern HT_FEATURES HtFeaturesNone;
-    extern HT_INTERFACE HtInterfaceDefault;
-    extern HT_INTERFACE HtInterfaceCoherentOnly;
-    extern HT_INTERFACE HtInterfaceMapsOnly;
-    extern HT_INTERFACE HtInterfaceNone;
-    extern NORTHBRIDGE HtFam15Mod4xNb;
-    extern NORTHBRIDGE HtFam15Mod1xNb;
-    extern NORTHBRIDGE HtFam16Nb;
-
-    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
-      INTERNAL_HT_OPTION_SUPPORTED_NBS
-      NULL
-    };
-
-    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
-    {
-      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
-      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
-      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
-      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
-      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
-      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
-      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
-      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
-      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
-      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
-    };
-    #ifndef HT_OPTIONS_PLATFORM
-      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
-    #endif
-
-    /**
-     * A list of all the supported topologies.
-     *
-     */
-    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
-      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
-      {
-        amdHtTopologySingleNode,
-        amdHtTopologyDualNode,
-        amdHtTopologyThreeLine,
-        amdHtTopologyTriangle,
-        amdHtTopologyFourLine,
-        amdHtTopologyFourStar,
-        amdHtTopologyFourDegenerate,
-        amdHtTopologyFourSquare,
-        amdHtTopologyFourKite,
-        amdHtTopologyFourFully,
-        amdHtTopologyFiveFully,
-        amdHtTopologyFiveTwistedLadder,
-        amdHtTopologySixFully,
-        amdHtTopologySixDoubloonLower,
-        amdHtTopologySixDoubloonUpper,
-        amdHtTopologySixTwistedLadder,
-        amdHtTopologySevenFully,
-        amdHtTopologySevenTwistedLadder,
-        amdHtTopologyEightFully,
-        amdHtTopologyEightDoubloon,
-        amdHtTopologyEightTwistedLadder,
-        amdHtTopologyEightStraightLadder,
-        amdHtTopologySixTwinTriangles,
-        amdHtTopologyEightTwinFullyFourWays,
-        NULL
-      };
-      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
-    #endif
-
-    /**
-     * Declare the instance of the Ht option configuration structure
-     */
-    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
-      OPTION_IS_RECOVERY_HT,
-      CFG_SET_HTCRC_SYNC_FLOOD,
-      CFG_USE_UNIT_ID_CLUMPING,
-      HT_OPTIONS_PLATFORM,
-      INTERNAL_HT_OPTION_INTERFACE,
-      INTERNAL_HT_OPTION_FEATURES,
-      &HtInstalledFamilyNorthbridgeList,
-      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
-    };
-
-  #endif
-#endif
-
-#ifndef OPTION_HT_INIIT_RESET_ENTRY
-
-  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
-  #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
-
-  #if ((OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY16H == TRUE))
-    #undef OPTION_HT_INIIT_RESET_ENTRY
-    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
-    #define OPTION_HT_INIIT_RESET_ENTRY NULL
-    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
-  #endif
-
-#endif
-
-#ifdef AGESA_ENTRY_INIT_RESET
-  #if AGESA_ENTRY_INIT_RESET == TRUE
-
-    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
-      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
-      0                                            // Unused by options
-    };
-
-    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
-      OPTION_HT_INIIT_RESET_ENTRY,
-      OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
-    };
-  #endif
-
-#endif
-
-#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionHtcInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionHtcInstall.h
deleted file mode 100644
index 8f5079cb56..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionHtcInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Hardware Thermal Control (HTC).
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_HTC_INSTALL_H_
-#define _OPTION_HTC_INSTALL_H_
-
-#include "cpuHtc.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_HTC_FEAT
-#define F15_TN_HTC_SUPPORT
-#define F16_KB_HTC_SUPPORT
-
-#if OPTION_CPU_HTC == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_TN == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
-          #undef OPTION_CPU_HTC_FEAT
-          #define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
-          extern CONST HTC_FAMILY_SERVICES ROMDATA F15TnHtcSupport;
-          #undef F15_TN_HTC_SUPPORT
-          #define F15_TN_HTC_SUPPORT {AMD_FAMILY_15_TN, &F15TnHtcSupport},
-        #endif
-      #endif
-    #endif
-
-    // Family 16h
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtc;
-          #undef OPTION_CPU_HTC_FEAT
-          #define OPTION_CPU_HTC_FEAT &CpuFeatureHtc,
-          extern CONST HTC_FAMILY_SERVICES ROMDATA F16KbHtcSupport;
-          #undef F16_KB_HTC_SUPPORT
-          #define F16_KB_HTC_SUPPORT {AMD_FAMILY_16_KB, &F16KbHtcSupport},
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtcFamilyServiceArray[] =
-{
-  F15_TN_HTC_SUPPORT
-  F16_KB_HTC_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtcFamilyServiceTable =
-{
-  (sizeof (HtcFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &HtcFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_HTC_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
deleted file mode 100644
index fe875004a2..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionIdsInstall.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * IDS Option Install File
- *
- * This file generates the defaults tables for family 10h model 5 processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-#ifndef _OPTION_IDS_INSTALL_H_
-#define _OPTION_IDS_INSTALL_H_
-#include "Ids.h"
-#include "IdsHt.h"
-#include "IdsLib.h"
-#include "IdsDebugPrint.h"
-#ifdef __IDS_EXTENDED__
-  #include OPTION_IDS_EXT_INSTALL_FILE
-#endif
-
-#define IDS_LATE_RUN_AP_TASK
-
-#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (IDSOPT_CONTROL_ENABLED == TRUE)
-    // Check for all families which include HT Features.To add new family support replace FALSE
-    #if (FALSE) && (AGESA_ENTRY_INIT_POST == TRUE)
-      #undef M_HTIDS_PORT_OVERRIDE_HOOK
-      #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
-    #endif
-  #endif
-#endif // OPTION_IDS_LEVEL
-CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
-
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if (AGESA_ENTRY_INIT_LATE == TRUE)
-    #undef IDS_LATE_RUN_AP_TASK
-    #define IDS_LATE_RUN_AP_TASK  {IDS_LATE_RUN_AP_TASK_ID, (IMAGE_ENTRY)AmdIdsRunApTaskLate},
-  #endif
-#endif // OPTION_IDS_LEVEL
-
-#if (IDSOPT_TRACING_ENABLED == TRUE)
-  #if (AGESA_ENTRY_INIT_POST == TRUE)
-    #include <mu.h>
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
-      { (UINTN) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
-      { (UINTN) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
-    };
-  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-    #include <mru.h>
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINTN) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
-      { (UINTN) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
-      { (UINTN) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
-    };
-  #else
-    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-      { (UINTN) CommonReturnFalse, "DefRet()"},
-      { (UINTN) CommonReturnFalse,  "DefRet()"},
-      { (UINTN) CommonReturnFalse,    "DefRet()"}
-    };
-  #endif
-#else
-  CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
-    { (UINTN) CommonReturnFalse, "DefRet()"},
-    { (UINTN) CommonReturnFalse,  "DefRet()"},
-    { (UINTN) CommonReturnFalse,    "DefRet()"}
-  };
-#endif
-
-
-#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
-#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
-#if (IDSOPT_IDS_ENABLED == TRUE)
-  #if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
-       ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
-        (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
-        (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
-    #if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
-      #define OPTION_IDS_NV_TO_CMOS_COMMON
-
-      //Family 15h TN
-      #ifdef OPTION_FAMILY15H_TN
-        #if OPTION_FAMILY15H_TN == TRUE
-          #define OPTION_IDS_NV_TO_CMOS_F15_TN\
-            {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
-        #endif
-      #endif
-
-      #ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
-        #define OPTION_IDS_NV_TO_CMOS_F15_TN
-      #endif
-
-
-      //Family 16h KB
-      #ifdef OPTION_FAMILY16H_KB
-        #if OPTION_FAMILY16H_KB == TRUE
-          #define OPTION_IDS_NV_TO_CMOS_F16_KB\
-            {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
-        #endif
-      #endif
-
-      #ifndef OPTION_IDS_NV_TO_CMOS_F16_KB
-        #define OPTION_IDS_NV_TO_CMOS_F16_KB
-      #endif
-
-      #ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
-        #define OPTION_IDS_NV_TO_CMOS_EXTEND
-      #endif
-
-      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
-        OPTION_IDS_NV_TO_CMOS_COMMON
-        OPTION_IDS_NV_TO_CMOS_F15_TN
-        OPTION_IDS_NV_TO_CMOS_F16_KB
-        OPTION_IDS_NV_TO_CMOS_EXTEND
-        OPTION_IDS_NV_TO_CMOS_END
-      };
-    #else
-      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
-        OPTION_IDS_NV_TO_CMOS_END
-      };
-    #endif
-  #else
-    IDS_NV_TO_CMOS gIdsNVToCmos[] = {
-      OPTION_IDS_NV_TO_CMOS_END
-    };
-  #endif
-#else
-  IDS_NV_TO_CMOS gIdsNVToCmos[] = {
-    OPTION_IDS_NV_TO_CMOS_END
-  };
-#endif
-
-///Ids Feat Options
-#if ((IDSOPT_IDS_ENABLED == TRUE) && \
-     ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
-      (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
-      (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
-  #if (IDSOPT_CONTROL_ENABLED == TRUE)
-    #ifndef OPTION_IDS_EXTEND_FEATS
-      #define OPTION_IDS_EXTEND_FEATS
-    #endif
-
-    #define OPTION_IDS_FEAT_ECCCTRL
-
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
-                OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN \
-                OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
-
-
-    #define OPTION_IDS_FEAT_CPB_CTRL
-
-    #define OPTION_IDS_FEAT_HTC_CTRL\
-                OPTION_IDS_FEAT_HTC_CTRL_F15_TN \
-                OPTION_IDS_FEAT_HTC_CTRL_F16_KB
-
-
-    #define OPTION_IDS_FEAT_MEMORY_MAPPING\
-                OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN \
-                OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
-
-
-    #define OPTION_IDS_FEAT_HT_ASSIST
-
-/*----------------------------------------------------------------------------
- *                        Family 15 TN feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
-    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
-    #ifdef OPTION_FAMILY15H_TN
-      #if OPTION_FAMILY15H_TN == TRUE
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
-        #undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
-        #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
-                    &IdsFeatHtcControlBlockF15Tn,
-
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
-        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
-        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
-        &IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
-        &IdsFeatMemoryMappingChIntlvBlockF15Tn,
-
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
-        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
-        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
-      #endif
-    #endif
-
-
-/*----------------------------------------------------------------------------
- *                        Family 16 KB feat blocks
- *
- *----------------------------------------------------------------------------
- */
-    #define OPTION_IDS_FEAT_HTC_CTRL_F16_KB
-    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
-    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
-    #ifdef OPTION_FAMILY16H_KB
-      #if OPTION_FAMILY16H_KB == TRUE
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF16Kb;
-        #undef OPTION_IDS_FEAT_HTC_CTRL_F16_KB
-        #define OPTION_IDS_FEAT_HTC_CTRL_F16_KB\
-                    &IdsFeatHtcControlBlockF16Kb,
-
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF16Kb;
-        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB
-        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F16_KB\
-        &IdsFeatMemoryMappingPostBeforeBlockF16Kb,
-
-        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF16Kb;
-        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB
-        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF16KB &IdsFeatGnbPlatformCfgBlockF16Kb,
-      #endif
-    #endif
-
-    #define OPTION_IDS_FEAT_NV_TO_CMOS
-    #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
-      #undef OPTION_IDS_FEAT_NV_TO_CMOS
-      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
-      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
-      #define OPTION_IDS_FEAT_NV_TO_CMOS\
-        &IdsFeatNvToCmosSaveBlock, \
-        &IdsFeatNvToCmosRestoreBlock,
-
-    #endif
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
-    {
-      IDS_FEAT_UCODE_UPDATE,
-      IDS_ALL_CORES,
-      IDS_UCODE,
-      IDS_FAMILY_ALL,
-      IdsSubUCode
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
-    {
-      IDS_FEAT_POWER_POLICY,
-      IDS_ALL_CORES,
-      IDS_PLATFORMCFG_OVERRIDE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerPolicyOverride
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
-    {
-      IDS_FEAT_TARGET_PSTATE,
-      IDS_BSP_ONLY,
-      IDS_INIT_LATE_AFTER,
-      IDS_FAMILY_ALL,
-      IdsSubTargetPstate
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
-    {
-      IDS_FEAT_POSTPSTATE,
-      IDS_ALL_CORES,
-      IDS_CPU_Early_Override,
-      IDS_FAMILY_ALL,
-      IdsSubPostPState
-    };
-
-    //Dram controller Features
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
-    {
-      IDS_FEAT_DCT_ALLMEMCLK,
-      IDS_BSP_ONLY,
-      IDS_ALL_MEMORY_CLOCK,
-      IDS_FAMILY_ALL,
-      IdsSubAllMemClkEn
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
-    {
-      IDS_FEAT_DCT_GANGMODE,
-      IDS_BSP_ONLY,
-      IDS_GANGING_MODE,
-      IDS_FAMILY_ALL,
-      IdsSubGangingMode
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
-    {
-      IDS_FEAT_DCT_POWERDOWN,
-      IDS_BSP_ONLY,
-      IDS_INIT_POST_BEFORE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerDownCtrl
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
-    {
-      IDS_FEAT_DCT_POWERDOWN,
-      IDS_BSP_ONLY,
-      IDS_POWERDOWN_MODE,
-      IDS_FAMILY_ALL,
-      IdsSubPowerDownMode
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
-    {
-      IDS_FEAT_HDTOUT,
-      IDS_BSP_ONLY,
-      IDS_INIT_EARLY_BEFORE,
-      IDS_FAMILY_ALL,
-      IdsSubHdtOut
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
-    {
-      IDS_FEAT_HT_SETTING,
-      IDS_BSP_ONLY,
-      IDS_HT_CONTROL,
-      IDS_FAMILY_ALL,
-      IdsSubHtLinkControl
-    };
-
-    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
-    {
-      &IdsFeatUcodeBlock,
-      &IdsFeatPowerPolicyBlock,
-
-      &IdsFeatTargetPstateBlock,
-
-      &IdsFeatPostPstateBlock,
-
-      OPTION_IDS_FEAT_NV_TO_CMOS
-
-      OPTION_IDS_FEAT_ECCCTRL
-
-      &IdsFeatDctAllMemClkBlock,
-
-      &IdsFeatDctGangModeBlock,
-
-      &IdsFeatDctPowerDownCtrlBlock,
-
-      &IdsFeatDctPowerDownModeBlock,
-
-      &IdsFeatDctPowerDownModeBlock,
-
-      OPTION_IDS_FEAT_HT_ASSIST
-
-      &IdsFeatHdtOutBlock,
-
-      &IdsFeatHtSettingBlock,
-
-      OPTION_IDS_FEAT_GNB_PLATFORMCFG
-
-      OPTION_IDS_FEAT_CPB_CTRL
-
-      OPTION_IDS_FEAT_HTC_CTRL
-
-      OPTION_IDS_FEAT_MEMORY_MAPPING
-
-      OPTION_IDS_EXTEND_FEATS
-
-      NULL
-    };
-  #else
-    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
-    {
-      NULL
-    };
-  #endif//IDSOPT_CONTROL_ENABLED
-
-  #define OPTION_IDS_FAM_REGACC_F15TN
-  #ifdef OPTION_FAMILY15H_TN
-    #if OPTION_FAMILY15H_TN == TRUE
-      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
-      #undef OPTION_IDS_FAM_REGACC_F15TN
-      #define OPTION_IDS_FAM_REGACC_F15TN \
-                &IdsFeatRegGmmxF15Tn,
-    #endif
-  #endif
-
-
-  #define OPTION_IDS_FAM_REGACC_F16KB
-  #ifdef OPTION_FAMILY16H_KB
-    #if OPTION_FAMILY16H_KB == TRUE
-      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF16Kb;
-      #undef OPTION_IDS_FAM_REGACC_F16KB
-      #define OPTION_IDS_FAM_REGACC_F16KB \
-                &IdsFeatRegGmmxF16Kb,
-    #endif
-  #endif
-
-  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
-  {
-    OPTION_IDS_FAM_REGACC_F15TN
-    OPTION_IDS_FAM_REGACC_F16KB
-    NULL
-  };
-
-/*----------------------------------------------------------------------------
- *                        IDS TRACING SERVICES
- *
- *----------------------------------------------------------------------------
- */
-  #if IDSOPT_TRACING_ENABLED == TRUE
-    #define IDS_TRACING_CONSOLE_HDTOUT
-    #define IDS_TRACING_CONSOLE_SERIALPORT
-    #define IDS_TRACING_CONSOLE_REDIRECT_IO
-    #define IDS_TRACING_CONSOLE_RAM
-
-    #ifdef IDSOPT_TRACING_CONSOLE_HDTOUT
-      #if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
-        #undef IDS_TRACING_CONSOLE_HDTOUT
-        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintHdtoutInstance;
-        #define IDS_TRACING_CONSOLE_HDTOUT &IdsDebugPrintHdtoutInstance,
-      #endif
-    #endif
-
-    #ifdef IDSOPT_TRACING_CONSOLE_SERIALPORT
-      #if IDSOPT_TRACING_CONSOLE_SERIALPORT == TRUE
-        #undef IDS_TRACING_CONSOLE_SERIALPORT
-        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintSerialInstance;
-        #define IDS_TRACING_CONSOLE_SERIALPORT &IdsDebugPrintSerialInstance,
-      #endif
-    #endif
-
-    #ifdef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
-      #if IDSOPT_TRACING_CONSOLE_REDIRECT_IO == TRUE
-        #undef IDS_TRACING_CONSOLE_REDIRECT_IO
-        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRedirectIoInstance;
-        #define IDS_TRACING_CONSOLE_REDIRECT_IO &IdsDebugPrintRedirectIoInstance,
-      #endif
-    #endif
-
-    #ifdef IDSOPT_TRACING_CONSOLE_RAM
-      #if IDSOPT_TRACING_CONSOLE_RAM == TRUE
-        #undef IDS_TRACING_CONSOLE_RAM
-        extern CONST IDS_DEBUG_PRINT ROMDATA IdsDebugPrintRamInstance;
-        #define IDS_TRACING_CONSOLE_RAM &IdsDebugPrintRamInstance,
-      #endif
-    #endif
-
-
-    CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
-    {
-      IDS_TRACING_CONSOLE_SERIALPORT
-      IDS_TRACING_CONSOLE_HDTOUT
-      IDS_TRACING_CONSOLE_REDIRECT_IO
-      IDS_TRACING_CONSOLE_RAM
-      NULL
-    };
-  #else
-    CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
-    {
-      NULL
-    };
-  #endif
-
-#else
-  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsControlFeats[] =
-  {
-    NULL
-  };
-
-  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
-  {
-    NULL
-  };
-
-  CONST IDS_DEBUG_PRINT* ROMDATA IdsDebugPrint[] =
-  {
-    NULL
-  };
-#endif// IDSOPT_IDS_ENABLED
-
-#endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionIoCstateInstall.h
deleted file mode 100644
index e466c9ebe9..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionIoCstateInstall.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: IO C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_IO_CSTATE_INSTALL_H_
-#define _OPTION_IO_CSTATE_INSTALL_H_
-
-#include "cpuIoCstate.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define OPTION_IO_CSTATE_FEAT
-#define F15_TN_IO_CSTATE_SUPPORT
-#define F16_KB_IO_CSTATE_SUPPORT
-
-#if OPTION_IO_CSTATE == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_TN == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15TnIoCstateSupport;
-          #undef F15_TN_IO_CSTATE_SUPPORT
-          #define F15_TN_IO_CSTATE_SUPPORT {AMD_FAMILY_15_TN, &F15TnIoCstateSupport},
-        #endif
-
-      #endif
-    #endif
-
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
-          #undef OPTION_IO_CSTATE_FEAT
-          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
-          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F16KbIoCstateSupport;
-          #undef F16_KB_IO_CSTATE_SUPPORT
-          #define F16_KB_IO_CSTATE_SUPPORT {AMD_FAMILY_16_KB, &F16KbIoCstateSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
-{
-  F15_TN_IO_CSTATE_SUPPORT
-  F16_KB_IO_CSTATE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
-{
-  (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &IoCstateFamilyServiceArray[0]
-};
-
-#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
deleted file mode 100644
index 3323fea953..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: L3 Dependent Features
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_L3_FEATURES_INSTALL_H_
-#define _OPTION_L3_FEATURES_INSTALL_H_
-
-#include "cpuL3Features.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_L3_FEAT
-#define L3_FEAT_AP_DISABLE_CACHE
-#define L3_FEAT_AP_ENABLE_CACHE
-
-#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE)
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
-
-    #undef L3_FEAT_AP_DISABLE_CACHE
-    #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
-    #undef L3_FEAT_AP_ENABLE_CACHE
-    #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
-{
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
-{
-  (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &L3FeatureFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_L3_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionLowPwrPstateInstall.h
deleted file mode 100644
index 3834bd4d7c..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionLowPwrPstateInstall.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
-#define F15_OR_LOW_PWR_PSTATE_SUPPORT
-
-
-#endif  // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
deleted file mode 100644
index e2d4e03bf9..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
+++ /dev/null
@@ -1,1643 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 85859 $   @e \$Date: 2013-01-14 02:57:14 -0600 (Mon, 14 Jan 2013) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_MEMORY_INSTALL_H_
-#define _OPTION_MEMORY_INSTALL_H_
-
-/* Memory Includes */
-#include "OptionMemory.h"
-
-/*-------------------------------------------------------------------------------
- *  This option file is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-/*----------------------------------------------------------------------------------
- * FEATURE BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-BOOLEAN MemFDefRet (
-  IN OUT   MEM_NB_BLOCK *NBPtr
-  )
-{
-  return FALSE;
-}
-
-BOOLEAN MemMDefRet (
-  IN   MEM_MAIN_DATA_BLOCK *MMPtr
-  )
-{
-  return TRUE;
-}
-
-BOOLEAN MemMDefRetFalse (
-  IN   MEM_MAIN_DATA_BLOCK *MMPtr
-  )
-{
-  return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *   This function initializes the northbridge block for dimm identification translator
- *
- *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
- *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
- *     @param[in,out]   NodeID   - ID of current node to construct
- *     @return          TRUE     - This is the correct constructor for the targeted node.
- *     @return          FALSE    - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN MemNIdentifyDimmConstructorRetDef (
-  IN OUT   MEM_NB_BLOCK *NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  return FALSE;
-}
-/*----------------------------------------------------------------------------------
- * TABLE FEATURE BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-UINT8 MemFTableDefRet (
-  IN OUT   MEM_TABLE_ALIAS **MTPtr
-  )
-{
-  return 0;
-}
-/*----------------------------------------------------------------------------------
- * FEATURE S3 BLOCK FUNCTIONS
- *
- *  This section defines function names that depend upon options that are selected
- *  in the platform solution install file.
- */
-BOOLEAN MemFS3DefConstructorRet (
-  IN OUT   VOID *S3NBPtr,
-  IN OUT   MEM_DATA_STRUCT *MemPtr,
-  IN       UINT8 NodeID
-  )
-{
-  return FALSE;
-}
-
-#if (OPTION_MEMCTLR_TN == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) || ((AGESA_ENTRY_INIT_POST) && (OPTION_S3_MEM_SUPPORT == TRUE)))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockTN;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemS3ResumeConstructNBBlockTN
-      #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-        extern OPTION_MEM_FEATURE_MAIN MemMS3Save;
-        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMS3Save
-      #else
-        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
-      #endif
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet
-      #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet
-    #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorTN;
-    #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorTN
-  #else
-    #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-
-#if (OPTION_MEMCTLR_KB == TRUE)
-  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) || ((AGESA_ENTRY_INIT_POST) && (OPTION_S3_MEM_SUPPORT == TRUE)))
-    #if (OPTION_S3_MEM_SUPPORT == TRUE)
-      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockKB;
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB MemS3ResumeConstructNBBlockKB
-      #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-        extern OPTION_MEM_FEATURE_MAIN MemMS3Save;
-        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMS3Save
-      #else
-        #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
-      #endif
-    #else
-      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB MemFS3DefConstructorRet
-      #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
-    #endif
-  #else
-    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB MemFS3DefConstructorRet
-    #define MEM_MAIN_FEATURE_MEM_S3_SAVE MemMDefRet
-  #endif
-  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
-    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorKB;
-    #define MEM_IDENDIMM_KB MemNIdentifyDimmConstructorKB
-  #else
-    #define MEM_IDENDIMM_KB MemNIdentifyDimmConstructorRetDef
-  #endif
-#endif
-
-
-
-/*----------------------------------------------------------------------------------
- * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
- *
- *----------------------------------------------------------------------------------
-*/
-#define MEM_NB_SUPPORT_TN
-#define MEM_NB_SUPPORT_KB
-#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-  /*----------------------------------------------------------------------------------
-   * FLOW CONTROL FUNCTION
-   *
-   *  This section selects the function that controls the memory initialization sequence
-   *  based upon the number of processor families that the BIOS will support.
-   */
-  extern MEM_FLOW_CFG MemMFlowDef;
-
-  #if (OPTION_MEMCTLR_TN == TRUE)
-    extern MEM_FLOW_CFG MemMFlowTN;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowTN,
-  #else
-    #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowDef,
-  #endif
-
-
-  #if (OPTION_MEMCTLR_KB == TRUE)
-    extern MEM_FLOW_CFG MemMFlowKB;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_KB MemMFlowKB,
-  #else
-    extern MEM_FLOW_CFG MemMFlowDef;
-    #define MEM_MAIN_FLOW_CONTROL_PTR_KB MemMFlowDef,
-  #endif
-
-
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
-    MEM_MAIN_FLOW_CONTROL_PTR_TN
-    MEM_MAIN_FLOW_CONTROL_PTR_KB
-    NULL
-  };
-
-  #if (OPTION_ONLINE_SPARE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
-    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
-    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
-    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
-  #else
-    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
-    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
-  #endif
-
-  #if (OPTION_MEM_RESTORE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
-    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
-    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
-    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
-  #else
-    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
-    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
-  #endif
-
-  #if (OPTION_BANK_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
-    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
-    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
-    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
-  #else
-    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
-    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
-  #endif
-
-  #if (OPTION_NODE_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
-    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
-    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
-    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
-    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
-  #else
-    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
-    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
-    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
-  #endif
-
-  #if (OPTION_DCT_INTERLEAVE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
-    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
-  #else
-    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
-  #endif
-
-  #if (OPTION_ECC == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
-    #define MEM_MAIN_FEATURE_ECC  MemMEcc
-    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
-    extern OPTION_MEM_FEATURE_NB MemFInitECC;
-    #define MEM_FEATURE_CK_ECC   MemFCheckECC
-    #define MEM_FEATURE_ECC   MemFInitECC
-    #define MEM_FEATURE_ECCX8  MemMDefRet
-  #else
-    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
-    #define MEM_FEATURE_CK_ECC   MemFDefRet
-    #define MEM_FEATURE_ECC   MemFDefRet
-    #define MEM_FEATURE_ECCX8  MemMDefRet
-  #endif
-
-  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
-  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
-
-  #if (OPTION_AGGRESSOR == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMAggressor;
-    #define MEM_MAIN_FEATURE_AGGRESSOR  MemMAggressor
-    extern OPTION_MEM_FEATURE_NB MemFAggressorInit;
-    #define MEM_FEATURE_AGGRESSOR  MemFAggressorInit
-  #else //#if (OPTION_AGGRESSOR == FALSE)
-    #define MEM_MAIN_FEATURE_AGGRESSOR  MemMDefRet
-    #define MEM_FEATURE_AGGRESSOR  MemFDefRet
-  #endif
-
-  #if (OPTION_DMI == TRUE)
-    #if (OPTION_DDR3 == TRUE)
-      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
-      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
-    #else
-      #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
-    #endif
-  #else
-    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
-  #endif
-
-  #if (OPTION_CRAT == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemFCratSupport;
-    #define MEM_MAIN_FEATURE_MEM_CRAT MemFCratSupport
-  #else
-    #define MEM_MAIN_FEATURE_MEM_CRAT MemMDefRet
-  #endif
-
-  #if (OPTION_DDR3 == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
-    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
-    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
-    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
-    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
-    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
-  #else
-    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
-    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
-    #define MEM_FEATURE_LVDDR3 MemFDefRet
-  #endif
-
-  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
-  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
-
-  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
-  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
-
-  #if (OPTION_PARALLEL_TRAINING == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
-    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
-  #else
-    #ifndef EXTERN_MEMMSTANDARDTRAINING
-    #define EXTERN_MEMMSTANDARDTRAINING
-        extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-    #endif
-    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-  #endif
-
-  #if (OPTION_DIMM_EXCLUDE == TRUE)
-    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
-    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
-    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
-    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
-  #else
-    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
-    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
-  #endif
-
-  #if (OPTION_AMP == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFAMP;
-    #define MEM_FEATURE_AMP  MemFAMP
-  #else
-    #define MEM_FEATURE_AMP  MemFDefRet
-  #endif
-
-  #if (OPTION_DATA_EYE == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemF2DDataEyeInit;
-    #define MEM_FEATURE_DATA_EYE  MemF2DDataEyeInit
-  #else //#if (OPTION_DATA_EYE == FALSE)
-    #define MEM_FEATURE_DATA_EYE  MemFDefRet
-  #endif
-
-  /*----------------------------------------------------------------------------------
-   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
-   *
-   *----------------------------------------------------------------------------------
-  */
-  #if OPTION_DDR2 == TRUE
-    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
-    #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
-    #if (OPTION_HW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitHw;
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
-    #else
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
-    #endif
-    #if (OPTION_SW_DRAM_INIT == TRUE)
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-    #else
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-#endif
-  #else
-    #define MEM_TECH_CONSTRUCTOR_DDR2
-  #endif
-  #if OPTION_DDR3 == TRUE
-    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
-    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
-    #if (OPTION_HW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitHw;
-      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
-    #else
-      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
-    #endif
-    #if (OPTION_SW_DRAM_INIT == TRUE)
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
-    #else
-      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
-    #endif
-  #else
-    #define MEM_TECH_CONSTRUCTOR_DDR3
-  #endif
-
-  /*---------------------------------------------------------------------------------------------------
-   * FEATURE BLOCKS
-   *
-   *  This section instantiates a feature block structure for each memory controller installed
-   *  by the platform solution install file.
-   *---------------------------------------------------------------------------------------------------
-   */
-
-
-  /*---------------------------------------------------------------------------------------------------
-   * TRINITY FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_TN == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_MAIN_FEATURE_LVDDR3
-      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
-      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #if (OPTION_EARLY_SAMPLES == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportTN;
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportTN
-    #else
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
-    #endif
-
-    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
-    #else
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemFDefRet
-    #endif
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    #if (OPTION_RDDQS_2D_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies;
-      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTrainingUsingAdjacentDies
-    #else
-      extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-    #endif
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockTN = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MEM_FEATURE_ONLINE_SPARE,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MemFDefRet,
-      MemFDefRet,
-      MEM_FEATURE_CHANNEL_INTERLEAVE,
-      MEM_FEATURE_REGION_INTERLEAVE,
-      MEM_FEATURE_CK_ECC,
-      MEM_FEATURE_ECC,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MEM_EARLY_SAMPLE_SUPPORT,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN,
-      MEM_FEATURE_AMP,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet
-    };
-
-    #undef MEM_NB_SUPPORT_TN
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockTN;
-    extern MEM_INITIALIZER MemNInitDefaultsTN;
-    #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockTN, MemNInitDefaultsTN, &MemFeatBlockTN, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN },
-  #endif // OPTION_MEMCTRL_TN
-
-
-  /*---------------------------------------------------------------------------------------------------
-   * KABINI FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_KB == TRUE)
-    #if OPTION_DDR2
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
-    #endif
-    #if OPTION_DDR3
-      #undef MEM_MAIN_FEATURE_LVDDR3
-      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
-      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
-      #undef MEM_TECH_FEATURE_DRAMINIT
-      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
-    #endif
-
-    #if (OPTION_EARLY_SAMPLES == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportKB;
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportKB
-    #else
-      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
-    #endif
-
-    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
-    #else
-      #undef MEM_TECH_FEATURE_CPG
-      #define MEM_TECH_FEATURE_CPG    MemFDefRet
-    #endif
-
-    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
-    #else
-      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
-      #undef MEM_TECH_FEATURE_HWRXEN
-      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
-    #endif
-
-
-    #undef MEM_MAIN_FEATURE_TRAINING
-    #undef MEM_FEATURE_TRAINING
-    #if (OPTION_RDDQS_2D_TRAINING == TRUE)
-      extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies;
-      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTrainingUsingAdjacentDies
-      extern OPTION_MEM_FEATURE_NB MemFRdWr2DTrainingInitKB;
-      #define MEM_FEATURE_RDWR_2D_TRAINING MemFRdWr2DTrainingInitKB
-    #else
-      #ifndef EXTERN_MEMMSTANDARDTRAINING
-      #define EXTERN_MEMMSTANDARDTRAINING
-        extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
-      #endif
-      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
-      #define MEM_FEATURE_RDWR_2D_TRAINING MemFDefRet
-    #endif
-    extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
-    #define MEM_FEATURE_TRAINING  MemFStandardTraining
-
-    MEM_FEAT_BLOCK_NB  MemFeatBlockKB = {
-      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
-      MEM_FEATURE_ONLINE_SPARE,
-      MEM_FEATURE_BANK_INTERLEAVE,
-      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MemFDefRet,
-      MEM_FEATURE_CK_ECC,
-      MEM_FEATURE_ECC,
-      MEM_FEATURE_TRAINING,
-      MEM_FEATURE_LVDDR3,
-      MEM_FEATURE_ONDIMMTHERMAL,
-      MEM_TECH_FEATURE_DRAMINIT,
-      MEM_FEATURE_DIMM_EXCLUDE,
-      MEM_EARLY_SAMPLE_SUPPORT,
-      MEM_TECH_FEATURE_CPG,
-      MEM_TECH_FEATURE_HWRXEN,
-      MemFDefRet,
-      MemFDefRet,
-      MEM_FEATURE_RDWR_2D_TRAINING,
-      MemFDefRet
-    };
-
-    #undef MEM_NB_SUPPORT_KB
-    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockKB;
-    extern MEM_INITIALIZER MemNInitDefaultsKB;
-    #define MEM_NB_SUPPORT_KB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockKB, MemNInitDefaultsKB, &MemFeatBlockKB, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB, MEM_IDENDIMM_KB },
-  #endif // OPTION_MEMCTRL_KB
-
-
-  /*---------------------------------------------------------------------------------------------------
-   * MAIN FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
-    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
-    MEM_MAIN_FEATURE_TRAINING,
-    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
-    MEM_MAIN_FEATURE_ONLINE_SPARE,
-    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
-    MEM_MAIN_FEATURE_ECC,
-    MEM_MAIN_FEATURE_MEM_CLEAR,
-    MEM_MAIN_FEATURE_MEM_DMI,
-    MEM_MAIN_FEATURE_MEM_CRAT,
-    MEM_MAIN_FEATURE_LVDDR3,
-    MEM_MAIN_FEATURE_UMAALLOC,
-    MEM_MAIN_FEATURE_MEM_SAVE,
-    MEM_MAIN_FEATURE_MEM_RESTORE,
-    MEM_MAIN_FEATURE_MEM_S3_SAVE,
-    MEM_MAIN_FEATURE_AGGRESSOR
-  };
-
-
-  /*---------------------------------------------------------------------------------------------------
-   * Technology Training SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
-
-  #if OPTION_MEMCTLR_TN
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceTN;
-    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
-          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
-          extern MEM_TECH_FEAT MemNRdPosTrnTN;
-          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemNRdPosTrnTN
-        #else
-          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
-          #else
-            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
-          #endif
-        #endif
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
-        #else
-          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
-        #endif
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_RDDQS_2D_TRAINING == TRUE)
-        #undef TECH_TRAIN_DQS_2D_DDR3
-        #define TECH_TRAIN_DQS_2D_DDR3    MemTAmdRdDqs2DTraining
-      #else
-        #undef TECH_TRAIN_DQS_2D_DDR3
-        #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3TN = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
-        TECH_TRAIN_DQS_2D_DDR3
-      };
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceTN, &memTechTrainingFeatSequenceDDR3TN },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-
-  #if OPTION_MEMCTLR_KB
-    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceKB;
-    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
-    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
-    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
-    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #if OPTION_DDR3
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
-      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
-        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
-      #else
-        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
-        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
-        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
-        #endif
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
-        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
-          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
-          extern MEM_TECH_FEAT MemNRdPosTrnKB;
-          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemNRdPosTrnKB
-        #else
-          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
-          #else
-            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
-          #endif
-        #endif
-      #else
-        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
-        #else
-          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
-        #endif
-      #endif
-      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
-      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
-      #else
-        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
-      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
-      #else
-        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
-      #else
-        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #endif
-      #if (OPTION_RDDQS_2D_TRAINING == TRUE)
-        extern  MEM_TECH_FEAT MemFAmdRdDqs2DTraining;
-        #undef TECH_TRAIN_DQS_2D_DDR3
-        #define TECH_TRAIN_DQS_2D_DDR3    MemFAmdRdDqs2DTraining
-      #else
-        #undef TECH_TRAIN_DQS_2D_DDR3
-        #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
-      #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3KB = {
-        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
-        TECH_TRAIN_ENTER_HW_TRN_DDR3,
-        TECH_TRAIN_SW_WL_DDR3,
-        TECH_TRAIN_HW_WL_P1_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_HW_WL_P2_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
-        TECH_TRAIN_EXIT_HW_TRN_DDR3,
-        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
-        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
-        TECH_TRAIN_MAX_RD_LAT_DDR3,
-        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
-        TECH_TRAIN_DQS_2D_DDR3
-      };
-      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceKB, &memTechTrainingFeatSequenceDDR3KB },
-    #else
-      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
-      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
-      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
-      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
-      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
-      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
-      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
-      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #endif
-  #else
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
-  #endif
-
-
-
-  #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
-  };
-
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB
-    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * NB TRAINING FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
-    NB_TRAIN_FLOW_DDR2,
-    NB_TRAIN_FLOW_DDR3,
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
-    MEM_TECH_CONSTRUCTOR_DDR2
-    MEM_TECH_CONSTRUCTOR_DDR3
-    NULL
-  };
-   /*---------------------------------------------------------------------------------------------------
-   * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  /*---------------------------------------------------------------------------------------------------
-   * PLATFORM-SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
-    NULL
-  };
-  CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
-
-  /*---------------------------------------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_PSC_FLOW_BLOCK_END NULL
-  #define PSC_TBL_END NULL
-  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
-  #define PSC_TBL_TN_UDIMM3_S2D_FM2
-  #define PSC_TBL_TN_SODIMM3_S2D_FS1
-  #define PSC_TBL_TN_SODIMM3_S2D_FP2
-  #define PSC_TBL_TN_SODIMM3_S2D_FM2
-  #if OPTION_MEMCTLR_TN
-    #if OPTION_FS1_SOCKET_SUPPORT
-      extern PSC_TBL_ENTRY TNClkDisMapEntSOFS1;
-      #define PSC_TBL_TN_CLK_DIS_FS1 &TNClkDisMapEntSOFS1,
-      extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFS1;
-      #define PSC_TBL_TN_ODT_TRI_FS1 &TNSODdr3ODTTriEntFS1,
-      extern PSC_TBL_ENTRY TNSODdr3CSTriEntFS1;
-      #define PSC_TBL_TN_CS_TRI_FS1 &TNSODdr3CSTriEntFS1,
-    #endif
-    #if (OPTION_FM2_SOCKET_SUPPORT || OPTION_FM2r2_SOCKET_SUPPORT)
-      extern PSC_TBL_ENTRY TNClkDisMapEntUFM2;
-      #define PSC_TBL_TN_CLK_DIS_FM2 &TNClkDisMapEntUFM2,
-      extern PSC_TBL_ENTRY TNUDdr3ODTTriEntFM2;
-      #define PSC_TBL_TN_ODT_TRI_FM2 &TNUDdr3ODTTriEntFM2,
-      extern PSC_TBL_ENTRY TNUDdr3CSTriEntFM2;
-      #define PSC_TBL_TN_CS_TRI_FM2 &TNUDdr3CSTriEntFM2,
-    #endif
-    #if OPTION_FP2_SOCKET_SUPPORT
-      extern PSC_TBL_ENTRY TNClkDisMapEntSOFP2;
-      #define PSC_TBL_TN_CLK_DIS_FP2 &TNClkDisMapEntSOFP2,
-      extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFP2;
-      #define PSC_TBL_TN_ODT_TRI_FP2 &TNSODdr3ODTTriEntFP2,
-      extern PSC_TBL_ENTRY TNSODdr3CSTriEntFP2;
-      #define PSC_TBL_TN_CS_TRI_FP2 &TNSODdr3CSTriEntFP2,
-    #endif
-    #if OPTION_UDIMMS
-      extern PSC_TBL_ENTRY TNMaxFreqTblEntU;
-      #define PSC_TBL_TN_UDIMM3_MAX_FREQ  &TNMaxFreqTblEntU,
-      extern PSC_TBL_ENTRY RLMaxFreqTblEntU;
-      #define PSC_TBL_RL_UDIMM3_MAX_FREQ  &RLMaxFreqTblEntU,
-      extern PSC_TBL_ENTRY TNDramTermTblEntU;
-      #define PSC_TBL_TN_UDIMM3_DRAM_TERM  &TNDramTermTblEntU,
-      extern PSC_TBL_ENTRY TNSAOTblEntU3;
-      #define PSC_TBL_TN_UDIMM3_SAO  &TNSAOTblEntU3,
-      #if (OPTION_FM2_SOCKET_SUPPORT || OPTION_FM2r2_SOCKET_SUPPORT)
-        extern PSC_TBL_ENTRY TNMaxFreqTblEntUFM2;
-        #define PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2  &TNMaxFreqTblEntUFM2,
-        extern PSC_TBL_ENTRY RLMaxFreqTblEntUFM2;
-        #define PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2  &RLMaxFreqTblEntUFM2,
-        #undef PSC_TBL_TN_UDIMM3_S2D_FM2
-        extern PSC_TBL_ENTRY S2DTblEntUFM2;
-        #define PSC_TBL_TN_UDIMM3_S2D_FM2  &S2DTblEntUFM2,
-      #endif
-    #endif
-    #if OPTION_SODIMMS
-      extern PSC_TBL_ENTRY TNSAOTblEntSO3;
-      #define PSC_TBL_TN_SODIMM3_SAO  &TNSAOTblEntSO3,
-      extern PSC_TBL_ENTRY TNDramTermTblEntSO;
-      #define PSC_TBL_TN_SODIMM3_DRAM_TERM  &TNDramTermTblEntSO,
-      #if OPTION_FS1_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY TNMaxFreqTblEntSOFS1;
-        #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1  &TNMaxFreqTblEntSOFS1,
-        #undef PSC_TBL_TN_SODIMM3_S2D_FS1
-        #define PSC_TBL_TN_SODIMM3_S2D_FS1
-      #endif
-      #if (OPTION_FM2_SOCKET_SUPPORT || OPTION_FM2r2_SOCKET_SUPPORT)
-        extern PSC_TBL_ENTRY TNMaxFreqTblEntSO;
-        #define PSC_TBL_TN_SODIMM3_MAX_FREQ  &TNMaxFreqTblEntSO,
-        #undef PSC_TBL_TN_SODIMM3_S2D_FM2
-        extern PSC_TBL_ENTRY S2DTblEntUFM2;
-        #define PSC_TBL_TN_SODIMM3_S2D_FM2 &S2DTblEntUFM2,
-      #endif
-      #if OPTION_FP2_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY TNSAOTblEntSODWNSO3;
-        #define PSC_TBL_TN_SODWN_SODIMM3_SAO  &TNSAOTblEntSODWNSO3,
-        extern PSC_TBL_ENTRY TNDramTermTblEntSODWNSO;
-        #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM  &TNDramTermTblEntSODWNSO,
-        extern PSC_TBL_ENTRY TNMaxFreqTblEntSODWNSO;
-        #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ  &TNMaxFreqTblEntSODWNSO,
-        extern PSC_TBL_ENTRY TNMaxFreqTblEntSOFP2;
-        #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2  &TNMaxFreqTblEntSOFP2,
-        extern PSC_TBL_ENTRY RLMaxFreqTblEntSOFP2;
-        #define PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2  &RLMaxFreqTblEntSOFP2,
-        #undef PSC_TBL_TN_SODIMM3_S2D_FP2
-        #define PSC_TBL_TN_SODIMM3_S2D_FP2
-      #endif
-    #endif
-    extern PSC_TBL_ENTRY TNMR0WrTblEntry;
-    extern PSC_TBL_ENTRY TNMR0CLTblEntry;
-    extern PSC_TBL_ENTRY TNDdr3CKETriEnt;
-    extern PSC_TBL_ENTRY TNOdtPatTblEnt;
-
-
-    #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ
-      #define PSC_TBL_TN_SODIMM3_MAX_FREQ
-    #endif
-    #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
-      #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
-    #endif
-    #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
-      #define PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
-    #endif
-    #ifndef PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
-      #define PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
-    #endif
-    #ifndef PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ
-      #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ
-    #endif
-    #ifndef PSC_TBL_TN_UDIMM3_MAX_FREQ
-      #define PSC_TBL_TN_UDIMM3_MAX_FREQ
-    #endif
-    #ifndef PSC_TBL_RL_UDIMM3_MAX_FREQ
-      #define PSC_TBL_RL_UDIMM3_MAX_FREQ
-    #endif
-    #ifndef PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2
-      #define PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2
-    #endif
-    #ifndef PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2
-      #define PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2
-    #endif
-    #ifndef PSC_TBL_TN_UDIMM3_DRAM_TERM
-      #define PSC_TBL_TN_UDIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_TBL_TN_SODIMM3_DRAM_TERM
-      #define PSC_TBL_TN_SODIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
-      #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_TBL_TN_SODIMM3_SAO
-      #define PSC_TBL_TN_SODIMM3_SAO
-    #endif
-    #ifndef PSC_TBL_TN_SODWN_SODIMM3_SAO
-      #define PSC_TBL_TN_SODWN_SODIMM3_SAO
-    #endif
-    #ifndef PSC_TBL_TN_UDIMM3_SAO
-      #define PSC_TBL_TN_UDIMM3_SAO
-    #endif
-    #ifndef PSC_TBL_TN_CLK_DIS_FM2
-      #define PSC_TBL_TN_CLK_DIS_FM2
-    #endif
-    #ifndef PSC_TBL_TN_ODT_TRI_FM2
-      #define PSC_TBL_TN_ODT_TRI_FM2
-    #endif
-    #ifndef PSC_TBL_TN_CS_TRI_FM2
-      #define PSC_TBL_TN_CS_TRI_FM2
-    #endif
-    #ifndef PSC_TBL_TN_CLK_DIS_FS1
-      #define PSC_TBL_TN_CLK_DIS_FS1
-    #endif
-    #ifndef PSC_TBL_TN_ODT_TRI_FS1
-      #define PSC_TBL_TN_ODT_TRI_FS1
-    #endif
-    #ifndef PSC_TBL_TN_CS_TRI_FS1
-      #define PSC_TBL_TN_CS_TRI_FS1
-    #endif
-    #ifndef PSC_TBL_TN_CLK_DIS_FP2
-      #define PSC_TBL_TN_CLK_DIS_FP2
-    #endif
-    #ifndef PSC_TBL_TN_ODT_TRI_FP2
-      #define PSC_TBL_TN_ODT_TRI_FP2
-    #endif
-    #ifndef PSC_TBL_TN_CS_TRI_FP2
-      #define PSC_TBL_TN_CS_TRI_FP2
-    #endif
-
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayTN[] = {
-      PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
-      PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
-      PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
-      PSC_TBL_TN_SODIMM3_MAX_FREQ
-      PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ
-      PSC_TBL_TN_UDIMM3_MAX_FREQ_FM2
-      PSC_TBL_RL_UDIMM3_MAX_FREQ_FM2
-      PSC_TBL_TN_UDIMM3_MAX_FREQ
-      PSC_TBL_RL_UDIMM3_MAX_FREQ
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayTN[] = {
-      PSC_TBL_TN_UDIMM3_DRAM_TERM
-      PSC_TBL_TN_SODIMM3_DRAM_TERM
-      PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayTN[] = {
-      &TNOdtPatTblEnt,
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblSAOArrayTN[] = {
-      PSC_TBL_TN_SODIMM3_SAO
-      PSC_TBL_TN_SODWN_SODIMM3_SAO
-      PSC_TBL_TN_UDIMM3_SAO
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayTN[] = {
-      &TNMR0WrTblEntry,
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayTN[] = {
-      &TNMR0CLTblEntry,
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblGenArrayTN[] = {
-      &TNDdr3CKETriEnt,
-      PSC_TBL_TN_CLK_DIS_FM2
-      PSC_TBL_TN_ODT_TRI_FM2
-      PSC_TBL_TN_CS_TRI_FM2
-      PSC_TBL_TN_CLK_DIS_FS1
-      PSC_TBL_TN_ODT_TRI_FS1
-      PSC_TBL_TN_CS_TRI_FS1
-      PSC_TBL_TN_CLK_DIS_FP2
-      PSC_TBL_TN_ODT_TRI_FP2
-      PSC_TBL_TN_CS_TRI_FP2
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblS2DArrayTN[] = {
-      PSC_TBL_TN_UDIMM3_S2D_FM2
-      PSC_TBL_TN_SODIMM3_S2D_FS1
-      PSC_TBL_TN_SODIMM3_S2D_FP2
-      PSC_TBL_TN_SODIMM3_S2D_FM2
-      PSC_TBL_END
-    };
-
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = {
-      (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN,
-      (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN,
-      (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN,
-      (PSC_TBL_ENTRY **)&memPSCTblSAOArrayTN,
-      (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayTN,
-      (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayTN,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      (PSC_TBL_ENTRY **)&memPSCTblGenArrayTN,
-      (PSC_TBL_ENTRY **)&memPSCTblS2DArrayTN,
-      NULL,
-      NULL
-    };
-
-    extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
-    extern MEM_PSC_FLOW MemPGetRttNomWr;
-    extern MEM_PSC_FLOW MemPGetODTPattern;
-    extern MEM_PSC_FLOW MemPGetSAO;
-    extern MEM_PSC_FLOW MemPGetMR0WrCL;
-    extern MEM_PSC_FLOW MemPGetS2D;
-
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = {
-      &memPSCTblBlockTN,
-      MemPGetMaxFreqSupported,
-      MemPGetRttNomWr,
-      MemPGetODTPattern,
-      MemPGetSAO,
-      MemPGetMR0WrCL,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MemPGetS2D,
-      MEM_PSC_FLOW_DEFTRUE
-    };
-    #define MEM_PSC_FLOW_BLOCK_TN &memPlatSpecFlowTN,
-  #else
-    #define MEM_PSC_FLOW_BLOCK_TN
-  #endif
-
-
-  #define PSC_TBL_KB_UDIMM3_S2D_FT3
-  #define PSC_TBL_KB_SODIMM3_S2D_FT3
-  #if OPTION_MEMCTLR_KB
-    #if OPTION_FT3_SOCKET_SUPPORT
-      extern PSC_TBL_ENTRY KBClkDisMapEntSOFT3;
-      #define PSC_TBL_KB_CLK_DIS_FT3 &KBClkDisMapEntSOFT3,
-      extern PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3;
-      #define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3,
-      extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3;
-      #define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3,
-      #undef PSC_TBL_KB_UDIMM3_S2D_FT3
-      #ifndef extern_S2DTblEntUFT3
-      #define extern_S2DTblEntUFT3
-        extern PSC_TBL_ENTRY S2DTblEntUFT3;
-      #endif
-      #define PSC_TBL_KB_UDIMM3_S2D_FT3  &S2DTblEntUFT3,
-    #endif
-    #if OPTION_UDIMMS
-      #if (OPTION_MICROSERVER == TRUE)
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L;
-        #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntMicroSrvU6L,
-      #else
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L;
-        #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntU6L,
-      #endif
-      extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L;
-      #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L  &KBMaxFreqTblEntU4L,
-      #if OPTION_FT3_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY KBDramTermTblEntUFT3;
-        #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3  &KBDramTermTblEntUFT3,
-        extern PSC_TBL_ENTRY KBSAOTblEntU3FT3;
-        #define PSC_TBL_KB_UDIMM3_SAO_FT3  &KBSAOTblEntU3FT3,
-      #endif
-      #undef PSC_TBL_KB_UDIMM3_S2D_FT3
-      #ifndef extern_S2DTblEntUFT3
-      #define extern_S2DTblEntUFT3
-        extern PSC_TBL_ENTRY S2DTblEntUFT3;
-      #endif
-      #define PSC_TBL_KB_UDIMM3_S2D_FT3  &S2DTblEntUFT3,
-    #endif
-    #if OPTION_SODIMMS
-      #if OPTION_FT3_SOCKET_SUPPORT
-        extern PSC_TBL_ENTRY KBSAOTblEntSO3;
-        #define PSC_TBL_KB_SODIMM3_SAO  &KBSAOTblEntSO3,
-        extern PSC_TBL_ENTRY KBSAOTblEntSoDwnPlusSODIMM3;
-        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO  &KBSAOTblEntSoDwnPlusSODIMM3,
-        extern PSC_TBL_ENTRY KBSAOTblEntSoDwn3;
-        #define PSC_TBL_KB_SODWN_SAO  &KBSAOTblEntSoDwn3,
-        extern PSC_TBL_ENTRY KBDramTermTblEntSO3;
-        #define PSC_TBL_KB_SODIMM3_DRAM_TERM  &KBDramTermTblEntSO3,
-        extern PSC_TBL_ENTRY KBDramTermTblEntSoDwnPlusSODIMM3;
-        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM  &KBDramTermTblEntSoDwnPlusSODIMM3,
-        extern PSC_TBL_ENTRY KBDramTermTblEntSoDwn3;
-        #define PSC_TBL_KB_SODWN_DRAM_TERM  &KBDramTermTblEntSoDwn3,
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntSO6L;
-        #define PSC_TBL_KB_SODIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntSO6L,
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntSO4L;
-        #define PSC_TBL_KB_SODIMM3_MAX_FREQ_4L  &KBMaxFreqTblEntSO4L,
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM6L;
-        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L  &KBMaxFreqTblEntSoDwnPlusSODIMM6L,
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM4L;
-        #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L  &KBMaxFreqTblEntSoDwnPlusSODIMM6L,
-        extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn;
-        #define PSC_TBL_KB_SODWN_MAX_FREQ  &KBMaxFreqTblEntSoDwn,
-        #undef PSC_TBL_KB_SODIMM3_S2D_FT3
-        #define PSC_TBL_KB_SODIMM3_S2D_FT3
-      #endif
-    #endif
-    extern PSC_TBL_ENTRY KBMR0WrTblEntry;
-    extern PSC_TBL_ENTRY KBMR0CLTblEntry;
-    extern PSC_TBL_ENTRY KBDdr3CKETriEnt;
-    extern PSC_TBL_ENTRY KB1DOdtPatTblEnt;
-    extern PSC_TBL_ENTRY KB2DOdtPatTblEnt;
-
-    #ifndef PSC_TBL_KB_SODIMM3_MAX_FREQ_6L
-      #define PSC_TBL_KB_SODIMM3_MAX_FREQ_6L
-    #endif
-    #ifndef PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
-      #define PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L
-      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
-      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_MAX_FREQ
-      #define PSC_TBL_KB_SODWN__MAX_FREQ
-    #endif
-    #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_6L
-      #define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L
-    #endif
-    #ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
-      #define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
-    #endif
-    #ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
-      #define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
-    #endif
-    #ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM
-      #define PSC_TBL_KB_SODIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
-      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_DRAM_TERM
-      #define PSC_TBL_KB_SODWN_DRAM_TERM
-    #endif
-    #ifndef PSC_TBL_KB_SODIMM3_SAO
-      #define PSC_TBL_KB_SODIMM3_SAO
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
-      #define PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
-    #endif
-    #ifndef PSC_TBL_KB_SODWN_SAO
-      #define PSC_TBL_KB_SODWN_SAO
-    #endif
-    #ifndef PSC_TBL_KB_UDIMM3_SAO_FT3
-      #define PSC_TBL_KB_UDIMM3_SAO_FT3
-    #endif
-    #ifndef PSC_TBL_KB_CLK_DIS_FT3
-      #define PSC_TBL_KB_CLK_DIS_FT3
-    #endif
-    #ifndef PSC_TBL_KB_ODT_TRI_FT3
-      #define PSC_TBL_KB_ODT_TRI_FT3
-    #endif
-    #ifndef PSC_TBL_KB_CS_TRI_FT3
-      #define PSC_TBL_KB_CS_TRI_FT3
-    #endif
-
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayKB[] = {
-      // 4 layer tables block
-      PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
-      PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
-      PSC_TBL_KB_SODWN_MAX_FREQ
-      PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
-      PSC_TBL_END,
-      // 6 layer tables block
-      PSC_TBL_KB_SODIMM3_MAX_FREQ_6L
-      PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_6L
-      PSC_TBL_KB_SODWN_MAX_FREQ
-      PSC_TBL_KB_UDIMM3_MAX_FREQ_6L
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = {
-      PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
-      PSC_TBL_KB_SODIMM3_DRAM_TERM
-      PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
-      PSC_TBL_KB_SODWN_DRAM_TERM
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayKB[] = {
-      &KB1DOdtPatTblEnt,
-      &KB2DOdtPatTblEnt,
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblSAOArrayKB[] = {
-      PSC_TBL_KB_SODIMM3_SAO
-      PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
-      PSC_TBL_KB_SODWN_SAO
-      PSC_TBL_KB_UDIMM3_SAO_FT3
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayKB[] = {
-      &KBMR0WrTblEntry,
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayKB[] = {
-      &KBMR0CLTblEntry,
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblGenArrayKB[] = {
-      &KBDdr3CKETriEnt,
-      PSC_TBL_KB_CLK_DIS_FT3
-      PSC_TBL_KB_ODT_TRI_FT3
-      PSC_TBL_KB_CS_TRI_FT3
-      PSC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memPSCTblS2DArrayKB[] = {
-      PSC_TBL_KB_UDIMM3_S2D_FT3
-      PSC_TBL_KB_SODIMM3_S2D_FT3
-      PSC_TBL_END
-    };
-
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockKB = {
-      (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayKB,
-      (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayKB,
-      (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayKB,
-      (PSC_TBL_ENTRY **)&memPSCTblSAOArrayKB,
-      (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayKB,
-      (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayKB,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      (PSC_TBL_ENTRY **)&memPSCTblGenArrayKB,
-      (PSC_TBL_ENTRY **)&memPSCTblS2DArrayKB,
-      NULL,
-      NULL
-    };
-
-    extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
-    extern MEM_PSC_FLOW MemPGetRttNomWr;
-    extern MEM_PSC_FLOW MemPGetODTPattern;
-    extern MEM_PSC_FLOW MemPGetSAO;
-    extern MEM_PSC_FLOW MemPGetMR0WrCL;
-    extern MEM_PSC_FLOW MemPGetS2D;
-
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowKB = {
-      &memPSCTblBlockKB,
-      MemPGetMaxFreqSupported,
-      MemPGetRttNomWr,
-      MemPGetODTPattern,
-      MemPGetSAO,
-      MemPGetMR0WrCL,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MEM_PSC_FLOW_DEFTRUE,
-      MemPGetS2D,
-      MEM_PSC_FLOW_DEFTRUE
-    };
-    #define MEM_PSC_FLOW_BLOCK_KB &memPlatSpecFlowKB,
-  #else
-    #define MEM_PSC_FLOW_BLOCK_KB
-  #endif
-
-
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
-    MEM_PSC_FLOW_BLOCK_TN
-    MEM_PSC_FLOW_BLOCK_KB
-    MEM_PSC_FLOW_BLOCK_END
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-  *
-  *  LRDIMM CONTROL
-  *
-  *---------------------------------------------------------------------------------------------------
-  */
-  #if (OPTION_LRDIMMS == TRUE)
-    #if (OPTION_MEMCTLR_BK == TRUE)
-      #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
-    #else
-      #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
-    #endif
-  #else //#if (OPTION_LRDIMMS == FALSE)
-    #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
-  #endif
-  MEM_TECH_LRDIMM memLrdimmSupported = {
-    MEM_TECH_LRDIMM_STRUCT_VERSION,
-    MEM_TECH_FEATURE_LRDIMM_INIT
-  };
-#else
-  /*---------------------------------------------------------------------------------------------------
-   * MAIN FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * NB TRAINING FLOW CONTROL
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY MAP
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT MAIN FEATURE BLOCK
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
-    0
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT NORTHBRIDGE SUPPORT LIST
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if (OPTION_MEMCTLR_TN == TRUE)
-    #undef MEM_NB_SUPPORT_TN
-    #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN },
-  #endif
-  #if (OPTION_MEMCTLR_KB == TRUE)
-    #undef MEM_NB_SUPPORT_KB
-    #define MEM_NB_SUPPORT_KB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_KB, MEM_IDENDIMM_KB },
-  #endif
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT Technology Training
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #if OPTION_DDR2
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
-      0
-    };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
-      { 0 }
-    };
-  #endif
-  #if OPTION_DDR3
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
-      0
-    };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
-      { 0 }
-    };
-  #endif
-    /*---------------------------------------------------------------------------------------------------
-     * DEFAULT Platform Specific list
-     *
-     *
-     *---------------------------------------------------------------------------------------------------
-     */
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
-    NULL
-  };
-
-  /*----------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
-    NULL
-  };
-
-  MEM_TECH_LRDIMM memLrdimmSupported = {
-    MEM_TECH_LRDIMM_STRUCT_VERSION,
-    NULL
-  };
-#endif
-
-/*---------------------------------------------------------------------------------------------------
- * NORTHBRIDGE SUPPORT LIST
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
-MEM_NB_SUPPORT memNBInstalled[] = {
-  MEM_NB_SUPPORT_TN
-  MEM_NB_SUPPORT_KB
-  MEM_NB_SUPPORT_END
-};
-
-UINT8 SizeOfNBInstalledTable = sizeof (memNBInstalled) / sizeof (memNBInstalled[0]);
-
-
-#endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecoveryInstall.h
deleted file mode 100644
index 0ed16d5d73..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryRecoveryInstall.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
-#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
-
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-
-  #if (OPTION_MEMCTLR_TN == TRUE)
-    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockTN;
-    #define MEM_REC_NB_SUPPORT_TN MemRecConstructNBBlockTN,
-  #else
-    #define MEM_REC_NB_SUPPORT_TN
-  #endif
-
-  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
-    MEM_REC_NB_SUPPORT_TN
-    NULL
-  };
-
-  #define MEM_REC_TECH_CONSTRUCTOR_DDR2
-  #if (OPTION_DDR3 == TRUE)
-    extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
-    #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
-  #else
-    #define MEM_REC_TECH_CONSTRUCTOR_DDR3
-  #endif
-
-  MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
-    MEM_REC_TECH_CONSTRUCTOR_DDR3
-    MEM_REC_TECH_CONSTRUCTOR_DDR2
-    NULL
-  };
-
-  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
-    NULL
-  };
-
-  /*---------------------------------------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  #define MEM_PSC_REC_FLOW_BLOCK_END NULL
-  #define PSC_REC_TBL_END NULL
-  #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) MemRecDefTrue
-
-  #if OPTION_MEMCTLR_TN
-    #if OPTION_UDIMMS
-      extern PSC_TBL_ENTRY RecTNDramTermTblEntU;
-      #define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM  &RecTNDramTermTblEntU,
-      extern PSC_TBL_ENTRY RecTNSAOTblEntU3;
-      #define PSC_REC_TBL_TN_UDIMM3_SAO  &RecTNSAOTblEntU3,
-    #endif
-    #if OPTION_SODIMMS
-      extern PSC_TBL_ENTRY RecTNSAOTblEntSO3;
-      #define PSC_REC_TBL_TN_SODIMM3_SAO  &RecTNSAOTblEntSO3,
-      extern PSC_TBL_ENTRY RecTNDramTermTblEntSO;
-      #define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM  &RecTNDramTermTblEntSO,
-    #endif
-    extern PSC_TBL_ENTRY RecTNMR0WrTblEntry;
-    extern PSC_TBL_ENTRY RecTNMR0CLTblEntry;
-    extern PSC_TBL_ENTRY RecTNDdr3CKETriEnt;
-    extern PSC_TBL_ENTRY RecTNOdtPatTblEnt;
-
-    #ifndef PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
-      #define PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
-      #define PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
-    #endif
-    #ifndef PSC_REC_TBL_TN_SODIMM3_SAO
-      #define PSC_REC_TBL_TN_SODIMM3_SAO
-    #endif
-    #ifndef PSC_REC_TBL_TN_UDIMM3_SAO
-      #define PSC_REC_TBL_TN_UDIMM3_SAO
-    #endif
-
-    PSC_TBL_ENTRY* memRecPSCTblDramTermArrayTN[] = {
-      PSC_REC_TBL_TN_UDIMM3_DRAM_TERM
-      PSC_REC_TBL_TN_SODIMM3_DRAM_TERM
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblODTPatArrayTN[] = {
-      &RecTNOdtPatTblEnt,
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblSAOArrayTN[] = {
-      PSC_REC_TBL_TN_SODIMM3_SAO
-      PSC_REC_TBL_TN_UDIMM3_SAO
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayTN[] = {
-      &RecTNMR0WrTblEntry,
-      PSC_REC_TBL_END
-    };
-
-    PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayTN[] = {
-      &RecTNMR0CLTblEntry,
-      PSC_REC_TBL_END
-    };
-
-    MEM_PSC_TABLE_BLOCK memRecPSCTblBlockTN = {
-      NULL,
-      (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayTN,
-      (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayTN,
-      (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayTN,
-      (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayTN,
-      (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayTN,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL,
-      NULL
-    };
-    extern MEM_PSC_FLOW MemPRecGetRttNomWr;
-    #define PSC_REC_FLOW_TN_DRAM_TERM   MemPRecGetRttNomWr
-    extern MEM_PSC_FLOW MemPRecGetODTPattern;
-    #define PSC_REC_FLOW_TN_ODT_PATTERN   MemPRecGetODTPattern
-    extern MEM_PSC_FLOW MemPRecGetSAO;
-    #define PSC_REC_FLOW_TN_SAO   MemPRecGetSAO
-    extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
-    #define PSC_REC_FLOW_TN_MR0_WRCL   MemPRecGetMR0WrCL
-
-    MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowTN = {
-      &memRecPSCTblBlockTN,
-      MEM_REC_PSC_FLOW_DEFTRUE,
-      PSC_REC_FLOW_TN_DRAM_TERM,
-      PSC_REC_FLOW_TN_ODT_PATTERN,
-      PSC_REC_FLOW_TN_SAO,
-      PSC_REC_FLOW_TN_MR0_WRCL,
-      MEM_REC_PSC_FLOW_DEFTRUE,
-      MEM_REC_PSC_FLOW_DEFTRUE,
-      MEM_REC_PSC_FLOW_DEFTRUE,
-      MEM_REC_PSC_FLOW_DEFTRUE,
-      MEM_REC_PSC_FLOW_DEFTRUE,
-      MEM_REC_PSC_FLOW_DEFTRUE
-    };
-    #define MEM_PSC_REC_FLOW_BLOCK_TN &memRecPlatSpecFlowTN,
-  #else
-    #define MEM_PSC_REC_FLOW_BLOCK_TN
-  #endif
-
-  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
-    MEM_PSC_REC_FLOW_BLOCK_TN
-    MEM_PSC_REC_FLOW_BLOCK_END
-  };
-
-#else
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT TECHNOLOGY BLOCK
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {    // Types of technology installed
-    NULL
-  };
-  /*---------------------------------------------------------------------------------------------------
-   * DEFAULT NORTHBRIDGE SUPPORT LIST
-   *
-   *
-   *---------------------------------------------------------------------------------------------------
-   */
-  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
-    NULL
-  };
-  /*----------------------------------------------------------------------
-   * DEFAULT PSCFG DEFINITIONS
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
-    NULL
-  };
-  /*----------------------------------------------------------------------
-   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
-   *
-   *----------------------------------------------------------------------
-   */
-  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
-    NULL
-  };
-#endif
-#endif  // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMmioMapInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMmioMapInstall.h
deleted file mode 100644
index 0150c1bcb6..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMmioMapInstall.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: MMIO map manager
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_MMIO_MAP_INSTALL_H_
-#define _OPTION_MMIO_MAP_INSTALL_H_
-
-#include "mmioMapManager.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define F15_MMIO_MAP_SUPPORT
-#define F16_MMIO_MAP_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
-  // Family 15h
-  #ifdef OPTION_FAMILY15H
-    #if OPTION_FAMILY15H == TRUE
-      extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F15MmioMapSupport;
-      #undef F15_MMIO_MAP_SUPPORT
-      #define F15_MMIO_MAP_SUPPORT {AMD_FAMILY_15, &F15MmioMapSupport},
-    #endif
-  #endif
-
-  // Family 16h
-  #ifdef OPTION_FAMILY16H
-    #if OPTION_FAMILY16H == TRUE
-      extern CONST MMIO_MAP_FAMILY_SERVICES ROMDATA F16MmioMapSupport;
-      #undef F16_MMIO_MAP_SUPPORT
-      #define F16_MMIO_MAP_SUPPORT {AMD_FAMILY_16, &F16MmioMapSupport},
-    #endif
-  #endif
-
-#endif
-
-
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MmioMapFamilyServiceArray[] =
-{
-  F15_MMIO_MAP_SUPPORT
-  F16_MMIO_MAP_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MmioMapFamilyServiceTable =
-{
-  (sizeof (MmioMapFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &MmioMapFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_MMIO_MAP_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMsgBasedC1eInstall.h
deleted file mode 100644
index d99bb7c0f7..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMsgBasedC1eInstall.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Message-Based C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
-#define _OPTION_MSG_BASED_C1E_INSTALL_H_
-
-#include "cpuMsgBasedC1e.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_MSG_BASED_C1E_FEAT
-#define F15_BK_MSG_BASED_C1E_SUPPORT
-#if OPTION_MSG_BASED_C1E == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-
-
-    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
-    {
-      {0, NULL}
-    };
-    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
-    {
-      (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-      &MsgBasedC1eFamilyServiceArray[0]
-    };
-  #endif
-#endif
-#endif  // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocketInstall.h
deleted file mode 100644
index cc79ceb883..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionMultiSocketInstall.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Multiple Socket Support
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_MULTISOCKET_INSTALL_H_
-#define _OPTION_MULTISOCKET_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#ifndef OPTION_MULTISOCKET
-  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-#if OPTION_MULTISOCKET == TRUE
-  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
-  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrMulti
-  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
-  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sMulti
-  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
-  #define GET_SYS_NB_COF      GetSystemNbCofMulti
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
-  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
-  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
-  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
-  OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
-  #define GET_MIN_NB_COF GetMinNbCofMulti
-  OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti;
-  #define GET_PCI_ADDRESS GetCurrPciAddrMulti
-  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti;
-  #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti
-#else
-  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
-  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrSingle
-  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
-  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sSingle
-  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
-  #define GET_SYS_NB_COF      GetSystemNbCofSingle
-  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
-  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
-  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
-  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
-  OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
-  #define GET_MIN_NB_COF GetMinNbCofSingle
-  OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle;
-  #define GET_PCI_ADDRESS GetCurrPciAddrSingle
-  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle;
-  #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle
-#endif
-
-/*  Declare the instance of the multisocket option configuration structure  */
-OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
-  MULTISOCKET_STRUCT_VERSION,
-  GET_NUM_PM_STEPS,
-  CORE0_PM_TASK,
-  GET_SYS_NB_COF,
-  GET_SYS_NB_COF_UPDATE,
-  GET_EARLY_PM_ERRORS,
-  GET_MIN_NB_COF,
-  GET_PCI_ADDRESS,
-  MODIFY_CURR_SOCKET_PCI
-};
-
-#endif  // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
deleted file mode 100644
index 711b1a3ace..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Prefetch Mode
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_PREFETCH_MODE_INSTALL_H_
-#define _OPTION_PREFETCH_MODE_INSTALL_H_
-
-#include "cpuPrefetchMode.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_PREFETCH_MODE_FEAT
-#define CPU_PREFETCH_MODE_AP_TASK
-#define F15_PREFETCH_MODE_SUPPORT
-#define F16_PREFETCH_MODE_SUPPORT
-
-#if OPTION_PREFETCH_MODE == TRUE
-  #if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
-    #undef CPU_PREFETCH_MODE_AP_TASK
-    #define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask},
-
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePrefetchMode;
-        #undef OPTION_PREFETCH_MODE_FEAT
-        #define OPTION_PREFETCH_MODE_FEAT &CpuFeaturePrefetchMode,
-        extern CONST PREFETCH_MODE_FAMILY_SERVICES ROMDATA F15PrefetchModeSupport;
-        #undef F15_PREFETCH_MODE_SUPPORT
-        #define F15_PREFETCH_MODE_SUPPORT {AMD_FAMILY_15, &F15PrefetchModeSupport},
-      #endif
-    #endif
-
-
-    ///@todo
-    // Family 16h
-    //#ifdef OPTION_FAMILY16H
-    //  #if OPTION_FAMILY16H == TRUE
-    //    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePrefetchMode;
-    //    #undef OPTION_PREFETCH_MODE_FEAT
-    //    #define OPTION_PREFETCH_MODE_FEAT &CpuFeaturePrefetchMode,
-    //    extern CONST PREFETCH_MODE_FAMILY_SERVICES ROMDATA F16PrefetchModeSupport;
-    //    #undef F16_PREFETCH_MODE_SUPPORT
-    //    #define F16_PREFETCH_MODE_SUPPORT {AMD_FAMILY_16, &F16PrefetchModeSupport},
-    //  #endif
-    //#endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PrefetchModeFamilyServiceArray[] =
-{
-  F15_PREFETCH_MODE_SUPPORT
-  F16_PREFETCH_MODE_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PrefetchModeFamilyServiceTable =
-{
-  (sizeof (PrefetchModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &PrefetchModeFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_PREFETCH_MODE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPreserveMailboxInstall.h
deleted file mode 100644
index 1f32feecba..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPreserveMailboxInstall.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Preserve Mailbox
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-
-#include "PreserveMailbox.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_PRESERVE_MAILBOX_FEAT
-#define F15_PRESERVE_MAILBOX_SUPPORT
-
-
-#endif  // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPsiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPsiInstall.h
deleted file mode 100644
index 8e8910770d..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPsiInstall.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Power Status Indicator (PSI).
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_PSI_INSTALL_H_
-#define _OPTION_PSI_INSTALL_H_
-
-#include "cpuPsi.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_PSI_FEAT
-#define F15_TN_PSI_SUPPORT
-#define F16_KB_PSI_SUPPORT
-
-#if OPTION_CPU_PSI == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        #if OPTION_FAMILY15H_TN == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
-          #undef OPTION_CPU_PSI_FEAT
-          #define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
-          extern CONST PSI_FAMILY_SERVICES ROMDATA F15TnPsiSupport;
-          #undef F15_TN_PSI_SUPPORT
-          #define F15_TN_PSI_SUPPORT {AMD_FAMILY_15_TN, &F15TnPsiSupport},
-        #endif
-      #endif
-    #endif
-
-    // Family 16h
-    #ifdef OPTION_FAMILY16H
-      #if OPTION_FAMILY16H == TRUE
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePsi;
-          #undef OPTION_CPU_PSI_FEAT
-          #define OPTION_CPU_PSI_FEAT &CpuFeaturePsi,
-          extern CONST PSI_FAMILY_SERVICES ROMDATA F16KbPsiSupport;
-          #undef F16_KB_PSI_SUPPORT
-          #define F16_KB_PSI_SUPPORT {AMD_FAMILY_16_KB, &F16KbPsiSupport},
-        #endif
-      #endif
-    #endif
-
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PsiFamilyServiceArray[] =
-{
-  F15_TN_PSI_SUPPORT
-  F16_KB_PSI_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PsiFamilyServiceTable =
-{
-  (sizeof (PsiFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &PsiFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_PSI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateHpcModeInstall.h
deleted file mode 100644
index 58699e6372..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateHpcModeInstall.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Pstate HPC mode.
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
-#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_
-
-#include "cpuPstateHpcMode.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_CPU_PSTATE_HPC_MODE_FEAT
-#define F15_PSTATE_HPC_MODE_SUPPORT
-
-
-#endif  // _OPTION_PSTATE_HPC_MODE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateInstall.h
deleted file mode 100644
index a3c5fa3328..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPstateInstall.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: PState
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_PSTATE_INSTALL_H_
-#define _OPTION_PSTATE_INSTALL_H_
-
-#include "cpuPstateTables.h"
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-
-#define F15_TN_PSTATE_SERVICE_SUPPORT
-#define F16_KB_PSTATE_SERVICE_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
-  //
-  //Define Pstate CPU Family service
-  //
-  #ifdef OPTION_FAMILY15H
-    #if OPTION_FAMILY15H == TRUE
-      #ifdef OPTION_FAMILY15H_TN
-        #if OPTION_FAMILY15H_TN == TRUE
-          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
-          #undef F15_TN_PSTATE_SERVICE_SUPPORT
-          #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
-        #endif
-      #endif
-    #endif
-  #endif
-
-  #ifdef OPTION_FAMILY16H
-    #if OPTION_FAMILY16H == TRUE
-      #ifdef OPTION_FAMILY16H_KB
-        #if OPTION_FAMILY16H_KB == TRUE
-          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F16KbPstateServices;
-          #undef F16_KB_PSTATE_SERVICE_SUPPORT
-          #define F16_KB_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_16_KB, &F16KbPstateServices},
-        #endif
-      #endif
-    #endif
-  #endif
-  //
-  //Define ACPI Pstate objects.
-  //
-  #ifndef OPTION_ACPI_PSTATES
-    #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
-  #endif
-  #if (OPTION_ACPI_PSTATES == TRUE)
-    OPTION_SSDT_FEATURE               GenerateSsdt;
-    #define USER_SSDT_MAIN            GenerateSsdt
-    #ifndef OPTION_MULTISOCKET
-      #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-    #endif
-
-    OPTION_ACPI_FEATURE               CreatePStateAcpiTables;
-    OPTION_PSTATE_GATHER              PStateGatherMain;
-    #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
-      OPTION_PSTATE_LEVELING          PStateLevelingMain;
-      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingMain
-    #else
-      OPTION_PSTATE_LEVELING            PStateLevelingStub;
-      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-    #endif
-    #if AGESA_ENTRY_INIT_LATE == TRUE
-      #define USER_PSTATE_OPTION_MAIN   CreatePStateAcpiTables
-    #else
-      OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #endif
-    #if AGESA_ENTRY_INIT_POST == TRUE
-      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
-    #else
-      OPTION_PSTATE_GATHER              PStateGatherStub;
-      #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-    #endif
-    #if CFG_ACPI_PSTATES_PPC == TRUE
-      #define USER_PSTATE_CFG_PPC   TRUE
-    #else
-      #define USER_PSTATE_CFG_PPC   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PCT == TRUE
-      #define USER_PSTATE_CFG_PCT   TRUE
-    #else
-      #define USER_PSTATE_CFG_PCT   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PSD == TRUE
-      #define USER_PSTATE_CFG_PSD   TRUE
-    #else
-      #define USER_PSTATE_CFG_PSD   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_PSS == TRUE
-      #define USER_PSTATE_CFG_PSS   TRUE
-    #else
-      #define USER_PSTATE_CFG_PSS   FALSE
-    #endif
-    #if CFG_ACPI_PSTATES_XPSS == TRUE
-      #define USER_PSTATE_CFG_XPSS   TRUE
-    #else
-      #define USER_PSTATE_CFG_XPSS   FALSE
-    #endif
-
-    #if OPTION_IO_CSTATE == TRUE
-      OPTION_ACPI_FEATURE             CreateCStateAcpiTables;
-      #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
-    #else
-      OPTION_ACPI_FEATURE             CreateAcpiTablesStub;
-      #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
-    #endif
-  #else
-    OPTION_SSDT_FEATURE               GenerateSsdtStub;
-    OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-    OPTION_PSTATE_GATHER              PStateGatherStub;
-    OPTION_PSTATE_LEVELING            PStateLevelingStub;
-    #define USER_SSDT_MAIN            GenerateSsdtStub
-    #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
-    #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-    #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-    #define USER_PSTATE_CFG_PPC    FALSE
-    #define USER_PSTATE_CFG_PCT    FALSE
-    #define USER_PSTATE_CFG_PSD    FALSE
-    #define USER_PSTATE_CFG_PSS    FALSE
-    #define USER_PSTATE_CFG_XPSS   FALSE
-
-    // If ACPI Objects are disabled for PStates, we still need to check
-    // whether ACPI Objects are enabled for CStates
-    #if OPTION_IO_CSTATE == TRUE
-      OPTION_SSDT_FEATURE               GenerateSsdt;
-      OPTION_PSTATE_GATHER              PStateGatherMain;
-      OPTION_ACPI_FEATURE               CreateCStateAcpiTables;
-      #undef  USER_SSDT_MAIN
-      #define USER_SSDT_MAIN            GenerateSsdt
-      #undef  USER_PSTATE_OPTION_GATHER
-      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
-      #undef  USER_CSTATE_OPTION_MAIN
-      #define USER_CSTATE_OPTION_MAIN   CreateCStateAcpiTables
-    #endif
-  #endif
-#else
-  OPTION_SSDT_FEATURE               GenerateSsdtStub;
-  OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
-  OPTION_PSTATE_GATHER              PStateGatherStub;
-  OPTION_PSTATE_LEVELING            PStateLevelingStub;
-  #define USER_SSDT_MAIN            GenerateSsdtStub
-  #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
-  #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
-  #define USER_PSTATE_OPTION_GATHER PStateGatherStub
-  #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
-  #define USER_PSTATE_CFG_PPC    FALSE
-  #define USER_PSTATE_CFG_PCT    FALSE
-  #define USER_PSTATE_CFG_PSD    FALSE
-  #define USER_PSTATE_CFG_PSS    FALSE
-  #define USER_PSTATE_CFG_XPSS   FALSE
-#endif
-
-/*  Declare the instance of the PSTATE option configuration structure  */
-OPTION_PSTATE_POST_CONFIGURATION      OptionPstatePostConfiguration = {
-  PSTATE_STRUCT_VERSION,
-  USER_PSTATE_OPTION_GATHER,
-  USER_PSTATE_OPTION_LEVEL
-};
-
-OPTION_PSTATE_LATE_CONFIGURATION      OptionPstateLateConfiguration = {
-  PSTATE_STRUCT_VERSION,
-  USER_SSDT_MAIN,
-  USER_PSTATE_OPTION_MAIN,
-  USER_CSTATE_OPTION_MAIN,
-  USER_PSTATE_CFG_PPC,
-  USER_PSTATE_CFG_PCT,
-  USER_PSTATE_CFG_PSD,
-  USER_PSTATE_CFG_PSS,
-  USER_PSTATE_CFG_XPSS,
-  {CFG_ACPI_SET_OEM_ID},
-  {CFG_ACPI_SET_OEM_TABLE_ID}
-};
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
-{
-  F15_TN_PSTATE_SERVICE_SUPPORT
-  F16_KB_PSTATE_SERVICE_SUPPORT
-  {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
-{
-  (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &PstateCpuFamilyServiceArray[0]
-};
-#endif  // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionS3ScriptInstall.h
deleted file mode 100644
index d36004ff3e..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionS3ScriptInstall.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: S3SCRIPT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_S3SCRIPT_INSTALL_H_
-#define _OPTION_S3SCRIPT_INSTALL_H_
-
-#include "S3SaveState.h"
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#ifndef OPTION_S3SCRIPT
-  #define OPTION_S3SCRIPT  FALSE    //if not define assume PI not use script
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
-  #if OPTION_S3SCRIPT == TRUE
-    #define P_S3_SCRIPT_INIT      S3ScriptInitState
-  #endif
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-  #if OPTION_S3SCRIPT == TRUE
-    #define P_S3_SCRIPT_RESTORE   S3ScriptRestoreState
-  #endif
-#endif
-
-#ifndef P_S3_SCRIPT_INIT
-  #define P_S3_SCRIPT_INIT        S3ScriptInitStateStub
-#endif
-
-#ifndef P_S3_SCRIPT_RESTORE
-  #define P_S3_SCRIPT_RESTORE     S3ScriptInitStateStub
-  #undef  GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
-  #define GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-/*  Declare the instance of the S3SCRIPT option configuration structure  */
-S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
-  P_S3_SCRIPT_INIT,
-  P_S3_SCRIPT_RESTORE
-};
-
-S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
-  GNB_S3_DISPATCH_FUNCTION_TABLE
-  {0, NULL}
-};
-#endif  // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionSlitInstall.h
deleted file mode 100644
index 2e42384e5a..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionSlitInstall.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SLIT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_SLIT_INSTALL_H_
-#define _OPTION_SLIT_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_SLIT
-    #error  BLDOPT: Option not defined: "OPTION_SLIT"
-  #endif
-  #if OPTION_SLIT == TRUE
-    OPTION_SLIT_FEATURE               GetAcpiSlitMain;
-    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBuffer;
-    #define USER_SLIT_OPTION     GetAcpiSlitMain
-    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
-  #else
-    OPTION_SLIT_FEATURE               GetAcpiSlitStub;
-    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
-    #define USER_SLIT_OPTION     GetAcpiSlitStub
-    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
-  #endif
-#else
-  OPTION_SLIT_FEATURE               GetAcpiSlitStub;
-  OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
-  #define USER_SLIT_OPTION     GetAcpiSlitStub
-  #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
-#endif
-/*  Declare the instance of the SLIT option configuration structure  */
-OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
-  SLIT_STRUCT_VERSION,
-  USER_SLIT_OPTION,
-  USER_SLIT_RELEASE_BUFFER,
-  {CFG_ACPI_SET_OEM_ID},
-  {CFG_ACPI_SET_OEM_TABLE_ID}
-};
-
-#endif  // _OPTION_SLIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionSratInstall.h
deleted file mode 100644
index 0e3fb296da..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionSratInstall.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SRAT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_SRAT_INSTALL_H_
-#define _OPTION_SRAT_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_SRAT
-    #error  BLDOPT: Option not defined: "OPTION_SRAT"
-  #endif
-  #if OPTION_SRAT == TRUE
-    OPTION_SRAT_FEATURE          GetAcpiSratMain;
-    #define USER_SRAT_OPTION     GetAcpiSratMain
-  #else
-    OPTION_SRAT_FEATURE          GetAcpiSratStub;
-    #define USER_SRAT_OPTION     GetAcpiSratStub
-  #endif
-#else
-  OPTION_SRAT_FEATURE            GetAcpiSratStub;
-  #define USER_SRAT_OPTION       GetAcpiSratStub
-#endif
-
-/*  Declare the instance of the WHEA option configuration structure  */
-OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
-  SRAT_STRUCT_VERSION,
-  USER_SRAT_OPTION,
-  {CFG_ACPI_SET_OEM_ID},
-  {CFG_ACPI_SET_OEM_TABLE_ID}
-};
-
-#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionTdpLimitingInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionTdpLimitingInstall.h
deleted file mode 100644
index 843bd85ec0..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionTdpLimitingInstall.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: TDP Limiting.
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_TDP_LIMITING_INSTALL_H_
-#define _OPTION_TDP_LIMITING_INSTALL_H_
-
-#include "cpuTdpLimiting.h"
-
-/*  This option is designed to be included into the CPU features install
- *  file. The CPU features install file will define the options status.
- *  Check to validate the definition
- */
-#define OPTION_TDP_LIMIT_FEAT
-#define F15_TDP_LIMIT_SUPPORT
-
-#if OPTION_CPU_TDP_LIMITING == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
-    // Family 15h
-    #ifdef OPTION_FAMILY15H
-      #if OPTION_FAMILY15H == TRUE
-        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureTdpLimit;
-        #undef OPTION_TDP_LIMIT_FEAT
-        #define OPTION_TDP_LIMIT_FEAT &CpuFeatureTdpLimit,
-        extern CONST TDP_LIMIT_FAMILY_SERVICES ROMDATA F15TdpLimitSupport;
-        #undef F15_TDP_LIMIT_SUPPORT
-        #define F15_TDP_LIMIT_SUPPORT {AMD_FAMILY_15, &F15TdpLimitSupport},
-      #endif
-    #endif
-  #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA TdpLimitFamilyServiceArray[] =
-{
-  F15_TDP_LIMIT_SUPPORT
-  {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA TdpLimitFamilyServiceTable =
-{
-  (sizeof (TdpLimitFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
-  &TdpLimitFamilyServiceArray[0]
-};
-
-#endif  // _OPTION_TDP_LIMITING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionWheaInstall.h
deleted file mode 100644
index afbd3259bb..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/OptionWheaInstall.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: WHEA
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Options
- * @e \$Revision: 84150 $   @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _OPTION_WHEA_INSTALL_H_
-#define _OPTION_WHEA_INSTALL_H_
-
-/*  This option is designed to be included into the platform solution install
- *  file. The platform solution install file will define the options status.
- *  Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
-  #ifndef OPTION_WHEA
-    #error  BLDOPT: Option not defined: "OPTION_WHEA"
-  #endif
-  #if OPTION_WHEA == TRUE
-    OPTION_WHEA_FEATURE          GetAcpiWheaMain;
-    #define USER_WHEA_OPTION     GetAcpiWheaMain
-  #else
-    OPTION_WHEA_FEATURE          GetAcpiWheaStub;
-    #define USER_WHEA_OPTION     GetAcpiWheaStub
-  #endif
-
-#else
-  OPTION_WHEA_FEATURE            GetAcpiWheaStub;
-  #define USER_WHEA_OPTION       GetAcpiWheaStub
-#endif
-
-/*  Declare the instance of the WHEA option configuration structure  */
-OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
-  WHEA_STRUCT_VERSION,
-  USER_WHEA_OPTION
-};
-
-#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
deleted file mode 100644
index 7ff268d67e..0000000000
--- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
+++ /dev/null
@@ -1,2111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a combination of package type, processor, and features.
- *
- * This file generates the defaults tables for the all platform solution
- * combinations.  The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:      AGESA
- * @e sub-project:  Core
- * @e \$Revision: 85818 $   @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
- */
-/*****************************************************************************
- *
- * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-/*****************************************************************************
- *
- * Start processing the user options:  First, set default settings
- *
- ****************************************************************************/
-
-VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
-  //ModuleHeaderSignature
-  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
-  Int32FromChar ('0', '0', '0', '0'),
-  //ModuleIdentifier[8]
-  AGESA_ID,
-  //ModuleVersion[12]
-  AGESA_VERSION_STRING,
-  //ModuleDispatcher
-  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
-  //NextBlock
-  NULL
-};
-
-/* Process solution defined socket / family installations
- *
- * As part of the release package for each image, define the options below to select the
- * AGESA processor support included in that image.
- */
-
-/*  Default sockets to off  */
-#define OPTION_FT3_SOCKET_SUPPORT    FALSE
-
-/*  Default families to off  */
-#define OPTION_FAMILY15H_MODEL_1x    FALSE
-#define OPTION_FAMILY16H_MODEL_0x    FALSE
-
-
-/*  Enable the appropriate socket support  */
-
-#ifdef INSTALL_FT3_SOCKET_SUPPORT
-  #if  INSTALL_FT3_SOCKET_SUPPORT == TRUE
-    #undef OPTION_FT3_SOCKET_SUPPORT
-    #define OPTION_FT3_SOCKET_SUPPORT  TRUE
-  #endif
-#endif
-
-
-
-// F16_0x is supported in FT3
-#ifdef INSTALL_FAMILY_16_MODEL_0x_SUPPORT
-  #if  INSTALL_FAMILY_16_MODEL_0x_SUPPORT == TRUE
-    #undef OPTION_FAMILY16H
-    #define OPTION_FAMILY16H     TRUE
-    #undef OPTION_FAMILY16H_MODEL_0x
-    #define OPTION_FAMILY16H_MODEL_0x     TRUE
-  #endif
-#endif
-
-/*  Turn off families not required by socket designations */
-#if (OPTION_FAMILY15H_MODEL_1x == FALSE)
-  #undef OPTION_FAMILY15H
-  #define OPTION_FAMILY15H     FALSE
-#endif
-
-#if (OPTION_FAMILY16H_MODEL_0x == TRUE)
-  #if (OPTION_FT3_SOCKET_SUPPORT == FALSE)
-    #undef OPTION_FAMILY16H_MODEL_0x
-    #define OPTION_FAMILY16H_MODEL_0x  FALSE
-  #endif
-#endif
-
-
-#if (OPTION_FAMILY16H_MODEL_0x == FALSE)
-  #undef OPTION_FAMILY16H
-  #define OPTION_FAMILY16H     FALSE
-#endif
-
-
-#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY16H_MODEL_0x == FALSE) && (OPTION_FAMILY16H_MODEL_3x == FALSE)
-    #error No FT3 supported families included in the build
-  #endif
-#endif
-
-
-/* Process AGESA private data
- *
- * Turn on appropriate CPU models and memory controllers,
- * as well as some other memory controls.
- */
-
-/*  Default all models to off  */
-#define OPTION_FAMILY15H_TN          FALSE
-#define OPTION_FAMILY16H_KB          FALSE
-#define OPTION_FAMILY15H_UNKNOWN     FALSE
-
-/*  Default all memory controllers to off  */
-#define OPTION_MEMCTLR_TN            FALSE
-#define OPTION_MEMCTLR_KB            FALSE
-
-/*  Default all memory controls to off  */
-#define OPTION_HW_WRITE_LEV_TRAINING            FALSE
-#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
-#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
-#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
-#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
-#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
-#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
-#define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
-#define OPTION_MAX_RD_LAT_TRAINING              FALSE
-#define OPTION_HW_DRAM_INIT                     FALSE
-#define OPTION_SW_DRAM_INIT                     FALSE
-#define OPTION_S3_MEM_SUPPORT                   FALSE
-#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
-#define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
-#define OPTION_RDDQS_2D_TRAINING                FALSE
-#define OPTION_PRE_MEM_INIT                     FALSE
-#define OPTION_POST_MEM_INIT                    FALSE
-
-/*  Defaults for public user options  */
-#define OPTION_UDIMMS                           FALSE
-#define OPTION_RDIMMS                           FALSE
-#define OPTION_SODIMMS                          FALSE
-#define OPTION_LRDIMMS                          FALSE
-#define OPTION_DDR2                             FALSE
-#define OPTION_DDR3                             FALSE
-#define OPTION_ECC                              FALSE
-#define OPTION_BANK_INTERLEAVE                  FALSE
-#define OPTION_DCT_INTERLEAVE                   FALSE
-#define OPTION_NODE_INTERLEAVE                  FALSE
-#define OPTION_PARALLEL_TRAINING                FALSE
-#define OPTION_ONLINE_SPARE                     FALSE
-#define OPTION_MEM_RESTORE                      FALSE
-#define OPTION_DIMM_EXCLUDE                     FALSE
-#define OPTION_AMP                              FALSE
-#define OPTION_DATA_EYE                         FALSE
-#define OPTION_AGGRESSOR                        FALSE
-
-/*  Default all CPU controls to off  */
-#define OPTION_MULTISOCKET                      FALSE
-#define OPTION_CRAT                             FALSE
-#define OPTION_CDIT                             FALSE
-#define OPTION_SRAT                             FALSE
-#define OPTION_SLIT                             FALSE
-#define OPTION_HT_ASSIST                        FALSE
-#define OPTION_ATM_MODE                         FALSE
-#define OPTION_NBR_CACHE                        FALSE
-#define OPTION_CPU_CORELEVELING                 FALSE
-#define OPTION_MSG_BASED_C1E                    FALSE
-#define OPTION_CPU_CFOH                         FALSE
-#define OPTION_C6_STATE                         FALSE
-#define OPTION_IO_CSTATE                        FALSE
-#define OPTION_CPB                              FALSE
-#define OPTION_CPU_APM                          FALSE
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT   FALSE
-#define OPTION_CPU_PSTATE_HPC_MODE              FALSE
-#define OPTION_CPU_TDP_LIMITING                 FALSE
-#define OPTION_CPU_PSI                          FALSE
-#define OPTION_CPU_HTC                          FALSE
-#define OPTION_S3SCRIPT                         FALSE
-#define OPTION_GFX_RECOVERY                     FALSE
-#define OPTION_CPU_SCS                          FALSE
-#define OPTION_PREFETCH_MODE                    FALSE
-
-/*  Default FCH controls to off  */
-#define FCH_SUPPORT                             FALSE
-
-/*  Enable all private controls based on socket/family enables  */
-
-#if (OPTION_FT3_SOCKET_SUPPORT == TRUE)
-  #if (OPTION_FAMILY16H_MODEL_0x == TRUE)
-    #undef FCH_SUPPORT
-    #define FCH_SUPPORT          TRUE
-    #undef OPTION_FAMILY16H_KB
-    #define OPTION_FAMILY16H_KB  TRUE
-    #undef OPTION_MEMCTLR_KB
-    #define OPTION_MEMCTLR_KB    TRUE
-    #undef OPTION_HW_WRITE_LEV_TRAINING
-    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
-    #undef OPTION_CONTINOUS_PATTERN_GENERATION
-    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
-    #undef OPTION_HW_DQS_REC_EN_TRAINING
-    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
-    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
-    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
-    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
-    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
-    #undef OPTION_RDDQS_2D_TRAINING
-    #define OPTION_RDDQS_2D_TRAINING  TRUE
-    #undef OPTION_MAX_RD_LAT_TRAINING
-    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
-    #undef OPTION_SW_DRAM_INIT
-    #define OPTION_SW_DRAM_INIT  TRUE
-    #undef OPTION_S3_MEM_SUPPORT
-    #define OPTION_S3_MEM_SUPPORT  TRUE
-    #undef OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY  TRUE
-    #undef OPTION_CPU_CORELEVELING
-    #define OPTION_CPU_CORELEVELING  TRUE
-    #undef OPTION_C6_STATE
-    #define OPTION_C6_STATE  TRUE
-    #undef OPTION_IO_CSTATE
-    #define OPTION_IO_CSTATE TRUE
-    #undef OPTION_CPU_CFOH
-    #define OPTION_CPU_CFOH  TRUE
-    #undef OPTION_CPU_APM
-    #define OPTION_CPU_APM TRUE
-    #undef OPTION_CPB
-    #define OPTION_CPB  TRUE
-    #undef OPTION_CPU_HTC
-    #define OPTION_CPU_HTC TRUE
-    #undef OPTION_CPU_PSI
-    #define OPTION_CPU_PSI TRUE
-    #undef OPTION_CDIT
-    #define OPTION_CDIT  TRUE
-    #undef OPTION_CRAT
-    #define OPTION_CRAT  TRUE
-    #undef OPTION_CPU_SCS
-    #define OPTION_CPU_SCS TRUE
-    #undef OPTION_S3SCRIPT
-    #define OPTION_S3SCRIPT  TRUE
-    ///@todo
-    //#undef OPTION_PREFETCH_MODE
-    //#define OPTION_PREFETCH_MODE TRUE
-    #undef OPTION_UDIMMS
-    #define OPTION_UDIMMS  TRUE
-    #undef OPTION_SODIMMS
-    #define OPTION_SODIMMS  TRUE
-    #undef OPTION_DDR3
-    #define OPTION_DDR3  TRUE
-    #undef OPTION_ECC
-    #define OPTION_ECC  TRUE
-    #undef OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE  TRUE
-    #undef OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE  TRUE
-    #undef OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE  TRUE
-    #undef OPTION_DIMM_EXCLUDE
-    #define OPTION_DIMM_EXCLUDE  TRUE
-    #ifndef OPTION_MICROSERVER
-      #define OPTION_MICROSERVER  FALSE
-    #endif
-  #endif
-#endif
-
-
-#if (OPTION_FAMILY16H_KB == TRUE)
-  #undef  GNB_SUPPORT
-  #define GNB_SUPPORT   TRUE
-#endif
-
-#define OPTION_ACPI_PSTATES             TRUE
-#define OPTION_WHEA                     TRUE
-#define OPTION_DMI                      TRUE
-#define OPTION_EARLY_SAMPLES            FALSE
-#define CFG_ACPI_PSTATES_PPC            TRUE
-#define CFG_ACPI_PSTATES_PCT            TRUE
-#define CFG_ACPI_PSTATES_PSD            TRUE
-#define CFG_ACPI_PSTATES_PSS            TRUE
-#define CFG_ACPI_PSTATES_XPSS           TRUE
-#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
-#define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
-#define OPTION_ALIB                     TRUE
-/*---------------------------------------------------------------------------
- *       Processing the options:  Second, process the user's selections
- *--------------------------------------------------------------------------*/
-#ifdef BLDOPT_REMOVE_DDR3_SUPPORT
-  #if  BLDOPT_REMOVE_DDR3_SUPPORT == TRUE
-    #undef  OPTION_DDR3
-    #define OPTION_DDR3               FALSE
-  #endif
-#endif
-#if ((OPTION_DDR3 == FALSE))
-  #error  BLDOPT: No DIMM type support selected. BLDOPT_REMOVE_DDR3_SUPPORT must be FALSE.
-#endif
-#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
-  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
-    #undef  OPTION_MULTISOCKET
-    #define OPTION_MULTISOCKET          FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ECC_SUPPORT
-  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
-    #undef  OPTION_ECC
-    #define OPTION_ECC        FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
-    #undef  OPTION_UDIMMS
-    #define OPTION_UDIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
-    #undef  OPTION_RDIMMS
-    #define OPTION_RDIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
-    #undef  OPTION_SODIMMS
-    #define OPTION_SODIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
-  #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
-    #undef  OPTION_LRDIMMS
-    #define OPTION_LRDIMMS               FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
-  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
-    #undef  OPTION_BANK_INTERLEAVE
-    #define OPTION_BANK_INTERLEAVE      FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
-  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
-    #undef  OPTION_DCT_INTERLEAVE
-    #define OPTION_DCT_INTERLEAVE       FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
-  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
-    #undef  OPTION_NODE_INTERLEAVE
-    #define OPTION_NODE_INTERLEAVE      FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
-  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
-    #undef  OPTION_PARALLEL_TRAINING
-    #define OPTION_PARALLEL_TRAINING    FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
-  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
-    #undef  OPTION_ONLINE_SPARE
-    #define OPTION_ONLINE_SPARE         FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
-  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
-    #undef  OPTION_MEM_RESTORE
-    #define OPTION_MEM_RESTORE         FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
-  #if  BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
-    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
-    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ACPI_PSTATES
-  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
-    #undef  OPTION_ACPI_PSTATES
-    #define OPTION_ACPI_PSTATES         FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_CRAT
-  #if  BLDOPT_REMOVE_CRAT == TRUE
-    #undef  OPTION_CRAT
-    #define OPTION_CRAT                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_CDIT
-  #if  BLDOPT_REMOVE_CDIT == TRUE
-    #undef  OPTION_CDIT
-    #define OPTION_CDIT                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_SRAT
-  #if  BLDOPT_REMOVE_SRAT == TRUE
-    #undef  OPTION_SRAT
-    #define OPTION_SRAT                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_SLIT
-  #if  BLDOPT_REMOVE_SLIT == TRUE
-    #undef  OPTION_SLIT
-    #define OPTION_SLIT                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_WHEA
-  #if  BLDOPT_REMOVE_WHEA == TRUE
-    #undef  OPTION_WHEA
-    #define OPTION_WHEA                 FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_DMI
-  #if  BLDOPT_REMOVE_DMI == TRUE
-    #undef  OPTION_DMI
-    #define OPTION_DMI                  FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
-  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
-    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
-    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
-  #endif
-#endif
-#ifdef BLDOPT_REMOVE_AMP_SUPPORT
-  #if  BLDOPT_REMOVE_AMP_SUPPORT == TRUE
-    #undef  OPTION_AMP
-    #define OPTION_AMP        FALSE
-  #endif
-#endif
-
-#ifdef OPTION_RDDQS_2D_TRAINING
-  #if OPTION_RDDQS_2D_TRAINING == FALSE
-    #undef OPTION_DATA_EYE
-    #define OPTION_DATA_EYE     FALSE
-  #else
-    #ifdef BLDOPT_REMOVE_DATA_EYE
-      #if BLDOPT_REMOVE_DATA_EYE == TRUE
-        #undef OPTION_DATA_EYE
-        #define OPTION_DATA_EYE     FALSE
-      #endif
-    #endif
-  #endif
-#else
-  #undef OPTION_DATA_EYE
-  #define OPTION_DATA_EYE     FALSE
-#endif
-
-#ifdef BLDOPT_REMOVE_HT_ASSIST
-  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
-    #undef  OPTION_HT_ASSIST
-    #define OPTION_HT_ASSIST      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ATM_MODE
-  #if  BLDOPT_REMOVE_ATM_MODE == TRUE
-    #undef  OPTION_ATM_MODE
-    #define OPTION_ATM_MODE      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_NEIGHBOR_CACHE
-  #if  BLDOPT_REMOVE_NEIGHBOR_CACHE == TRUE
-    #undef  OPTION_NBR_CACHE
-    #define OPTION_NBR_CACHE      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
-  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
-    #undef  OPTION_MSG_BASED_C1E
-    #define OPTION_MSG_BASED_C1E      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_C6_STATE
-  #if  BLDOPT_REMOVE_C6_STATE == TRUE
-    #undef  OPTION_C6_STATE
-    #define OPTION_C6_STATE      FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_GFX_RECOVERY
-  #if  BLDOPT_REMOVE_GFX_RECOVERY == TRUE
-    #undef  OPTION_GFX_RECOVERY
-    #define OPTION_GFX_RECOVERY         FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING
-  #if  BLDOPT_REMOVE_HW_RDDQS_2D_TRAINING == TRUE
-    #undef OPTION_RDDQS_2D_TRAINING
-    #define OPTION_RDDQS_2D_TRAINING      FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
-    #undef  CFG_ACPI_PSTATES_PPC
-    #define CFG_ACPI_PSTATES_PPC        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
-    #undef  CFG_ACPI_PSTATES_PCT
-    #define CFG_ACPI_PSTATES_PCT        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
-    #undef  CFG_ACPI_PSTATES_PSD
-    #define CFG_ACPI_PSTATES_PSD        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
-    #undef  CFG_ACPI_PSTATES_PSS
-    #define CFG_ACPI_PSTATES_PSS        FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
-  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
-    #undef  CFG_ACPI_PSTATES_XPSS
-    #define CFG_ACPI_PSTATES_XPSS       FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
-  #if  BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT  == TRUE
-    #undef  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
-    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT    FALSE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_AGGRESSOR
-  #if  BLDOPT_REMOVE_AGGRESSOR == TRUE
-    #undef  OPTION_AGGRESSOR
-    #define OPTION_AGGRESSOR      FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_PSTATE_HPC_MODE
-  #if  BLDCFG_PSTATE_HPC_MODE  == TRUE
-    #undef  OPTION_CPU_PSTATE_HPC_MODE
-    #define OPTION_CPU_PSTATE_HPC_MODE    TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
-  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
-    #undef  CFG_ACPI_PSTATE_PSD_INDPX
-    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_ACPI_PSTATES_PSD_POLICY
-    #define CFG_ACPI_PSTATES_PSD_POLICY     (BLDCFG_ACPI_PSTATES_PSD_POLICY)
-#else
-    #define CFG_ACPI_PSTATES_PSD_POLICY     PsdPolicyProcessorDefault
-#endif
-
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
-  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
-    #undef  CFG_VRM_HIGH_SPEED_ENABLE
-    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
-  #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
-    #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
-    #define CFG_VRM_NB_HIGH_SPEED_ENABLE    TRUE
-  #endif
-#endif
-
-#ifdef BLDCFG_STARTING_BUSNUM
-  #define CFG_STARTING_BUSNUM         (BLDCFG_STARTING_BUSNUM)
-#else
-  #define CFG_STARTING_BUSNUM         (0)
-#endif
-
-#ifdef BLDCFG_AMD_PLATFORM_TYPE
-  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
-#else
-  #define CFG_AMD_PLATFORM_TYPE              0
-#endif
-
-CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
-
-#ifdef BLDCFG_MAXIMUM_BUSNUM
-  #define CFG_MAXIMUM_BUSNUM          (BLDCFG_MAXIMUM_BUSNUM)
-#else
-  #define CFG_MAXIMUM_BUSNUM          (0xF8)
-#endif
-
-#ifdef BLDCFG_ALLOCATED_BUSNUM
-  #define CFG_ALLOCATED_BUSNUM        (BLDCFG_ALLOCATED_BUSNUM)
-#else
-  #define CFG_ALLOCATED_BUSNUM        (0x20)
-#endif
-
-#ifdef BLDCFG_BUID_SWAP_LIST
-  #define CFG_BUID_SWAP_LIST         (BLDCFG_BUID_SWAP_LIST)
-#else
-  #define CFG_BUID_SWAP_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
-  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
-#else
-  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
-  #define CFG_HTFABRIC_LIMITS_LIST         (BLDCFG_HTFABRIC_LIMITS_LIST)
-#else
-  #define CFG_HTFABRIC_LIMITS_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
-  #define CFG_HTCHAIN_LIMITS_LIST         (BLDCFG_HTCHAIN_LIMITS_LIST)
-#else
-  #define CFG_HTCHAIN_LIMITS_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_BUS_NUMBERS_LIST
-  #define CFG_BUS_NUMBERS_LIST         (BLDCFG_BUS_NUMBERS_LIST)
-#else
-  #define CFG_BUS_NUMBERS_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_IGNORE_LINK_LIST
-  #define CFG_IGNORE_LINK_LIST         (BLDCFG_IGNORE_LINK_LIST)
-#else
-  #define CFG_IGNORE_LINK_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
-  #define CFG_LINK_SKIP_REGANG_LIST         (BLDCFG_LINK_SKIP_REGANG_LIST)
-#else
-  #define CFG_LINK_SKIP_REGANG_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
-  #define CFG_SET_HTCRC_SYNC_FLOOD         (BLDCFG_SET_HTCRC_SYNC_FLOOD)
-#else
-  #define CFG_SET_HTCRC_SYNC_FLOOD         (FALSE)
-#endif
-
-#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
-  #define CFG_USE_UNIT_ID_CLUMPING         (BLDCFG_USE_UNIT_ID_CLUMPING)
-#else
-  #define CFG_USE_UNIT_ID_CLUMPING         (FALSE)
-#endif
-
-#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
-  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
-#else
-  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (NULL)
-#endif
-
-#ifdef BLDCFG_USE_HT_ASSIST
-  #define CFG_USE_HT_ASSIST               (BLDCFG_USE_HT_ASSIST)
-#else
-  #define CFG_USE_HT_ASSIST               (TRUE)
-#endif
-
-#ifdef BLDCFG_USE_ATM_MODE
-  #define CFG_USE_ATM_MODE                (BLDCFG_USE_ATM_MODE)
-#else
-  #define CFG_USE_ATM_MODE                (TRUE)
-#endif
-
-#ifdef BLDCFG_USE_NEIGHBOR_CACHE
-  #define CFG_USE_NBR_CACHE                (BLDCFG_USE_NEIGHBOR_CACHE)
-#else
-  #define CFG_USE_NBR_CACHE                (TRUE)
-#endif
-
-#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
-  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
-#else
-  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (Nfcm)
-#endif
-
-#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
-  #define CFG_PERFORMANCE_HARDWARE_PREFETCHER  (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
-#else
-  #define CFG_PERFORMANCE_HARDWARE_PREFETCHER  (HARDWARE_PREFETCHER_AUTO)
-#endif
-
-#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
-  #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES  (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
-#else
-  #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES  (SOFTWARE_PREFETCHES_AUTO)
-#endif
-
-#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
-  #define CFG_PERFORMANCE_DRAM_PREFETCHER  (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
-#else
-  #define CFG_PERFORMANCE_DRAM_PREFETCHER  (DRAM_PREFETCHER_AUTO)
-#endif
-
-#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
-  #define CFG_PLATFORM_DEEMPHASIS_LIST  (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
-#else
-  #define CFG_PLATFORM_DEEMPHASIS_LIST  (NULL)
-#endif
-
-#ifdef BLDCFG_VRM_CURRENT_LIMIT
-  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
-#else
-  #define CFG_VRM_CURRENT_LIMIT            0
-#endif
-
-#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
-  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
-#else
-  #define CFG_VRM_LOW_POWER_THRESHOLD      0
-#endif
-
-#ifdef BLDCFG_VRM_SLEW_RATE
-  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
-#else
-  #define CFG_VRM_SLEW_RATE                DFLT_VRM_SLEW_RATE
-#endif
-
-#ifdef BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-  #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
-#else
-  #define CFG_VRM_MAXIMUM_CURRENT_LIMIT  (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-  #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
-#else
-  #define CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT  (0)
-#endif
-
-#ifdef BLDCFG_VRM_SVI_OCP_LEVEL
-  #define CFG_VRM_SVI_OCP_LEVEL     BLDCFG_VRM_SVI_OCP_LEVEL
-#else
-  #define CFG_VRM_SVI_OCP_LEVEL     0
-#endif
-
-#ifdef BLDCFG_VRM_NB_SVI_OCP_LEVEL
-  #define CFG_VRM_NB_SVI_OCP_LEVEL  BLDCFG_VRM_NB_SVI_OCP_LEVEL
-#else
-  #define CFG_VRM_NB_SVI_OCP_LEVEL  0
-#endif
-
-#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
-  #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
-#else
-  #define CFG_VRM_NB_CURRENT_LIMIT         (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
-  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
-#else
-  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_SLEW_RATE
-  #define CFG_VRM_NB_SLEW_RATE             BLDCFG_VRM_NB_SLEW_RATE
-#else
-  #define CFG_VRM_NB_SLEW_RATE             DFLT_VRM_SLEW_RATE
-#endif
-
-#ifdef BLDCFG_PLAT_NUM_IO_APICS
-  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
-#else
-  #define CFG_PLAT_NUM_IO_APICS            0
-#endif
-
-#ifdef BLDCFG_MEM_INIT_PSTATE
-  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
-#else
-  #define CFG_MEM_INIT_PSTATE              0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_MODE
-  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
-#else
-  #define CFG_C1E_MODE                        C1eModeDisabled
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA
-  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
-#else
-  #define CFG_C1E_OPDATA                      0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
-  #define CFG_C1E_OPDATA1                     BLDCFG_PLATFORM_C1E_OPDATA1
-#else
-  #define CFG_C1E_OPDATA1                     0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
-  #define CFG_C1E_OPDATA2                     BLDCFG_PLATFORM_C1E_OPDATA2
-#else
-  #define CFG_C1E_OPDATA2                     0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
-  #define CFG_C1E_OPDATA3                     BLDCFG_PLATFORM_C1E_OPDATA3
-#else
-  #define CFG_C1E_OPDATA3                     0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_MODE
-  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
-#else
-  #define CFG_CSTATE_MODE                     CStateModeC6
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
-  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
-#else
-  #define CFG_CSTATE_OPDATA                   0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
-  #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
-#else
-  #define CFG_CSTATE_IO_BASE_ADDRESS       0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CPB_MODE
-  #define CFG_CPB_MODE                        BLDCFG_PLATFORM_CPB_MODE
-#else
-  #define CFG_CPB_MODE                        CpbModeAuto
-#endif
-
-#ifdef BLDCFG_CORE_LEVELING_MODE
-  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
-#else
-  #define CFG_CORE_LEVELING_MODE           0
-#endif
-
-#ifdef BLDCFG_AMD_TDP_LIMIT
-  #define CFG_AMD_POWER_CEILING            BLDCFG_AMD_TDP_LIMIT
-#else
-  #define CFG_AMD_POWER_CEILING            0
-#endif
-
-#ifdef BLDCFG_HEAP_DRAM_ADDRESS
-  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
-#else
-  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
-#endif
-
-#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
-#else
-  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
-#endif
-
-#ifdef BLDCFG_MEMORY_MODE_UNGANGED
-  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
-#else
-  #define CFG_MEMORY_MODE_UNGANGED              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
-  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
-#else
-  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
-  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
-#else
-  #define CFG_MEMORY_QUADRANK_TYPE              DFLT_MEMORY_QUADRANK_TYPE
-#endif
-
-#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
-  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
-#else
-  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
-  #define CFG_MEMORY_LRDIMM_CAPABLE              BLDCFG_MEMORY_LRDIMM_CAPABLE
-#else
-  #define CFG_MEMORY_LRDIMM_CAPABLE              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
-  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
-#else
-  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
-  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
-#else
-  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
-#endif
-
-#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
-  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
-#else
-  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
-  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
-#else
-  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
-  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
-#else
-  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
-  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
-#else
-  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_POWER_DOWN
-  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
-#else
-  #define CFG_MEMORY_POWER_DOWN                 FALSE
-#endif
-
-#ifdef BLDCFG_POWER_DOWN_MODE
-  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
-#else
-  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
-#endif
-
-#ifdef BLDCFG_ONLINE_SPARE
-  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
-#else
-  #define CFG_ONLINE_SPARE                      FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_PARITY_ENABLE
-  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
-#else
-  #define CFG_MEMORY_PARITY_ENABLE              FALSE
-#endif
-
-#ifdef BLDCFG_BANK_SWIZZLE
-  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
-#else
-  #define CFG_BANK_SWIZZLE                      TRUE
-#endif
-
-#ifdef BLDCFG_TIMING_MODE_SELECT
-  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
-#else
-  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
-#endif
-
-#ifdef BLDCFG_MEMORY_CLOCK_SELECT
-  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
-#else
-  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
-#endif
-
-#ifdef BLDCFG_DQS_TRAINING_CONTROL
-  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
-#else
-  #define CFG_DQS_TRAINING_CONTROL              TRUE
-#endif
-
-#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
-  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
-#else
-  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
-#endif
-
-#ifdef BLDCFG_USE_BURST_MODE
-  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
-#else
-  #define CFG_USE_BURST_MODE                    FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
-  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
-#else
-  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
-#endif
-
-#ifdef BLDCFG_ENABLE_ECC_FEATURE
-  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
-#else
-  #define CFG_ENABLE_ECC_FEATURE                TRUE
-#endif
-
-#ifdef BLDCFG_ECC_REDIRECTION
-  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
-#else
-  #define CFG_ECC_REDIRECTION                   FALSE
-#endif
-
-#ifdef BLDCFG_SCRUB_DRAM_RATE
-  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
-#else
-  #define CFG_SCRUB_DRAM_RATE         DFLT_SCRUB_DRAM_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_L2_RATE
-  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
-#else
-  #define CFG_SCRUB_L2_RATE           DFLT_SCRUB_L2_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_L3_RATE
-  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
-#else
-  #define CFG_SCRUB_L3_RATE           DFLT_SCRUB_L3_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_IC_RATE
-  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
-#else
-  #define CFG_SCRUB_IC_RATE           DFLT_SCRUB_IC_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_DC_RATE
-  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
-#else
-  #define CFG_SCRUB_DC_RATE           DFLT_SCRUB_DC_RATE
-#endif
-
-#ifdef BLDCFG_ECC_SYNC_FLOOD
-  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
-#else
-  #define CFG_ECC_SYNC_FLOOD          TRUE
-#endif
-
-#ifdef BLDCFG_ECC_SYMBOL_SIZE
-  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
-#else
-  #define CFG_ECC_SYMBOL_SIZE         0
-#endif
-
-#ifdef BLDCFG_1GB_ALIGN
-  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
-#else
-  #define CFG_1GB_ALIGN               FALSE
-#endif
-
-#ifdef BLDCFG_UMA_ALLOCATION_MODE
-  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
-#else
-  #define CFG_UMA_MODE                UMA_AUTO
-#endif
-
-#ifdef BLDCFG_FORCE_TRAINING_MODE
-  #define CFG_FORCE_TRAIN_MODE                BLDCFG_FORCE_TRAINING_MODE
-#else
-  #define CFG_FORCE_TRAIN_MODE                FORCE_TRAIN_AUTO
-#endif
-
-#ifdef BLDCFG_UMA_ALLOCATION_SIZE
-  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
-#else
-  #define CFG_UMA_SIZE                0
-#endif
-
-#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
-  #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
-#else
-  #define CFG_UMA_ABOVE4G           FALSE
-#endif
-
-#ifdef BLDCFG_UMA_ALIGNMENT
-  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
-#else
-  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
-#endif
-
-#ifdef BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
-  #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG      BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG
-#else
-  #define CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG      DDR3_TECHNOLOGY
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
-  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
-#else
-  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
-#endif
-
-#ifdef BLDCFG_S3_LATE_RESTORE
-  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
-#else
-  #define CFG_S3_LATE_RESTORE         TRUE
-#endif
-
-#ifdef BLDCFG_USE_32_BYTE_REFRESH
-  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
-#else
-  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
-#endif
-
-#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
-  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
-#else
-  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
-  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
-#else
-  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
-  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
-#else
-  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
-#endif
-
-#ifdef BLDCFG_CFG_GNB_HD_AUDIO
-  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
-#else
-  #define CFG_GNB_HD_AUDIO                   TRUE
-#endif
-
-#ifdef BLDCFG_CFG_ABM_SUPPORT
-  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
-#else
-  #define CFG_ABM_SUPPORT                    FALSE
-#endif
-
-#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
-  #define CFG_DYNAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
-#else
-  #define CFG_DYNAMIC_REFRESH_RATE           0
-#endif
-
-#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
-  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
-#else
-  #define CFG_LCD_BACK_LIGHT_CONTROL         200
-#endif
-
-#ifdef BLDCFG_STEREO_3D_PINOUT
-  #define CFG_GNB_STEREO_3D_PINOUT           BLDCFG_STEREO_3D_PINOUT
-#else
-  #define CFG_GNB_STEREO_3D_PINOUT           0
-#endif
-
-#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
-  #define CFG_GNB_REMOTE_DISPLAY_SUPPORT     BLDCFG_REMOTE_DISPLAY_SUPPORT
-#else
-  #define CFG_GNB_REMOTE_DISPLAY_SUPPORT     FALSE
-#endif
-
-// Define pin configuration for SYNCFLOOD
-// Default to FALSE (Use pin as SYNCFLOOD)
-#ifdef BLDCFG_USE_SYNCFLOOD_AS_NMI
-  #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI       BLDCFG_USE_SYNCFLOOD_AS_NMI
-#else
-  #define CFG_GNB_SYNCFLOOD_PIN_AS_NMI       FALSE
-#endif
-
-#ifdef BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
-  #define CFG_GNB_THERMAL_SENSOR_CORRECTION  BLDCFG_GNB_THERMAL_SENSOR_CORRECTION
-#else
-  #define CFG_GNB_THERMAL_SENSOR_CORRECTION  0
-#endif
-
-#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
-  #define CFG_GNB_IGPU_SSID                  BLDCFG_IGPU_SUBSYSTEM_ID
-#else
-  #define CFG_GNB_IGPU_SSID                  0
-#endif
-
-#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
-  #define CFG_GNB_HDAUDIO_SSID               BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
-#else
-  #define CFG_GNB_HDAUDIO_SSID               0
-#endif
-
-#ifdef BLDCFG_IGPU_ENABLE_DISABLE_POLICY
-  #define CFG_IGPU_ENABLE_DISABLE_POLICY    BLDCFG_IGPU_ENABLE_DISABLE_POLICY
-#else
-  #define CFG_IGPU_ENABLE_DISABLE_POLICY    IGPU_DISABLE_AUTO
-#endif
-
-#ifdef BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
-  #define CFG_GNB_PCIE_SSID                  BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
-#else
-  #define CFG_GNB_PCIE_SSID                  0x12341022ul
-#endif
-
-#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
-#else
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               0
-#endif
-
-#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
-#else
-  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
-#endif
-
-#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
-  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
-#else
-  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
-#endif
-
-#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
-  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
-#else
-  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000ul
-#endif
-
-#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
-  #define CFG_ENABLE_EXTERNAL_VREF                BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
-#else
-  #define CFG_ENABLE_EXTERNAL_VREF                FALSE
-#endif
-
-#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
-  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
-    #undef  OPTION_EARLY_SAMPLES
-    #define OPTION_EARLY_SAMPLES        FALSE
-  #else
-    #undef  OPTION_EARLY_SAMPLES
-    #define OPTION_EARLY_SAMPLES        TRUE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ALIB
-  #if  BLDOPT_REMOVE_ALIB == TRUE
-    #undef  OPTION_ALIB
-    #define OPTION_ALIB                 FALSE
-  #else
-    #undef  OPTION_ALIB
-    #define OPTION_ALIB                 TRUE
-  #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FCH_COMPONENT
-  #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
-    #undef FCH_SUPPORT
-    #define FCH_SUPPORT                            FALSE
-  #endif
-#endif
-
-#ifdef BLDCFG_IOMMU_SUPPORT
-  #define CFG_IOMMU_SUPPORT             BLDCFG_IOMMU_SUPPORT
-#else
-  #define CFG_IOMMU_SUPPORT             TRUE
-#endif
-
-#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
-  #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
-#else
-  #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             0
-#endif
-
-#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
-  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
-#else
-  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           0
-#endif
-
-#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
-  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
-#else
-  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             0
-#endif
-
-#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
-  #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
-#else
-  #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          0
-#endif
-
-#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
-  #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
-#else
-  #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         0
-#endif
-
-#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
-  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
-#else
-  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         0
-#endif
-
-#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
-  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
-#else
-  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         0
-#endif
-
-#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
-  #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
-#else
-  #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             0
-#endif
-
-#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
-  #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
-#else
-  #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           0
-#endif
-
-
-// BLDCFG_LVDS_24BBP_PANEL_MODE
-// This specifies the LVDS 24 BBP mode.
-// 0 - Use LDI mode (default).
-// 1 - Use FPDI mode.
-#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
-  #define CFG_LVDS_24BBP_PANEL_MODE                 BLDCFG_LVDS_24BBP_PANEL_MODE
-#else
-  #define CFG_LVDS_24BBP_PANEL_MODE                 0
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
-  #define CFG_LVDS_MISC_888_FPDI_MODE                 BLDCFG_LVDS_MISC_888_FPDI_MODE
-#else
-  #define CFG_LVDS_MISC_888_FPDI_MODE                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
-  #define CFG_LVDS_MISC_DL_CH_SWAP                 BLDCFG_LVDS_MISC_DL_CH_SWAP
-#else
-  #define CFG_LVDS_MISC_DL_CH_SWAP                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
-  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
-#else
-  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
-  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
-#else
-  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
-  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
-#else
-  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
-  #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE            BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE
-#else
-  #define CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE            FALSE
-#endif
-
-#ifdef BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
-  #define CFG_LVDS_MISC_VOLT_ADJUSTMENT               BLDCFG_LVDS_MISC_VOLT_ADJUSTMENT
-#else
-  #define CFG_LVDS_MISC_VOLT_ADJUSTMENT               0
-#endif
-
-#ifdef BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
-  #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE            BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE
-#else
-  #define CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE            FALSE
-#endif
-
-#ifdef BLDCFG_DP_FIXED_VOLT_SWING
-  #define CFG_DP_FIXED_VOLT_SWING               BLDCFG_DP_FIXED_VOLT_SWING
-#else
-  #define CFG_DP_FIXED_VOLT_SWING               0
-#endif
-
-#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
-  #define CFG_PLATFORM_POWER_POLICY_MODE  (BLDCFG_PLATFORM_POWER_POLICY_MODE)
-#else
-  #define CFG_PLATFORM_POWER_POLICY_MODE  (Performance)
-#endif
-
-#ifdef BLDCFG_NB_PSTATES_SUPPORTED
-  #define CFG_NB_PSTATES_SUPPORTED        (BLDCFG_NB_PSTATES_SUPPORTED)
-#else
-  #define CFG_NB_PSTATES_SUPPORTED        (TRUE)
-#endif
-
-#ifdef BLDCFG_HTC_TEMPERATURE_LIMIT
-  #define CFG_HTC_TEMPERATURE_LIMIT        (BLDCFG_HTC_TEMPERATURE_LIMIT)
-#else
-  #define CFG_HTC_TEMPERATURE_LIMIT        (0)
-#endif
-
-#ifdef BLDCFG_LHTC_TEMPERATURE_LIMIT
-  #define CFG_LHTC_TEMPERATURE_LIMIT        (BLDCFG_LHTC_TEMPERATURE_LIMIT)
-#else
-  #define CFG_LHTC_TEMPERATURE_LIMIT        (0)
-#endif
-
-#ifdef BLDCFG_PCI_MMIO_BASE
-  #define CFG_PCI_MMIO_BASE               (BLDCFG_PCI_MMIO_BASE)
-#else
-  #define CFG_PCI_MMIO_BASE               (0)
-#endif
-
-#ifdef BLDCFG_PCI_MMIO_SIZE
-  #define CFG_PCI_MMIO_SIZE               (BLDCFG_PCI_MMIO_SIZE)
-#else
-  #define CFG_PCI_MMIO_SIZE               (0)
-#endif
-
-#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
-  #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
-#else
-  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
-#endif
-
-#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
-  #define CFG_IOMMU_EXCLUSION_RANGE_LIST      (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
-#else
-  #define CFG_IOMMU_EXCLUSION_RANGE_LIST      (NULL)
-#endif
-
-#ifdef BLDCFG_HYBRID_BOOST_ENABLE
-  #define CFG_HYBRID_BOOST_ENABLE            BLDCFG_HYBRID_BOOST_ENABLE
-#else
-  #define CFG_HYBRID_BOOST_ENABLE            TRUE
-#endif
-
-#ifdef BLDCFG_GNB_IOAPIC_ADDRESS
-  #define CFG_GNB_IOAPIC_ADDRESS             BLDCFG_GNB_IOAPIC_ADDRESS
-#else
-  #define CFG_GNB_IOAPIC_ADDRESS             NULL
-#endif
-
-#ifdef BLDCFG_GNB_IOMMU_ADDRESS
-  #define CFG_GNB_IOMMU_ADDRESS             BLDCFG_GNB_IOMMU_ADDRESS
-#else
-  #define CFG_GNB_IOMMU_ADDRESS             NULL
-#endif
-
-#ifdef BLDCFG_ENABLE_DATA_EYE
-  #define CFG_ENABLE_DATA_EYE              BLDCFG_ENABLE_DATA_EYE
-#else
-  #define CFG_ENABLE_DATA_EYE              TRUE
-#endif
-
-#ifdef BLDCFG_ACPI_SET_OEM_ID
-  #define CFG_ACPI_SET_OEM_ID             BLDCFG_ACPI_SET_OEM_ID
-#else
-  #define CFG_ACPI_SET_OEM_ID             'A','M','D',' ',' ',' '
-#endif
-
-#ifdef BLDCFG_ACPI_SET_OEM_TABLE_ID
-  #define CFG_ACPI_SET_OEM_TABLE_ID       BLDCFG_ACPI_SET_OEM_TABLE_ID
-#else
-  #define CFG_ACPI_SET_OEM_TABLE_ID       'A','G','E','S','A',' ',' ',' '
-#endif
-
-#ifdef BLDCFG_DOCKED_TDP_HEADROOM
-  #define CFG_DOCKED_TDP_HEADROOM         BLDCFG_DOCKED_TDP_HEADROOM
-#else
-  #define CFG_DOCKED_TDP_HEADROOM         TRUE
-#endif
-
-#ifdef BLDCFG_DRAM_DOUBLE_REFRESH_RATE
-  #define CFG_DRAM_DOUBLE_REFRESH_RATE             BLDCFG_DRAM_DOUBLE_REFRESH_RATE
-#else
-  #define CFG_DRAM_DOUBLE_REFRESH_RATE             FALSE
-#endif
-
-/*---------------------------------------------------------------------------
- *       Processing the options:  Third, perform the option cross checks
- *--------------------------------------------------------------------------*/
-// Assure that at least one type of memory support is included
-#if OPTION_UDIMMS == FALSE
-  #if OPTION_RDIMMS == FALSE
-    #if OPTION_SODIMMS == FALSE
-      #if OPTION_LRDIMMS == FALSE
-        #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
-      #endif
-    #endif
-  #endif
-#endif
-// Ensure at least one dimm type is capable
-#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
-  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
-    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
-      #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
-        #error   BLDCFG: No dimm type is capable
-      #endif
-    #endif
-  #endif
-#endif
-//  Turn off multi-socket based features if only one node...
-#if OPTION_MULTISOCKET == FALSE
-  #undef  OPTION_PARALLEL_TRAINING
-  #define OPTION_PARALLEL_TRAINING    FALSE
-  #undef  OPTION_NODE_INTERLEAVE
-  #define OPTION_NODE_INTERLEAVE      FALSE
-#endif
-// Ensure the frequency limit is valid
-#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR2133_FREQUENCY)
-  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY)
-    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY)
-      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY)
-        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY)
-          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY)
-            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY)
-              #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY)
-                #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY)
-                  #error    BLDCFG: Unsupported memory bus frequency
-                #endif
-              #endif
-            #endif
-          #endif
-        #endif
-      #endif
-    #endif
-  #endif
-#endif
-// Ensure timing mode is valid
-#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
-  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
-    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
-      #error    BLDCFG: Invalid timing mode is set
-    #endif
-  #endif
-#endif
-// Ensure the scrub rate is valid
-#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
-  #error    BLDCFG: Unsupported dram scrub rate set
-#endif
-#if CFG_SCRUB_L2_RATE > 0x16
-  #error   BLDCFG: Unsupported L2 scrubber rate set
-#endif
-#if CFG_SCRUB_L3_RATE > 0x16
-  #error   BLDCFG: unsupported L3 scrubber rate set
-#endif
-#if CFG_SCRUB_IC_RATE > 0x16
-  #error    BLDCFG: Unsupported Instruction cache scrub rate set
-#endif
-#if CFG_SCRUB_DC_RATE > 0x16
-  #error   BLDCFG: Unsupported Dcache scrub rate set
-#endif
-// Ensure Quad rank dimm type is valid
-#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
-  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
-    #error     BLDCFG: Invalid quad rank dimm type set
-  #endif
-#endif
-// Ensure ECC symbol size is valid
-#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
-  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
-    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
-      #error   BLDCFG: Invalid Ecc symbol size set
-    #endif
-  #endif
-#endif
-// Ensure power down mode is valid
-#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
-  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
-    #if AGESA_ENTRY_INIT_POST == TRUE
-      #error     BLDCFG: Invalid power down mode set
-    #endif
-  #endif
-#endif
-
-// Ensure P-state dependence settings do not conflict
-#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyDependent) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
-  #error     BLDCFG: Conflict P-state dependency settings between BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT and BLDCFG_ACPI_PSTATES_PSD_POLICY.
-#endif
-
-#if ((CFG_HTC_TEMPERATURE_LIMIT == 0) && (CFG_LHTC_TEMPERATURE_LIMIT != 0))
-  #error     BLDCFG: Cannot define BLDCFG_LHTC_TEMPERATURE_LIMIT unless BLDCFG_HTC_TEMPERATURE_LIMIT is also not zero.
-#endif
-
-#if ((CFG_LHTC_TEMPERATURE_LIMIT == 0) && (CFG_HTC_TEMPERATURE_LIMIT != 0))
-  #error     BLDCFG: Cannot define BLDCFG_HTC_TEMPERATURE_LIMIT unless BLDCFG_LHTC_TEMPERATURE_LIMIT is also not zero.
-#endif
-
-
-
-/*****************************************************************************
- *
- * Process the option logic, setting local control variables
- *
- ****************************************************************************/
-#if OPTION_ACPI_PSTATES == TRUE
-  #define OPTFCN_ACPI_TABLES           CreateAcpiTablesMain
-  #define OPTFCN_GATHER_DATA           PStateGatherData
-  #if OPTION_MULTISOCKET == TRUE
-    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
-  #else
-    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
-  #endif
-#else
-  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
-  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
-  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
-#endif
-
-// Consolidate P-state dependence setings
-#if (CFG_ACPI_PSTATES_PSD_POLICY == PsdPolicyProcessorDefault) && (CFG_ACPI_PSTATE_PSD_INDPX == TRUE)
-  #undef CFG_ACPI_PSTATES_PSD_POLICY
-  #define CFG_ACPI_PSTATES_PSD_POLICY  PsdPolicyIndependent
-#endif
-
-/*****************************************************************************
- *
- * Include the structure definitions for the defaults table structures
- *
- ****************************************************************************/
-#include <CommonReturns.h>
-#include <agesa-entry-cfg.h>
-#include  "Options.h"
-#include  "OptionCpuFamiliesInstall.h"
-#include  "OptionsHt.h"
-#include  "OptionHtInstall.h"
-#include  "OptionMemory.h"
-#include  "OptionMemoryInstall.h"
-#include  "OptionMemoryRecovery.h"
-#include  "OptionMemoryRecoveryInstall.h"
-#include  "OptionCpuFeaturesInstall.h"
-#include  "OptionDmi.h"
-#include  "OptionDmiInstall.h"
-#include  "OptionPstate.h"
-#include  "OptionPstateInstall.h"
-#include  "OptionWhea.h"
-#include  "OptionWheaInstall.h"
-#include  "OptionCrat.h"
-#include  "OptionCratInstall.h"
-#include  "OptionCdit.h"
-#include  "OptionCditInstall.h"
-#include  "OptionSrat.h"
-#include  "OptionSratInstall.h"
-#include  "OptionSlit.h"
-#include  "OptionSlitInstall.h"
-#include  "OptionMultiSocket.h"
-#include  "OptionMultiSocketInstall.h"
-#include  "OptionIdsInstall.h"
-#include  "OptionGfxRecovery.h"
-#include  "OptionGfxRecoveryInstall.h"
-#include  "OptionGnb.h"
-#include  "OptionGnbInstall.h"
-#include  "OptionS3ScriptInstall.h"
-#include  "OptionFchInstall.h"
-#include  "OptionMmioMapInstall.h"
-#include  "OptionPrefetchModeInstall.h"
-
-
-/*****************************************************************************
- *
- *  Generate the output structures (defaults tables)
- *
- ****************************************************************************/
-
-FCH_PLATFORM_POLICY  FchUserOptions = {
-  CFG_SMBUS0_BASE_ADDRESS,              // CfgSmbus0BaseAddress
-  CFG_SMBUS1_BASE_ADDRESS,              // CfgSmbus1BaseAddress
-  CFG_SIO_PME_BASE_ADDRESS,             // CfgSioPmeBaseAddress
-  CFG_ACPI_PM1_EVT_BLOCK_ADDRESS,       // CfgAcpiPm1EvtBlkAddr
-  CFG_ACPI_PM1_CNT_BLOCK_ADDRESS,       // CfgAcpiPm1CntBlkAddr
-  CFG_ACPI_PM_TMR_BLOCK_ADDRESS,        // CfgAcpiPmTmrBlkAddr
-  CFG_ACPI_CPU_CNT_BLOCK_ADDRESS,       // CfgCpuControlBlkAddr
-  CFG_ACPI_GPE0_BLOCK_ADDRESS,          // CfgAcpiGpe0BlkAddr
-  CFG_SMI_CMD_PORT_ADDRESS,             // CfgSmiCmdPortAddr
-  CFG_ACPI_PMA_CNTBLK_ADDRESS,          // CfgAcpiPmaCntBlkAddr
-  CFG_GEC_SHADOW_ROM_BASE,              // CfgGecShadowRomBase
-  CFG_WATCHDOG_TIMER_BASE,              // CfgWatchDogTimerBase
-  CFG_SPI_ROM_BASE_ADDRESS,             // CfgSpiRomBaseAddress
-  CFG_HPET_BASE_ADDRESS,                // CfgHpetBaseAddress
-  0x780D1022ul,
-  CFG_SMBUS_SSID,                       // CfgSmbusSsid
-  CFG_IDE_SSID,                         // CfgIdeSsid
-  CFG_SATA_AHCI_SSID,                   // CfgSataAhciSsid
-  CFG_SATA_IDE_SSID,                    // CfgSataIdeSsid
-  CFG_SATA_RAID5_SSID,                  // CfgSataRaid5Ssid
-  CFG_SATA_RAID_SSID,                   // CfgSataRaidSsid
-  CFG_EHCI_SSID,                        // CfgEhcidSsid
-  CFG_OHCI_SSID,                        // CfgOhcidSsid
-  CFG_LPC_SSID,                         // CfgLpcSsid
-  CFG_SD_SSID,                          // CfgSdSsid
-  CFG_XHCI_SSID,                        // CfgXhciSsid
-  CFG_FCH_PORT80_BEHIND_PCIB,           // CfgFchPort80BehindPcib
-  CFG_FCH_ENABLE_ACPI_SLEEP_TRAP,       // CfgFchEnableAcpiSleepTrap
-  CFG_FCH_GPP_LINK_CONFIG,              // CfgFchGppLinkConfig
-  CFG_FCH_GPP_PORT0_PRESENT,            // CfgFchGppPort0Present
-  CFG_FCH_GPP_PORT1_PRESENT,            // CfgFchGppPort1Present
-  CFG_FCH_GPP_PORT2_PRESENT,            // CfgFchGppPort2Present
-  CFG_FCH_GPP_PORT3_PRESENT,            // CfgFchGppPort3Present
-  CFG_FCH_GPP_PORT0_HOTPLUG,            // CfgFchGppPort0HotPlug
-  CFG_FCH_GPP_PORT1_HOTPLUG,            // CfgFchGppPort1HotPlug
-  CFG_FCH_GPP_PORT2_HOTPLUG,            // CfgFchGppPort2HotPlug
-  CFG_FCH_GPP_PORT3_HOTPLUG,            // CfgFchGppPort3HotPlug
-
-  CFG_FCH_ESATA_PORT_BITMAP,            // CfgFchEsataPortBitMap
-  CFG_FCH_IR_PIN_CONTROL,               // CfgFchIrPinControl
-  CFG_FCH_SD_CLOCK_CONTROL,             // CfgFchSdClockControl
-  CFG_FCH_SCI_MAP_LIST,                 // *CfgFchSciMapControl
-  CFG_FCH_SATA_PHY_LIST,                // *CfgFchSataPhyControl
-  CFG_FCH_GPIO_CONTROL_LIST,            // *CfgFchGpioControl
-  CFG_FCH_RTC_WORKAROUND                // CfgFchRtcWorkaround
-};
-
-BUILD_OPT_CFG UserOptions = {
-  {                                             // AGESA version string
-    AGESA_CODE_SIGNATURE,                       //    code header Signature
-    AGESA_PACKAGE_STRING,                       //    16 character ID
-    AGESA_VERSION_STRING,                       //    12 character version string
-    0                                           //    null string terminator
-  },
-  //Build Option Area
-  OPTION_UDIMMS,                        //UDIMMS
-  OPTION_RDIMMS,                        //RDIMMS
-  OPTION_LRDIMMS,                       //LRDIMMS
-  OPTION_ECC,                           //ECC
-  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
-  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
-  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
-  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
-  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
-  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
-  OPTION_MULTISOCKET,                   //MULTISOCKET
-  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
-  OPTION_CPU_PSTATE_HPC_MODE,           //High Preformace Computing (HPC) mode
-  OPTION_CRAT,                          //CRAT
-  OPTION_CDIT,                          //CDIT
-  OPTION_SRAT,                          //SRAT
-  OPTION_SLIT,                          //SLIT
-  OPTION_WHEA,                          //WHEA
-  OPTION_DMI,                           //DMI
-  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
-  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
-
-  //Build Configuration Area
-  CFG_PCI_MMIO_BASE,
-  CFG_PCI_MMIO_SIZE,
-  {
-    // CoreVrm
-    {
-      CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
-      CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
-      CFG_VRM_SLEW_RATE,                  // VrmSlewRate
-      CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
-      CFG_VRM_MAXIMUM_CURRENT_LIMIT,      // VrmMaximumCurrentLimit
-      CFG_VRM_SVI_OCP_LEVEL               // VrmSviOcpLevel
-    },
-    // NbVrm
-    {
-      CFG_VRM_NB_CURRENT_LIMIT,           // VrmNbCurrentLimit
-      CFG_VRM_NB_LOW_POWER_THRESHOLD,     // VrmNbLowPowerThershold
-      CFG_VRM_NB_SLEW_RATE,               // VrmNbSlewRate
-      CFG_VRM_NB_HIGH_SPEED_ENABLE,       // VrmNbHiSpeedEnable
-      CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT,   // VrmNbMaximumCurrentLimit
-      CFG_VRM_NB_SVI_OCP_LEVEL            // VrmNbSviOcpLevel
-    }
-  },
-  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
-  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
-  CFG_C1E_MODE,                         //C1eMode
-  CFG_C1E_OPDATA,                       //C1ePlatformData
-  CFG_C1E_OPDATA1,                      //C1ePlatformData1
-  CFG_C1E_OPDATA2,                      //C1ePlatformData2
-  CFG_C1E_OPDATA3,                      //C1ePlatformData3
-  CFG_CSTATE_MODE,                      //CStateMode
-  CFG_CSTATE_OPDATA,                    //CStatePlatformData
-  CFG_CSTATE_IO_BASE_ADDRESS,           //CStateIoBaseAddress
-  CFG_CPB_MODE,                         //CpbMode
-  LOW_POWER_PSTATE_FOR_PROCHOT_AUTO,    //Low power Pstate for PROCHOT, it's always set to 'AUTO'
-  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
-  {
-    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
-    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
-    CFG_USE_ATM_MODE,                     // CfgUseAtmMode
-    CFG_USE_NBR_CACHE,                    // CfgUseNbrCache
-    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
-    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
-    // ADVANCED_PERFORMANCE_PROFILE
-    {
-      CFG_PERFORMANCE_HARDWARE_PREFETCHER,  // Hardware prefetcher mode
-      CFG_PERFORMANCE_SOFTWARE_PREFETCHES,  // Software prefetcher mode
-      CFG_PERFORMANCE_DRAM_PREFETCHER       // Dram prefetcher mode
-    },
-    CFG_PLATFORM_POWER_POLICY_MODE,       // The platform's power policy mode.
-    CFG_NB_PSTATES_SUPPORTED              // The Nb-Pstates is supported or not
-  },
-  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,         // Deemphasis settings
-  CFG_AMD_PLATFORM_TYPE,                // CfgAmdPlatformType
-  CFG_AMD_POWER_CEILING,                // CfgAmdPowerCeiling
-  CFG_HTC_TEMPERATURE_LIMIT,            // CfgHtcTemperatureLimit
-  CFG_LHTC_TEMPERATURE_LIMIT,           // CfgLhtcTemperatureLimit
-
-  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
-  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
-  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
-  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
-  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
-  CFG_MEMORY_LRDIMM_CAPABLE,            // CfgMemoryLRDimmCapable
-  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
-  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
-  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
-  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
-  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
-  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
-  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
-  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
-  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
-  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
-  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
-  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
-  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
-  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
-  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
-  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
-  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
-  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
-  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
-  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
-  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
-  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
-  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
-  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
-  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
-  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
-  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
-  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
-  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
-  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
-  CFG_ACPI_PSTATES_PSD_POLICY,          // CfgAcpiPstatesPsdPolicy
-  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
-  CFG_UMA_MODE,                         // CfgUmaMode
-  CFG_UMA_SIZE,                         // CfgUmaSize
-  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
-  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
-  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
-  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
-  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
-  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
-  CFG_ABM_SUPPORT,                      // CfgAbmSupport
-  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
-  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
-  CFG_GNB_STEREO_3D_PINOUT,             // CfgGnb3dStereoPinIndex
-  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
-  CFG_GNB_IGPU_SSID,                    // CfgGnbIGPUSSID
-  CFG_GNB_HDAUDIO_SSID,                 // CfgGnbHDAudioSSID
-  CFG_GNB_PCIE_SSID,                    // CfgGnbPcieSSID
-  CFG_GFX_LVDS_SPREAD_SPECTRUM,         // CfgLvdsSpreadSpectrum
-  CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE,    // CfgLvdsSpreadSpectrumRate
-
-  &FchUserOptions,                      // FchBldCfg
-
-  CFG_IOMMU_SUPPORT,                    // CfgIommuSupport
-  CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE,    // CfgLvdsPowerOnSeqDigonToDe
-  CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL,  // CfgLvdsPowerOnSeqDeToVaryBl
-  CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON,    // CfgLvdsPowerOnSeqDeToDigon
-  CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
-  CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
-  CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
-  CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
-  CFG_LVDS_MAX_PIXEL_CLOCK_FREQ,        // CfgLvdsMaxPixelClockFreq
-  CFG_LCD_BIT_DEPTH_CONTROL_VALUE,      // CfgLcdBitDepthControlValue
-  CFG_LVDS_24BBP_PANEL_MODE,            // CfgLvds24bbpPanelMode
-  {{
-    CFG_LVDS_MISC_888_FPDI_MODE,          // CfgLvdsMiscControl
-    CFG_LVDS_MISC_DL_CH_SWAP,             // CfgLvdsMiscControl
-    CFG_LVDS_MISC_VSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
-    CFG_LVDS_MISC_HSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
-    CFG_LVDS_MISC_BLON_ACTIVE_LOW,        // CfgLvdsMiscControl
-    CFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE,  // CfgLvdsMiscControl
-  }},
-  CFG_PCIE_REFCLK_SPREAD_SPECTRUM,      // CfgPcieRefClkSpreadSpectrum
-  CFG_ENABLE_EXTERNAL_VREF,             // CfgExternalVrefCtlFeature
-  CFG_FORCE_TRAIN_MODE,                 // CfgForceTrainMode
-  CFG_GNB_REMOTE_DISPLAY_SUPPORT,       // CfgGnbRemoteDisplaySupport
-  (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
-  CFG_GNB_SYNCFLOOD_PIN_AS_NMI,         // CfgGnbSyncFloodPinAsNmi
-  CFG_IGPU_ENABLE_DISABLE_POLICY,       // CfgIgpuEnableDisablePolicy
-  CFG_GNB_THERMAL_SENSOR_CORRECTION,    // CfgGnbSwTjOffset
-  CFG_LVDS_MISC_VOLT_ADJUSTMENT,        // CfgLvdsMiscVoltAdjustment
-  {{
-    0,                                       // Reserved
-    CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE, // CfgDisplayMiscControl.VbiosFastBootEn
-    0,                                       // Reserved
-  }},
-  CFG_DP_FIXED_VOLT_SWING,              // CfgDpFixedVoltSwingType
-  CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG,   // CfgDimmTypeUsedInMixedConfig
-  CFG_HYBRID_BOOST_ENABLE,              // CfgHybridBoostEnable
-  CFG_GNB_IOAPIC_ADDRESS,               // CfgGnbIoapicAddress
-  CFG_ENABLE_DATA_EYE,                  // CfgDataEyeEn
-  CFG_DOCKED_TDP_HEADROOM,              // CfgDockedTdpHeadroom
-  CFG_DRAM_DOUBLE_REFRESH_RATE,         // CfgDramDoubleRefreshRateEn
-  0,                                    //reserved...
-};
-
-CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
-{
-  IDS_LATE_RUN_AP_TASK
-  // Get DMI info
-  CPU_DMI_AP_GET_TYPE4_TYPE7
-  // Probe filter enable
-  L3_FEAT_AP_DISABLE_CACHE
-  L3_FEAT_AP_ENABLE_CACHE
-  // Cpu Prefetch Mode
-  CPU_PREFETCH_MODE_AP_TASK
-  { 0, NULL }
-};
-
-#if AGESA_ENTRY_INIT_EARLY == TRUE
-  #if IDSOPT_IDS_ENABLED == TRUE
-    #if IDSOPT_TRACING_ENABLED == TRUE
-      #define MAKE_DBG_STR(x, y)  MAKE_AS_A_STRING(x : y)
-      CONST CHAR8 *BldOptDebugOutput[] = {
-        #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
-          //Build Option Area
-          MAKE_DBG_STR (\nOptUDIMM,             OPTION_UDIMMS)
-          MAKE_DBG_STR (\nOptRDIMM,             OPTION_RDIMMS)
-          MAKE_DBG_STR (\nOptLRDIMM,            OPTION_LRDIMMS)
-          MAKE_DBG_STR (\nOptECC,               OPTION_ECC)
-          MAKE_DBG_STR (\nOptCsIntlv,           OPTION_BANK_INTERLEAVE)
-          MAKE_DBG_STR (\nOptDctIntlv,          OPTION_DCT_INTERLEAVE)
-          MAKE_DBG_STR (\nOptNodeIntlv,         OPTION_NODE_INTERLEAVE)
-          //MAKE_DBG_STR (\nOptParallelTraining,  OPTION_PARALLEL_TRAINING)
-          MAKE_DBG_STR (\nOptOnlineSpare,       OPTION_ONLINE_SPARE)
-          MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
-          MAKE_DBG_STR (\nOptMemRestore,        OPTION_MEM_RESTORE)
-          MAKE_DBG_STR (\nOptMultiSocket,       OPTION_MULTISOCKET)
-          MAKE_DBG_STR (\nOptPstates,           OPTION_ACPI_PSTATES)
-          MAKE_DBG_STR (\nOptSRAT,              OPTION_SRAT)
-          MAKE_DBG_STR (\nOptSLIT,              OPTION_SLIT)
-          MAKE_DBG_STR (\nOptWHEA,              OPTION_WHEA)
-          MAKE_DBG_STR (\nOptDMI,               OPTION_DMI)
-          MAKE_DBG_STR (\nOptEarlySamples,      OPTION_EARLY_SAMPLES),
-
-          //Build Configuration Area
-          // CoreVrm
-          MAKE_DBG_STR (\nVrmCurrentLimit      , CFG_VRM_CURRENT_LIMIT)
-          MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
-          MAKE_DBG_STR (\nVrmSlewRate          , CFG_VRM_SLEW_RATE)
-          MAKE_DBG_STR (\nVrmHiSpeedEnable     , CFG_VRM_HIGH_SPEED_ENABLE)
-          MAKE_DBG_STR (\nVrmMaximumCurrentLimit, CFG_VRM_MAXIMUM_CURRENT_LIMIT)
-          MAKE_DBG_STR (\nVrmSviOcpLevel,        CFG_VRM_SVI_OCP_LEVEL)
-          // NbVrm
-          MAKE_DBG_STR (\nNbVrmCurrentLimit      , CFG_VRM_NB_CURRENT_LIMIT)
-          MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
-          MAKE_DBG_STR (\nNbVrmSlewRate          , CFG_VRM_NB_SLEW_RATE)
-          MAKE_DBG_STR (\nNbVrmHiSpeedEnable     , CFG_VRM_NB_HIGH_SPEED_ENABLE)
-          MAKE_DBG_STR (\nNbVrmMaximumCurrentLimit, CFG_VRM_NB_MAXIMUM_CURRENT_LIMIT),
-          MAKE_DBG_STR (\nNbVrmSviOcpLevel,        CFG_VRM_NB_SVI_OCP_LEVEL)
-
-          MAKE_DBG_STR (\nNumIoApics            , CFG_PLAT_NUM_IO_APICS)
-          MAKE_DBG_STR (\nMemInitPstate         , CFG_MEM_INIT_PSTATE)
-          MAKE_DBG_STR (\nC1eMode               , CFG_C1E_MODE)
-          MAKE_DBG_STR (\nC1eOpData             , CFG_C1E_OPDATA)
-          MAKE_DBG_STR (\nC1eOpdata1            , CFG_C1E_OPDATA1)
-          MAKE_DBG_STR (\nC1eOpdata2            , CFG_C1E_OPDATA2)
-          MAKE_DBG_STR (\nC1eOpdata3            , CFG_C1E_OPDATA3)
-          MAKE_DBG_STR (\nCStateMode            , CFG_CSTATE_MODE)
-          MAKE_DBG_STR (\nCStateOpData          , CFG_CSTATE_OPDATA)
-          MAKE_DBG_STR (\nCStateIoBaseAddr      , CFG_CSTATE_IO_BASE_ADDRESS)
-          MAKE_DBG_STR (\nCpbMode               , CFG_CPB_MODE)
-          MAKE_DBG_STR (\nCoreLevelingMode      , CFG_CORE_LEVELING_MODE),
-
-          MAKE_DBG_STR (\nControlFlowMode       , CFG_PLATFORM_CONTROL_FLOW_MODE)
-          MAKE_DBG_STR (\nUseHtAssist           , CFG_USE_HT_ASSIST)
-          MAKE_DBG_STR (\nUseAtmMode            , CFG_USE_ATM_MODE)
-          MAKE_DBG_STR (\nUse32ByteRefresh      , CFG_USE_32_BYTE_REFRESH)
-          MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
-          MAKE_DBG_STR (\nPowerPolicy           , CFG_PLATFORM_POWER_POLICY_MOD)
-
-          MAKE_DBG_STR (\nDeemphasisList        , CFG_PLATFORM_DEEMPHASIS_LIST)
-
-          MAKE_DBG_STR (\nPciMmioAddr           , CFG_PCI_MMIO_BASE)
-          MAKE_DBG_STR (\nPciMmioSize           , CFG_PCI_MMIO_SIZE)
-          MAKE_DBG_STR (\nPlatformType          , CFG_AMD_PLATFORM_TYPE)
-          MAKE_DBG_STR (\nPowerCeiling          , CFG_AMD_POWER_CEILING),
-          MAKE_DBG_STR (\nHtcTempLimit          , CFG_HTC_TEMPERATURE_LIMIT)
-          MAKE_DBG_STR (\nLhtcTempLimit         , CFG_LHTC_TEMPERATURE_LIMIT)
-
-          MAKE_DBG_STR (\nMemBusFreqLimit       , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
-          MAKE_DBG_STR (\nTimingModeSelect      , CFG_TIMING_MODE_SELECT)
-          MAKE_DBG_STR (\nMemoryClockSelect     , CFG_MEMORY_CLOCK_SELECT)
-
-          MAKE_DBG_STR (\nMemUnganged           , CFG_MEMORY_MODE_UNGANGED)
-          MAKE_DBG_STR (\nQRCap                 , CFG_MEMORY_QUAD_RANK_CAPABLE)
-          MAKE_DBG_STR (\nQRType                , CFG_MEMORY_QUADRANK_TYPE)
-          MAKE_DBG_STR (\nRDimmCap              , CFG_MEMORY_RDIMM_CAPABLE)
-          MAKE_DBG_STR (\nLRDimmCap             , CFG_MEMORY_LRDIMM_CAPABLE)
-          MAKE_DBG_STR (\nUDimmCap              , CFG_MEMORY_UDIMM_CAPABLE)
-          MAKE_DBG_STR (\nSODimmCap             , CFG_MEMORY_SODIMM_CAPABLE)
-          MAKE_DBG_STR (\nDqsTrainingControl    , CFG_DQS_TRAINING_CONTROL)
-          MAKE_DBG_STR (\nIgnoreSpdChecksum     , CFG_IGNORE_SPD_CHECKSUM)
-          MAKE_DBG_STR (\nUseBurstMode          , CFG_USE_BURST_MODE)
-          MAKE_DBG_STR (\nAllMemClkOn           , CFG_MEMORY_ALL_CLOCKS_ON),
-
-          MAKE_DBG_STR (\nPowerDownEn           , CFG_MEMORY_POWER_DOWN)
-          MAKE_DBG_STR (\nPowerDownMode         , CFG_POWER_DOWN_MODE)
-          MAKE_DBG_STR (\nOnlineSpare           , CFG_ONLINE_SPARE)
-          MAKE_DBG_STR (\nAddrParityEn          , CFG_MEMORY_PARITY_ENABLE)
-          MAKE_DBG_STR (\nBankSwizzle           , CFG_BANK_SWIZZLE)
-          MAKE_DBG_STR (\nLimitBelow1TB         , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
-          MAKE_DBG_STR (\nCsIntlvEn             , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
-          MAKE_DBG_STR (\nNodeIntlvEn           , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
-          MAKE_DBG_STR (\nDctIntlvEn            , CFG_MEMORY_CHANNEL_INTERLEAVING),
-
-          MAKE_DBG_STR (\nUmaMode                , CFG_UMA_MODE)
-          MAKE_DBG_STR (\nUmaSize                , CFG_UMA_SIZE)
-          MAKE_DBG_STR (\nUmaAbove4G             , CFG_UMA_ABOVE4G)
-          MAKE_DBG_STR (\nUmaAlignment           , CFG_UMA_ALIGNMENT)
-
-          MAKE_DBG_STR (\nEccEn                 , CFG_ENABLE_ECC_FEATURE)
-          MAKE_DBG_STR (\nEccRedirect           , CFG_ECC_REDIRECTION)
-          MAKE_DBG_STR (\nScrubDramRate         , CFG_SCRUB_DRAM_RATE)
-          MAKE_DBG_STR (\nScrubL2Rate           , CFG_SCRUB_L2_RATE)
-          MAKE_DBG_STR (\nScrubL3Rate           , CFG_SCRUB_L3_RATE)
-          MAKE_DBG_STR (\nScrubIcRate           , CFG_SCRUB_IC_RATE)
-          MAKE_DBG_STR (\nScrubDcRate           , CFG_SCRUB_DC_RATE)
-          MAKE_DBG_STR (\nEccSyncFlood          , CFG_ECC_SYNC_FLOOD)
-          MAKE_DBG_STR (\nEccSymbolSize         , CFG_ECC_SYMBOL_SIZE)
-          MAKE_DBG_STR (\nHeapDramAddress       , CFG_HEAP_DRAM_ADDRESS)
-          MAKE_DBG_STR (\nNodeMem1GBAlign       , CFG_1GB_ALIGN),
-
-          MAKE_DBG_STR (\nS3LateRestore         , CFG_S3_LATE_RESTORE)
-          MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
-          MAKE_DBG_STR (\nAcpiPstatesPsdPolicy  , CFG_ACPI_PSTATES_PSD_POLICY)
-
-          MAKE_DBG_STR (\nApMtrrSettingsList     , CFG_AP_MTRR_SETTINGS_LIST)
-
-          MAKE_DBG_STR (\nProcessorScopeInSb     , CFG_PROCESSOR_SCOPE_IN_SB)
-          MAKE_DBG_STR (\nProcessorScopeName0    , CFG_PROCESSOR_SCOPE_NAME0)
-          MAKE_DBG_STR (\nProcessorScopeName1    , CFG_PROCESSOR_SCOPE_NAME1)
-          MAKE_DBG_STR (\nGnbHdAudio             , CFG_GNB_HD_AUDIO)
-          MAKE_DBG_STR (\nAbmSupport             , CFG_ABM_SUPPORT)
-          MAKE_DBG_STR (\nDynamicRefreshRate     , CFG_DYNAMIC_REFRESH_RATE)
-          MAKE_DBG_STR (\nLcdBackLightControl    , CFG_LCD_BACK_LIGHT_CONTROL)
-          MAKE_DBG_STR (\nGnb3dStereoPinIndex    , CFG_GNB_STEREO_3D_PINOUT)
-          MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
-          MAKE_DBG_STR (\nCfgGnbIGPUSSID         , CFG_GNB_IGPU_SSID)
-          MAKE_DBG_STR (\nCfgGnbHDAudioSSID      , CFG_GNB_HDAUDIO_SSID)
-          MAKE_DBG_STR (\nCfgGnbPcieSSID         , CFG_GNB_PCIE_SSID)
-          MAKE_DBG_STR (\nCfgIommuSupport        , CFG_IOMMU_SUPPORT)
-          MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum  , CFG_GFX_LVDS_SPREAD_SPECTRUM)
-          MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe    , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl   , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon    , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe   , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
-          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
-          MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq      , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
-          MAKE_DBG_STR (\nCfgLcdBitDepthControlValue    , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
-          MAKE_DBG_STR (\nCfgLvds24bbpPanelMode         , CFG_LVDS_24BBP_PANEL_MODE),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode   , CFG_LVDS_MISC_888_FPDI_MODE),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap           , CFG_LVDS_MISC_DL_CH_SWAP),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow     , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow     , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
-          MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow      , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
-          MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum   , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
-          MAKE_DBG_STR (\nCfgExtVref                    , CFG_ENABLE_EXTERNAL_VREF),
-          MAKE_DBG_STR (\nCfgForceTrainMode             , CFG_FORCE_TRAIN_MODE),
-          MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport    , CFG_GNB_REMOTE_DISPLAY_CONFIG),
-          MAKE_DBG_STR (\nCfgIvrsExclusionRangeList     , CFG_IOMMU_EXCLUSION_RANGE_LIST),
-          MAKE_DBG_STR (\nCfgGnbSyncFloodPinAsNmi       , CFG_GNB_SYNCFLOOD_PIN_AS_NMI),
-          MAKE_DBG_STR (\nCfgIgpuEnableDisablePolicy    , CFG_IGPU_ENABLE_DISABLE_POLICY),
-          MAKE_DBG_STR (\nCfgGnbSwTjOffset               , CFG_GNB_THERMAL_SENSOR_CORRECTION),
-          MAKE_DBG_STR (\nCfgDisplayMiscControl.VbiosFastBootEn   , CFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE),
-          MAKE_DBG_STR (\nCfgDimmTypeUsedInMixedConfig  , CFG_DIMM_TYPE_USED_IN_MIXED_CONFIG),
-          MAKE_DBG_STR (\nCfgDataEyeEn                  , CFG_ENABLE_DATA_EYE),
-          MAKE_DBG_STR (\nCfgDramDoubleRefreshRateEn    , CFG_DRAM_DOUBLE_REFRESH_RATE),
-        #endif
-        NULL
-      };
-    #endif
-  #endif
-#endif
-
-// Needed for floating point support, linker expects this symbol to be defined.
-#if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
-  CONST INT32 _fltused = 0;
-#endif
-