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authorPeter Lemenkov <lemenkov@gmail.com>2018-10-19 16:57:27 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-10-23 06:15:43 +0000
commit5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8 (patch)
tree1b23efeb6e987f4886ffd5afa12418234eb988b4 /src/vendorcode/amd/agesa/f16kb/Proc/CPU
parent39315985e89e6ef3e7c01e697faf439280045157 (diff)
downloadcoreboot-5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8.tar.xz
src: Typo fix (cosmetic)
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/CPU')
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c2
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
index db00c58e95..8d2fa344cb 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCpb.c
@@ -141,7 +141,7 @@ F16KbIsCpbSupported (
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for enabling Core Performance Boost.
+ * BSC entry point for enabling Core Performance Boost.
*
* Set up D18F4x15C[BoostSrc] and start the PDMs according to the BKDG.
*
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
index cf1d0d8ee9..714f970d78 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
@@ -85,7 +85,7 @@ STATIC CONST UINT16 ROMDATA MmioLimitLowRegOffset[MMIO_REG_PAIR_NUM] = {0x84, 0x
/*---------------------------------------------------------------------------------------*/
/**
- * BSC entry point for for adding MMIO map
+ * BSC entry point for adding MMIO map
*
* program MMIO base/limit registers
*