vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7

The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.

Use the name Kabini instead of Kerala everywhere.

Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.

Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>

3 files changed, 41 insertions, 8 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
index a035a722c3..57ca222710 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
@@ -77,21 +77,19 @@ ACPI_REG_WRITE FchYangtzeInitEnvHwAcpiMmioTable[] =
   //
   // HPET workaround
   //
-  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
-  {PMIO_BASE >> 8,  FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
+  {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
+  {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0x3D},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x0, 0x04},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40},
   {PMIO_BASE >> 8, FCH_PMIOA_REGC2, (UINT8)~(BIT4), BIT4},
-  {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x07},
+  {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x03},
   {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
   {PMIO_BASE >> 8, 0x74 + 3, (UINT8)~BIT5, 0},
   {PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3},
-  {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6},
   {PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1},
-  {PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0},
   {PMIO_BASE >> 8, 0xDC, 0x7C, BIT1},
 
   {SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1},
@@ -190,6 +188,11 @@ ProgramFchEnvHwAcpiPciReg (
   if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
     RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
   }
+  if ( LocalCfgPtr->Misc.NoneSioKbcSupport ) {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2 + BIT1);
+  } else {
+    RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2);
+  }
   ProgramPcieNativeMode (FchDataPtr);
 }
 
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
index 3db2cbeae1..68c9be79ce 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
@@ -116,6 +116,7 @@ ProgramFchHwAcpiResetP (
   LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
   StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
 
+  RwPmio (FCH_PMIOA_REGC8, AccessWidth8, 0xEF, 0x0, StdHeader);
   RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader);
   RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
   RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
index 5a3833e252..c9b5ffccf6 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
@@ -135,7 +135,18 @@ FchInitResetHwAcpi (
   if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) {
     ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr);
   }
-
+  //
+  // RTC Workaround for Daylight saving time enable bit
+  //
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 );   // Enable DltSavEnable
+  Value = 0x0B;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
+  LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+  Value &= 0xFE;
+  LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
+  RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 );      // Disable DltSavEnable
   //
   // Prevent RTC error
   //
@@ -148,6 +159,7 @@ FchInitResetHwAcpi (
   Value = 0x08;
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
   LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
+
   if ( !LocalCfgPtr->EcKbd ) {
     //
     // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
@@ -156,6 +168,23 @@ FchInitResetHwAcpi (
   }
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
 
+  if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) {
+    Value = RTC_WORKAROUND_SECOND;
+    LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    if ( Value > RTC_VALID_SECOND_VALUE ) {
+      Value = RTC_SECOND_RESET_VALUE;
+      LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    }
+    LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    Value &= RTC_SECOND_LOWER_NIBBLE;
+    if ( Value > RTC_VALID_SECOND_VALUE_LN ) {
+      LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+      Value = RTC_SECOND_RESET_VALUE;
+      LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
+    }
+  }
+
   Value = 0x09;
   LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
   LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
@@ -189,14 +218,14 @@ FchInitResetHwAcpi (
   //
   // PciExpWakeStatus workaround
   //
+  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
+  AsfPort++;
   ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits);
   ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue);
   if ( (GeventValue & GeventEnableBits) != 0 ) {
     Value = 0x40;
     LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
   }
-  ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
-  AsfPort++;
   LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader);
   if ((Value & (BIT2 + BIT0)) != 0) {
     Value = 0x40;